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Searched refs:BAR (Results 1 – 17 of 17) sorted by relevance

/openbmc/openbmc/poky/meta/lib/oeqa/runtime/cases/
H A Dparselogs-ignores-mipsarch.txt11 # pci 0000:00:00.0: BAR 2: can't handle BAR above 4GB (bus address 0x1f00000010)
12 # pci 0000:00:00.0: BAR 5: error updating (0x1105d034 != 0x0100d034)
13 BAR 0: error updating
14 BAR 1: error updating
15 BAR 2: error updating
16 BAR 3: error updating
17 BAR 4: error updating
18 BAR 5: error updating
19 : can't handle BAR above 4GB
H A Dparselogs-ignores-qemuall.txt9 # pci 0000:00:00.0: [Firmware Bug]: reg 0x10: invalid BAR (can't size)
10 # pci 0000:00:00.0: [Firmware Bug]: reg 0x14: invalid BAR (can't size)
11 # pci 0000:00:00.0: [Firmware Bug]: reg 0x18: invalid BAR (can't size)
12 # pci 0000:00:00.0: [Firmware Bug]: reg 0x1c: invalid BAR (can't size)
13 # pci 0000:00:00.0: [Firmware Bug]: reg 0x20: invalid BAR (can't size)
14 # pci 0000:00:00.0: [Firmware Bug]: reg 0x24: invalid BAR (can't size)
15 invalid BAR (can't size)
16 # 6.10+ the invalid BAR warnings are of this format:
17 # pci 0000:00:00.0: [Firmware Bug]: BAR 0: invalid; can't size
18 # pci 0000:00:00.0: [Firmware Bug]: BAR 1: invalid; can't size
[all …]
H A Dparselogs-ignores-qemuppc.txt5 can't handle BAR above 4GB
/openbmc/qemu/docs/specs/
H A Dpci-testdev.rst8 Each of BAR 0+1 can be memory or IO. Guests must detect
9 BAR types and act accordingly.
11 BAR 0+1 size is up to 4K bytes each.
12 BAR 0+1 starts with the following header:
21 * any other value if test not supported on this BAR
24 uint32_t offset; /* read-only, offset in this BAR for a given test */
32 The device is expected to always implement tests 0 to N on each BAR, and to add new
34 detects an access type that it does not support on this BAR, then stop.
36 BAR2 is a 64bit memory BAR, without backing storage. It is disabled
H A Divshmem-spec.rst9 said memory to the guest as a PCI BAR.
59 BAR 0 contains the following registers:
/openbmc/qemu/hw/remote/
H A Dtrace-events12 vfu_bar_register(int i, uint64_t addr, uint64_t size) "vfu: BAR %d: addr 0x%"PRIx64" size 0x%"PRIx6…
13 vfu_bar_rw_enter(const char *op, uint64_t addr) "vfu: %s request for BAR address 0x%"PRIx64""
14 vfu_bar_rw_exit(const char *op, uint64_t addr) "vfu: Finished %s of BAR address 0x%"PRIx64""
/openbmc/qemu/docs/
H A Dpcie_sriov.txt22 A virtual function is different from a physical function in that the BAR
23 space for all VFs are defined by the BAR registers in the PFs SR/IOV
24 capability. All VFs have the same BARs and BAR sizes.
28 <VF BAR start> + <VF number> * <BAR sz> + <offset>
31 setting up a BAR for a VF.
H A Digd-assign.txt44 For #6, ROM either provided via the ROM BAR or romfile= option is needed, this
54 * ROM BAR or romfile is present
86 Failed to mmap 0000:00:02.0 BAR <>. Performance may be slow
/openbmc/qemu/qapi/
H A Dcommon.json76 # An enumeration of options for specifying a PCI BAR
80 # @auto: The PCI BAR for the feature is automatically selected
H A Dpci.json44 # @mem_type_64: if @type is 'memory', true if the BAR is 64-bit
/openbmc/qemu/docs/devel/
H A Dvfio-iommufd.rst146 BAR region yet. Below warning shows for assigned PCI device, it's not a bug.
150 qemu-system-x86_64: warning: IOMMU_IOAS_MAP failed: Bad address, PCI BAR?
H A Dmulti-process.rst368 read-only, but certain registers (especially BAR and MSI-related ones)
501 those handlers with a PCI BAR, as they do within QEMU currently.
506 accomplish that, guest BAR programming must also be forwarded from QEMU
629 | id | range ID (e.g., PCI BAR) |
730 when a guest changes a device's PCI BAR registers.
893 config space. Much like the BAR case above, the proxy object must look
/openbmc/openbmc/poky/bitbake/doc/bitbake-user-manual/
H A Dbitbake-user-manual-metadata.rst170 assignment, ``BAR`` expands to the literal string "${FOO}" as long as
173 BAR = "${FOO}"
1288 d.appendVar('BAR',' bar 2')
1291 BAR = "bar 1"
1297 BAR = "bar 1"
1299 BAR += "bar 2"
1302 ``BAR`` with the value "bar 1 bar 2". Just as in the second snippet, the
1560 bar = origenv.getVar("BAR", False)
1562 The previous example returns ``BAR`` from the original execution
/openbmc/u-boot/arch/sh/include/asm/
H A Dcpu_sh7722.h206 #define BAR 0xA4150040 macro
/openbmc/qemu/docs/system/devices/
H A Dnvme.rst163 This adds a Controller Memory Buffer of the given size at offset zero in BAR
H A Dcxl.rst27 - BAR mapped memory accesses used for registers and mailboxes.
/openbmc/openbmc/meta-openembedded/meta-oe/recipes-support/anthy/anthy/
H A D2ch_t.patch3609 +�С� #JN BAR