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Searched refs:ATTR05__ATTR_PAL__SHIFT (Results 1 – 19 of 19) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_sh_mask.h391 #define ATTR05__ATTR_PAL__SHIFT 0x00000000 macro
H A Ddce_8_0_sh_mask.h10890 #define ATTR05__ATTR_PAL__SHIFT 0x0 macro
H A Ddce_10_0_sh_mask.h11274 #define ATTR05__ATTR_PAL__SHIFT 0x0 macro
H A Ddce_11_0_sh_mask.h11086 #define ATTR05__ATTR_PAL__SHIFT 0x0 macro
H A Ddce_11_2_sh_mask.h12340 #define ATTR05__ATTR_PAL__SHIFT 0x0 macro
H A Ddce_12_0_sh_mask.h64733 #define ATTR05__ATTR_PAL__SHIFT … macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_0_3_sh_mask.h27454 #define ATTR05__ATTR_PAL__SHIFT … macro
H A Ddcn_3_0_1_sh_mask.h45481 #define ATTR05__ATTR_PAL__SHIFT … macro
H A Ddcn_2_1_0_sh_mask.h48758 #define ATTR05__ATTR_PAL__SHIFT … macro
H A Ddcn_3_2_1_sh_mask.h48700 #define ATTR05__ATTR_PAL__SHIFT … macro
H A Ddcn_1_0_sh_mask.h46394 #define ATTR05__ATTR_PAL__SHIFT … macro
H A Ddcn_3_1_2_sh_mask.h52881 #define ATTR05__ATTR_PAL__SHIFT … macro
H A Ddcn_3_1_5_sh_mask.h51961 #define ATTR05__ATTR_PAL__SHIFT … macro
H A Ddcn_3_1_6_sh_mask.h54693 #define ATTR05__ATTR_PAL__SHIFT … macro
H A Ddcn_3_0_2_sh_mask.h54501 #define ATTR05__ATTR_PAL__SHIFT … macro
H A Ddcn_3_1_4_sh_mask.h389 #define ATTR05__ATTR_PAL__SHIFT … macro
H A Ddcn_3_0_0_sh_mask.h63079 #define ATTR05__ATTR_PAL__SHIFT … macro
H A Ddcn_2_0_0_sh_mask.h60005 #define ATTR05__ATTR_PAL__SHIFT … macro
H A Ddcn_3_2_0_sh_mask.h48702 #define ATTR05__ATTR_PAL__SHIFT … macro