1 /*
2 * ASPEED AST2400 I2C Controller
3 *
4 * Copyright (C) 2016 IBM Corp.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19 */
20
21 #ifndef ASPEED_I2C_H
22 #define ASPEED_I2C_H
23
24 #include "hw/i2c/i2c.h"
25 #include "hw/sysbus.h"
26 #include "hw/registerfields.h"
27 #include "qom/object.h"
28
29 #define TYPE_ASPEED_I2C "aspeed.i2c"
30 #define TYPE_ASPEED_2400_I2C TYPE_ASPEED_I2C "-ast2400"
31 #define TYPE_ASPEED_2500_I2C TYPE_ASPEED_I2C "-ast2500"
32 #define TYPE_ASPEED_2600_I2C TYPE_ASPEED_I2C "-ast2600"
33 #define TYPE_ASPEED_1030_I2C TYPE_ASPEED_I2C "-ast1030"
34 #define TYPE_ASPEED_2700_I2C TYPE_ASPEED_I2C "-ast2700"
35 OBJECT_DECLARE_TYPE(AspeedI2CState, AspeedI2CClass, ASPEED_I2C)
36
37 #define ASPEED_I2C_NR_BUSSES 16
38 #define ASPEED_I2C_SHARE_POOL_SIZE 0x800
39 #define ASPEED_I2C_BUS_POOL_SIZE 0x20
40 #define ASPEED_I2C_OLD_NUM_REG 11
41 #define ASPEED_I2C_NEW_NUM_REG 28
42
43 #define A_I2CD_M_STOP_CMD BIT(5)
44 #define A_I2CD_M_RX_CMD BIT(3)
45 #define A_I2CD_M_TX_CMD BIT(1)
46 #define A_I2CD_M_START_CMD BIT(0)
47
48 #define A_I2CD_MASTER_EN BIT(0)
49
50 /* Tx State Machine */
51 #define I2CD_TX_STATE_MASK 0xf
52 #define I2CD_IDLE 0x0
53 #define I2CD_MACTIVE 0x8
54 #define I2CD_MSTART 0x9
55 #define I2CD_MSTARTR 0xa
56 #define I2CD_MSTOP 0xb
57 #define I2CD_MTXD 0xc
58 #define I2CD_MRXACK 0xd
59 #define I2CD_MRXD 0xe
60 #define I2CD_MTXACK 0xf
61 #define I2CD_SWAIT 0x1
62 #define I2CD_SRXD 0x4
63 #define I2CD_STXACK 0x5
64 #define I2CD_STXD 0x6
65 #define I2CD_SRXACK 0x7
66 #define I2CD_RECOVER 0x3
67
68 /* I2C Global Register */
69 REG32(I2C_CTRL_STATUS, 0x0) /* Device Interrupt Status */
70 REG32(I2C_CTRL_ASSIGN, 0x8) /* Device Interrupt Target Assignment */
71 REG32(I2C_CTRL_GLOBAL, 0xC) /* Global Control Register */
72 FIELD(I2C_CTRL_GLOBAL, REG_MODE, 2, 1)
73 FIELD(I2C_CTRL_GLOBAL, SRAM_EN, 0, 1)
74 REG32(I2C_CTRL_NEW_CLK_DIVIDER, 0x10) /* New mode clock divider */
75
76 /* I2C Old Mode Device (Bus) Register */
77 REG32(I2CD_FUN_CTRL, 0x0) /* I2CD Function Control */
78 FIELD(I2CD_FUN_CTRL, POOL_PAGE_SEL, 20, 3) /* AST2400 */
79 SHARED_FIELD(M_SDA_LOCK_EN, 16, 1)
80 SHARED_FIELD(MULTI_MASTER_DIS, 15, 1)
81 SHARED_FIELD(M_SCL_DRIVE_EN, 14, 1)
82 SHARED_FIELD(MSB_STS, 9, 1)
83 SHARED_FIELD(SDA_DRIVE_IT_EN, 8, 1)
84 SHARED_FIELD(M_SDA_DRIVE_IT_EN, 7, 1)
85 SHARED_FIELD(M_HIGH_SPEED_EN, 6, 1)
86 SHARED_FIELD(DEF_ADDR_EN, 5, 1)
87 SHARED_FIELD(DEF_ALERT_EN, 4, 1)
88 SHARED_FIELD(DEF_ARP_EN, 3, 1)
89 SHARED_FIELD(DEF_GCALL_EN, 2, 1)
90 SHARED_FIELD(SLAVE_EN, 1, 1)
91 SHARED_FIELD(MASTER_EN, 0, 1)
92 REG32(I2CD_AC_TIMING1, 0x04) /* Clock and AC Timing Control #1 */
93 REG32(I2CD_AC_TIMING2, 0x08) /* Clock and AC Timing Control #2 */
94 REG32(I2CD_INTR_CTRL, 0x0C) /* I2CD Interrupt Control */
95 REG32(I2CD_INTR_STS, 0x10) /* I2CD Interrupt Status */
96 SHARED_FIELD(SLAVE_ADDR_MATCH, 31, 1) /* 0: addr1 1: addr2 */
97 SHARED_FIELD(SLAVE_ADDR_RX_PENDING, 29, 1)
98 SHARED_FIELD(SLAVE_INACTIVE_TIMEOUT, 15, 1)
99 SHARED_FIELD(SDA_DL_TIMEOUT, 14, 1)
100 SHARED_FIELD(BUS_RECOVER_DONE, 13, 1)
101 SHARED_FIELD(SMBUS_ALERT, 12, 1) /* Bus [0-3] only */
102 FIELD(I2CD_INTR_STS, SMBUS_ARP_ADDR, 11, 1) /* Removed */
103 FIELD(I2CD_INTR_STS, SMBUS_DEV_ALERT_ADDR, 10, 1) /* Removed */
104 FIELD(I2CD_INTR_STS, SMBUS_DEF_ADDR, 9, 1) /* Removed */
105 FIELD(I2CD_INTR_STS, GCALL_ADDR, 8, 1) /* Removed */
106 FIELD(I2CD_INTR_STS, SLAVE_ADDR_RX_MATCH, 7, 1) /* use RX_DONE */
107 SHARED_FIELD(SCL_TIMEOUT, 6, 1)
108 SHARED_FIELD(ABNORMAL, 5, 1)
109 SHARED_FIELD(NORMAL_STOP, 4, 1)
110 SHARED_FIELD(ARBIT_LOSS, 3, 1)
111 SHARED_FIELD(RX_DONE, 2, 1)
112 SHARED_FIELD(TX_NAK, 1, 1)
113 SHARED_FIELD(TX_ACK, 0, 1)
114 REG32(I2CD_CMD, 0x14) /* I2CD Command/Status */
115 SHARED_FIELD(SDA_OE, 28, 1)
116 SHARED_FIELD(SDA_O, 27, 1)
117 SHARED_FIELD(SCL_OE, 26, 1)
118 SHARED_FIELD(SCL_O, 25, 1)
119 SHARED_FIELD(TX_TIMING, 23, 2)
120 SHARED_FIELD(TX_STATE, 19, 4)
121 SHARED_FIELD(SCL_LINE_STS, 18, 1)
122 SHARED_FIELD(SDA_LINE_STS, 17, 1)
123 SHARED_FIELD(BUS_BUSY_STS, 16, 1)
124 SHARED_FIELD(SDA_OE_OUT_DIR, 15, 1)
125 SHARED_FIELD(SDA_O_OUT_DIR, 14, 1)
126 SHARED_FIELD(SCL_OE_OUT_DIR, 13, 1)
127 SHARED_FIELD(SCL_O_OUT_DIR, 12, 1)
128 SHARED_FIELD(BUS_RECOVER_CMD_EN, 11, 1)
129 SHARED_FIELD(S_ALT_EN, 10, 1)
130 /* Command Bits */
131 SHARED_FIELD(RX_DMA_EN, 9, 1)
132 SHARED_FIELD(TX_DMA_EN, 8, 1)
133 SHARED_FIELD(RX_BUFF_EN, 7, 1)
134 SHARED_FIELD(TX_BUFF_EN, 6, 1)
135 SHARED_FIELD(M_STOP_CMD, 5, 1)
136 SHARED_FIELD(M_S_RX_CMD_LAST, 4, 1)
137 SHARED_FIELD(M_RX_CMD, 3, 1)
138 SHARED_FIELD(S_TX_CMD, 2, 1)
139 SHARED_FIELD(M_TX_CMD, 1, 1)
140 SHARED_FIELD(M_START_CMD, 0, 1)
141 REG32(I2CD_DEV_ADDR, 0x18) /* Slave Device Address */
142 SHARED_FIELD(SLAVE_DEV_ADDR1, 0, 7)
143 REG32(I2CD_POOL_CTRL, 0x1C) /* Pool Buffer Control */
144 SHARED_FIELD(RX_COUNT, 24, 6)
145 SHARED_FIELD(RX_SIZE, 16, 5)
146 SHARED_FIELD(TX_COUNT, 8, 5)
147 FIELD(I2CD_POOL_CTRL, OFFSET, 2, 6) /* AST2400 */
148 SHARED_FIELD(BUF_ORGANIZATION, 0, 1) /* AST2600 */
149 REG32(I2CD_BYTE_BUF, 0x20) /* Transmit/Receive Byte Buffer */
150 SHARED_FIELD(RX_BUF, 8, 8)
151 SHARED_FIELD(TX_BUF, 0, 8)
152 REG32(I2CD_DMA_ADDR, 0x24) /* DMA Buffer Address */
153 REG32(I2CD_DMA_LEN, 0x28) /* DMA Transfer Length < 4KB */
154
155 /* I2C New Mode Device (Bus) Register */
156 REG32(I2CC_FUN_CTRL, 0x0)
157 FIELD(I2CC_FUN_CTRL, RB_EARLY_DONE_EN, 22, 1)
158 FIELD(I2CC_FUN_CTRL, DMA_DIS_AUTO_RECOVER, 21, 1)
159 FIELD(I2CC_FUN_CTRL, S_SAVE_ADDR, 20, 1)
160 FIELD(I2CC_FUN_CTRL, M_PKT_RETRY_CNT, 18, 2)
161 /* 17:0 shared with I2CD_FUN_CTRL[17:0] */
162 REG32(I2CC_AC_TIMING, 0x04)
163 REG32(I2CC_MS_TXRX_BYTE_BUF, 0x08)
164 /* 31:16 shared with I2CD_CMD[31:16] */
165 /* 15:0 shared with I2CD_BYTE_BUF[15:0] */
166 REG32(I2CC_POOL_CTRL, 0x0c)
167 /* 31:0 shared with I2CD_POOL_CTRL[31:0] */
168 REG32(I2CM_INTR_CTRL, 0x10)
169 REG32(I2CM_INTR_STS, 0x14)
170 FIELD(I2CM_INTR_STS, PKT_STATE, 28, 4)
171 FIELD(I2CM_INTR_STS, PKT_CMD_TIMEOUT, 18, 1)
172 FIELD(I2CM_INTR_STS, PKT_CMD_FAIL, 17, 1)
173 FIELD(I2CM_INTR_STS, PKT_CMD_DONE, 16, 1)
174 FIELD(I2CM_INTR_STS, BUS_RECOVER_FAIL, 15, 1)
175 /* 14:0 shared with I2CD_INTR_STS[14:0] */
176 REG32(I2CM_CMD, 0x18)
177 FIELD(I2CM_CMD, W1_CTRL, 31, 1)
178 FIELD(I2CM_CMD, PKT_DEV_ADDR, 24, 7)
179 FIELD(I2CM_CMD, HS_MASTER_MODE_LSB, 17, 3)
180 FIELD(I2CM_CMD, PKT_OP_EN, 16, 1)
181 /* 15:0 shared with I2CD_CMD[15:0] */
182 REG32(I2CM_DMA_LEN, 0x1c)
183 FIELD(I2CM_DMA_LEN, RX_BUF_LEN_W1T, 31, 1)
184 FIELD(I2CM_DMA_LEN, RX_BUF_LEN, 16, 11)
185 FIELD(I2CM_DMA_LEN, TX_BUF_LEN_W1T, 15, 1)
186 FIELD(I2CM_DMA_LEN, TX_BUF_LEN, 0, 11)
187 REG32(I2CS_INTR_CTRL, 0x20)
188 FIELD(I2CS_INTR_CTRL, PKT_CMD_FAIL, 17, 1)
189 FIELD(I2CS_INTR_CTRL, PKT_CMD_DONE, 16, 1)
190 REG32(I2CS_INTR_STS, 0x24)
191 /* 31:29 shared with I2CD_INTR_STS[31:29] */
192 FIELD(I2CS_INTR_STS, SLAVE_PARKING_STS, 24, 2)
193 FIELD(I2CS_INTR_STS, SLAVE_ADDR3_NAK, 22, 1)
194 FIELD(I2CS_INTR_STS, SLAVE_ADDR2_NAK, 21, 1)
195 FIELD(I2CS_INTR_STS, SLAVE_ADDR1_NAK, 20, 1)
196 FIELD(I2CS_INTR_STS, SLAVE_ADDR_INDICATOR, 18, 2)
197 FIELD(I2CS_INTR_STS, PKT_CMD_FAIL, 17, 1)
198 FIELD(I2CS_INTR_STS, PKT_CMD_DONE, 16, 1)
199 /* 14:0 shared with I2CD_INTR_STS[14:0] */
200 FIELD(I2CS_INTR_STS, SLAVE_ADDR_RX_MATCH, 7, 1)
201 REG32(I2CS_CMD, 0x28)
202 FIELD(I2CS_CMD, W1_CTRL, 31, 1)
203 FIELD(I2CS_CMD, PKT_MODE_ACTIVE_ADDR, 17, 2)
204 FIELD(I2CS_CMD, PKT_MODE_EN, 16, 1)
205 FIELD(I2CS_CMD, AUTO_NAK_INACTIVE_ADDR, 15, 1)
206 FIELD(I2CS_CMD, AUTO_NAK_ACTIVE_ADDR, 14, 1)
207 /* 13:0 shared with I2CD_CMD[13:0] */
208 REG32(I2CS_DMA_LEN, 0x2c)
209 FIELD(I2CS_DMA_LEN, RX_BUF_LEN_W1T, 31, 1)
210 FIELD(I2CS_DMA_LEN, RX_BUF_LEN, 16, 11)
211 FIELD(I2CS_DMA_LEN, TX_BUF_LEN_W1T, 15, 1)
212 FIELD(I2CS_DMA_LEN, TX_BUF_LEN, 0, 11)
213 REG32(I2CM_DMA_TX_ADDR, 0x30)
214 FIELD(I2CM_DMA_TX_ADDR, ADDR, 0, 31)
215 REG32(I2CM_DMA_RX_ADDR, 0x34)
216 FIELD(I2CM_DMA_RX_ADDR, ADDR, 0, 31)
217 REG32(I2CS_DMA_TX_ADDR, 0x38)
218 FIELD(I2CS_DMA_TX_ADDR, ADDR, 0, 31)
219 REG32(I2CS_DMA_RX_ADDR, 0x3c)
220 FIELD(I2CS_DMA_RX_ADDR, ADDR, 0, 31)
221 REG32(I2CS_DEV_ADDR, 0x40)
222 REG32(I2CM_DMA_LEN_STS, 0x48)
223 FIELD(I2CM_DMA_LEN_STS, RX_LEN, 16, 13)
224 FIELD(I2CM_DMA_LEN_STS, TX_LEN, 0, 13)
225 REG32(I2CS_DMA_LEN_STS, 0x4c)
226 FIELD(I2CS_DMA_LEN_STS, RX_LEN, 16, 13)
227 FIELD(I2CS_DMA_LEN_STS, TX_LEN, 0, 13)
228 REG32(I2CC_DMA_ADDR, 0x50)
229 REG32(I2CC_DMA_LEN, 0x54)
230 /* DMA 64bits */
231 REG32(I2CM_DMA_TX_ADDR_HI, 0x60)
232 FIELD(I2CM_DMA_TX_ADDR_HI, ADDR_HI, 0, 7)
233 REG32(I2CM_DMA_RX_ADDR_HI, 0x64)
234 FIELD(I2CM_DMA_RX_ADDR_HI, ADDR_HI, 0, 7)
235 REG32(I2CS_DMA_TX_ADDR_HI, 0x68)
236 FIELD(I2CS_DMA_TX_ADDR_HI, ADDR_HI, 0, 7)
237 REG32(I2CS_DMA_RX_ADDR_HI, 0x6c)
238 FIELD(I2CS_DMA_RX_ADDR_HI, ADDR_HI, 0, 7)
239
240 struct AspeedI2CState;
241
242 #define TYPE_ASPEED_I2C_BUS "aspeed.i2c.bus"
243 OBJECT_DECLARE_SIMPLE_TYPE(AspeedI2CBus, ASPEED_I2C_BUS)
244 struct AspeedI2CBus {
245 SysBusDevice parent_obj;
246
247 struct AspeedI2CState *controller;
248
249 /* slave mode */
250 I2CSlave *slave;
251
252 MemoryRegion mr;
253 MemoryRegion mr_pool;
254
255 I2CBus *bus;
256 uint8_t id;
257 qemu_irq irq;
258
259 uint32_t regs[ASPEED_I2C_NEW_NUM_REG];
260 uint8_t pool[ASPEED_I2C_BUS_POOL_SIZE];
261 uint64_t dma_dram_offset;
262 };
263
264 struct AspeedI2CState {
265 SysBusDevice parent_obj;
266
267 MemoryRegion iomem;
268 qemu_irq irq;
269
270 uint32_t intr_status;
271 uint32_t ctrl_global;
272 uint32_t new_clk_divider;
273 MemoryRegion pool_iomem;
274 uint8_t share_pool[ASPEED_I2C_SHARE_POOL_SIZE];
275
276 AspeedI2CBus busses[ASPEED_I2C_NR_BUSSES];
277 MemoryRegion *dram_mr;
278 AddressSpace dram_as;
279 };
280
281 #define TYPE_ASPEED_I2C_BUS_SLAVE "aspeed.i2c.slave"
282 OBJECT_DECLARE_SIMPLE_TYPE(AspeedI2CBusSlave, ASPEED_I2C_BUS_SLAVE)
283 struct AspeedI2CBusSlave {
284 I2CSlave i2c;
285 };
286
287 struct AspeedI2CClass {
288 SysBusDeviceClass parent_class;
289
290 uint8_t num_busses;
291 uint8_t reg_size;
292 uint32_t reg_gap_size;
293 uint8_t gap;
294 qemu_irq (*bus_get_irq)(AspeedI2CBus *);
295
296 uint64_t pool_size;
297 hwaddr pool_base;
298 uint32_t pool_gap_size;
299 uint8_t *(*bus_pool_base)(AspeedI2CBus *);
300 bool check_sram;
301 bool has_dma;
302 bool has_share_pool;
303 uint64_t mem_size;
304 bool has_dma64;
305 };
306
aspeed_i2c_is_new_mode(AspeedI2CState * s)307 static inline bool aspeed_i2c_is_new_mode(AspeedI2CState *s)
308 {
309 return FIELD_EX32(s->ctrl_global, I2C_CTRL_GLOBAL, REG_MODE);
310 }
311
aspeed_i2c_bus_pkt_mode_en(AspeedI2CBus * bus)312 static inline bool aspeed_i2c_bus_pkt_mode_en(AspeedI2CBus *bus)
313 {
314 if (aspeed_i2c_is_new_mode(bus->controller)) {
315 return ARRAY_FIELD_EX32(bus->regs, I2CM_CMD, PKT_OP_EN);
316 }
317 return false;
318 }
319
aspeed_i2c_bus_ctrl_offset(AspeedI2CBus * bus)320 static inline uint32_t aspeed_i2c_bus_ctrl_offset(AspeedI2CBus *bus)
321 {
322 if (aspeed_i2c_is_new_mode(bus->controller)) {
323 return R_I2CC_FUN_CTRL;
324 }
325 return R_I2CD_FUN_CTRL;
326 }
327
aspeed_i2c_bus_cmd_offset(AspeedI2CBus * bus)328 static inline uint32_t aspeed_i2c_bus_cmd_offset(AspeedI2CBus *bus)
329 {
330 if (aspeed_i2c_is_new_mode(bus->controller)) {
331 return R_I2CM_CMD;
332 }
333 return R_I2CD_CMD;
334 }
335
aspeed_i2c_bus_dev_addr_offset(AspeedI2CBus * bus)336 static inline uint32_t aspeed_i2c_bus_dev_addr_offset(AspeedI2CBus *bus)
337 {
338 if (aspeed_i2c_is_new_mode(bus->controller)) {
339 return R_I2CS_DEV_ADDR;
340 }
341 return R_I2CD_DEV_ADDR;
342 }
343
aspeed_i2c_bus_intr_ctrl_offset(AspeedI2CBus * bus)344 static inline uint32_t aspeed_i2c_bus_intr_ctrl_offset(AspeedI2CBus *bus)
345 {
346 if (aspeed_i2c_is_new_mode(bus->controller)) {
347 return R_I2CM_INTR_CTRL;
348 }
349 return R_I2CD_INTR_CTRL;
350 }
351
aspeed_i2c_bus_intr_sts_offset(AspeedI2CBus * bus)352 static inline uint32_t aspeed_i2c_bus_intr_sts_offset(AspeedI2CBus *bus)
353 {
354 if (aspeed_i2c_is_new_mode(bus->controller)) {
355 return R_I2CM_INTR_STS;
356 }
357 return R_I2CD_INTR_STS;
358 }
359
aspeed_i2c_bus_pool_ctrl_offset(AspeedI2CBus * bus)360 static inline uint32_t aspeed_i2c_bus_pool_ctrl_offset(AspeedI2CBus *bus)
361 {
362 if (aspeed_i2c_is_new_mode(bus->controller)) {
363 return R_I2CC_POOL_CTRL;
364 }
365 return R_I2CD_POOL_CTRL;
366 }
367
aspeed_i2c_bus_byte_buf_offset(AspeedI2CBus * bus)368 static inline uint32_t aspeed_i2c_bus_byte_buf_offset(AspeedI2CBus *bus)
369 {
370 if (aspeed_i2c_is_new_mode(bus->controller)) {
371 return R_I2CC_MS_TXRX_BYTE_BUF;
372 }
373 return R_I2CD_BYTE_BUF;
374 }
375
aspeed_i2c_bus_dma_len_offset(AspeedI2CBus * bus)376 static inline uint32_t aspeed_i2c_bus_dma_len_offset(AspeedI2CBus *bus)
377 {
378 if (aspeed_i2c_is_new_mode(bus->controller)) {
379 return R_I2CC_DMA_LEN;
380 }
381 return R_I2CD_DMA_LEN;
382 }
383
aspeed_i2c_bus_is_master(AspeedI2CBus * bus)384 static inline bool aspeed_i2c_bus_is_master(AspeedI2CBus *bus)
385 {
386 return SHARED_ARRAY_FIELD_EX32(bus->regs, aspeed_i2c_bus_ctrl_offset(bus),
387 MASTER_EN);
388 }
389
aspeed_i2c_bus_is_enabled(AspeedI2CBus * bus)390 static inline bool aspeed_i2c_bus_is_enabled(AspeedI2CBus *bus)
391 {
392 uint32_t ctrl_reg = aspeed_i2c_bus_ctrl_offset(bus);
393 return SHARED_ARRAY_FIELD_EX32(bus->regs, ctrl_reg, MASTER_EN) ||
394 SHARED_ARRAY_FIELD_EX32(bus->regs, ctrl_reg, SLAVE_EN);
395 }
396
397 I2CBus *aspeed_i2c_get_bus(AspeedI2CState *s, int busnr);
398
399 #endif /* ASPEED_I2C_H */
400