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Searched refs:AR_PHY_TIMING_CTRL4 (Results 1 – 7 of 7) sorted by relevance

/openbmc/linux/drivers/net/wireless/ath/ath9k/
H A Dar9002_calib.c55 REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(0), in ar9002_hw_setup_calibration()
75 REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0), in ar9002_hw_setup_calibration()
88 if (!(REG_READ(ah, AR_PHY_TIMING_CTRL4(0)) & in ar9002_hw_per_calibration()
111 REG_CLR_BIT(ah, AR_PHY_TIMING_CTRL4(0), in ar9002_hw_per_calibration()
253 REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i), in ar9002_hw_iqcalibrate()
256 REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i), in ar9002_hw_iqcalibrate()
265 REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0), in ar9002_hw_iqcalibrate()
H A Dar9002_phy.c225 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0)); in ar9002_hw_spur_mitigate()
233 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal); in ar9002_hw_spur_mitigate()
H A Dar9002_phy.h190 #define AR_PHY_TIMING_CTRL4(_i) (0x9920 + ((_i) << 12)) macro
H A Deeprom_9287.c868 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset, in ath9k_hw_ar9287_set_board_values()
869 (REG_READ(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset) in ath9k_hw_ar9287_set_board_values()
H A Dar5008_phy.c462 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0)); in ar5008_hw_spur_mitigate()
468 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new); in ar5008_hw_spur_mitigate()
H A Deeprom_def.c495 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset, in ath9k_hw_def_set_board_values()
496 (REG_READ(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset) & in ath9k_hw_def_set_board_values()
H A Deeprom_4k.c708 REG_RMW(ah, AR_PHY_TIMING_CTRL4(0), in ath9k_hw_4k_set_gain()