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Searched refs:ARM_FEATURE_EL3 (Results 1 – 18 of 18) sorted by relevance

/openbmc/qemu/target/arm/tcg/
H A Dcpu64.c44 set_feature(&cpu->env, ARM_FEATURE_EL3); in aarch64_a35_initfn()
216 set_feature(&cpu->env, ARM_FEATURE_EL3); in aarch64_a55_initfn()
288 set_feature(&cpu->env, ARM_FEATURE_EL3); in aarch64_a72_initfn()
347 set_feature(&cpu->env, ARM_FEATURE_EL3); in aarch64_a76_initfn()
419 set_feature(&cpu->env, ARM_FEATURE_EL3); in aarch64_a64fx_initfn()
472 if (el < 3 && arm_feature(env, ARM_FEATURE_EL3)) { in access_actlr_w()
593 set_feature(&cpu->env, ARM_FEATURE_EL3); in aarch64_neoverse_n1_initfn()
668 set_feature(&cpu->env, ARM_FEATURE_EL3); in aarch64_neoverse_v1_initfn()
894 set_feature(&cpu->env, ARM_FEATURE_EL3); in aarch64_a710_initfn()
995 set_feature(&cpu->env, ARM_FEATURE_EL3); in aarch64_neoverse_n2_initfn()
H A Dcpu32.c285 set_feature(&cpu->env, ARM_FEATURE_EL3); in arm1176_initfn()
352 set_feature(&cpu->env, ARM_FEATURE_EL3); in cortex_a8_initfn()
420 set_feature(&cpu->env, ARM_FEATURE_EL3); in cortex_a9_initfn()
492 set_feature(&cpu->env, ARM_FEATURE_EL3); in cortex_a7_initfn()
541 set_feature(&cpu->env, ARM_FEATURE_EL3); in cortex_a15_initfn()
961 set_feature(&cpu->env, ARM_FEATURE_EL3); in arm_max_initfn()
H A Dop_helper.c906 assert(arm_feature(env, ARM_FEATURE_EL3)); in HELPER()
1045 } else if (arm_feature(env, ARM_FEATURE_EL3)) { in HELPER()
1121 if (!arm_feature(env, ARM_FEATURE_EL3) && in HELPER()
1152 (smd || !arm_feature(env, ARM_FEATURE_EL3))) { in HELPER()
H A Dhflags.c68 bool ret = (arm_feature(env, ARM_FEATURE_EL3) && in access_secure_reg()
156 if (arm_feature(env, ARM_FEATURE_EL3)) { in sme_fa64()
H A Dpauth_helper.c478 if (el < 3 && arm_feature(env, ARM_FEATURE_EL3)) { in pauth_check_trap()
H A Dtlb-insns.c1298 if (arm_feature(env, ARM_FEATURE_EL3)) { in define_tlb_insn_regs()
H A Dtranslate.c2794 if (!arm_dc_feature(s, ARM_FEATURE_EL3) || s->ns) { in msr_banked_access_decode()
/openbmc/qemu/target/arm/
H A Dcpu.c321 if (arm_feature(env, ARM_FEATURE_EL3)) { in arm_cpu_reset_hold()
364 !arm_feature(env, ARM_FEATURE_EL3)) { in arm_cpu_reset_hold()
584 bool have_el3 = arm_feature(env, ARM_FEATURE_EL3); in arm_emulate_firmware_reset()
1237 if (arm_feature(env, ARM_FEATURE_EL3) && el != 3) { in aarch64_cpu_dump_state()
1434 if (arm_feature(env, ARM_FEATURE_EL3) && in arm_cpu_dump_state()
1754 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { in arm_cpu_post_init()
1880 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { in arm_cpu_post_init()
2333 unset_feature(env, ARM_FEATURE_EL3); in arm_cpu_realizefn()
2522 if (arm_feature(env, ARM_FEATURE_EL3)) { in arm_cpu_realizefn()
H A Darm-powerctl.c140 if (((target_el == 3) && !arm_feature(&target_cpu->env, ARM_FEATURE_EL3)) || in arm_set_cpu_on()
H A Dhelper.c580 if (arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) && in cpacr_write()
597 if (arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) && in cpacr_read()
1032 nsk = arm_feature(env, ARM_FEATURE_EL3) && (filter & PMXEVTYPER_NSK); in pmu_counter_enabled()
1033 nsu = arm_feature(env, ARM_FEATURE_EL3) && (filter & PMXEVTYPER_NSU); in pmu_counter_enabled()
1036 arm_feature(env, ARM_FEATURE_EL3) && (filter & PMXEVTYPER_M); in pmu_counter_enabled()
3363 if (arm_current_el(env) == 2 && arm_feature(env, ARM_FEATURE_EL3) && in gt_cntpoff_access()
4243 } else if (arm_feature(env, ARM_FEATURE_EL3)) { in vmsa_ttbcr_write()
5273 if (arm_feature(env, ARM_FEATURE_EL3)) { in do_hcr_write()
5552 && arm_feature(env, ARM_FEATURE_EL3) in access_hxen()
5590 if (arm_feature(env, ARM_FEATURE_EL3) && !(env->cp15.scr_el3 & SCR_HXEN)) { in arm_hcrx_el2_eff()
[all …]
H A Dinternals.h435 if (arm_feature(env, ARM_FEATURE_EL3)) { in arm_el_is_aa64()
1509 && arm_feature(env, ARM_FEATURE_EL3) in allocation_tag_access_enabled()
1898 (!arm_feature(env, ARM_FEATURE_EL3) || (env->cp15.scr_el3 & SCR_FGTEN)); in arm_fgt_active()
H A Dcpu64.c629 set_feature(&cpu->env, ARM_FEATURE_EL3); in aarch64_a57_initfn()
690 set_feature(&cpu->env, ARM_FEATURE_EL3); in aarch64_a53_initfn()
H A Dgdbstub.c281 if (!arm_feature(env, ARM_FEATURE_EL3) && in arm_register_sysreg_for_feature()
H A Dcpu.h2464 ARM_FEATURE_EL3, /* has EL3 Secure monitor support */ enumerator
2541 if (arm_feature(env, ARM_FEATURE_EL3)) { in arm_is_el3_or_mon()
2654 if (arm_feature(env, ARM_FEATURE_EL3)) { in arm_highest_el()
H A Ddebug_helper.c36 } else if (arm_feature(env, ARM_FEATURE_EL3) && in arm_debug_target_el()
/openbmc/qemu/hw/intc/
H A Darm_gicv3_cpuif.c1061 if (cs->hppi.grp == GICV3_G1 && !arm_feature(env, ARM_FEATURE_EL3)) { in gicv3_cpuif_update()
1114 if (arm_feature(env, ARM_FEATURE_EL3) && !arm_is_secure(env) && in icc_pmr_read()
1143 if (arm_feature(env, ARM_FEATURE_EL3) && !arm_is_secure(env) && in icc_pmr_write()
1683 && arm_feature(env, ARM_FEATURE_EL3) && !arm_is_secure(env)) { in icc_eoir_write()
1874 if (grp == GICV3_G1NS && regno < 2 && arm_feature(env, ARM_FEATURE_EL3)) { in icc_ap_write()
1980 if (arm_feature(env, ARM_FEATURE_EL3) && in icc_rpr_read()
1994 if (arm_feature(env, ARM_FEATURE_EL3) && !arm_is_secure(env)) { in icc_rpr_read()
2201 if (arm_feature(env, ARM_FEATURE_EL3) && in icc_ctlr_el1_write()
3167 assert(!arm_feature(&cpu->env, ARM_FEATURE_EL3)); in gicv3_init_cpuif()
/openbmc/qemu/hw/arm/
H A Dboot.c54 if (arm_feature(&cpu->env, ARM_FEATURE_EL3) && info->secure_boot) { in arm_boot_address_space()
742 if (arm_feature(env, ARM_FEATURE_EL3) && in do_cpu_reset()
1265 if (arm_feature(env, ARM_FEATURE_EL3)) { in arm_load_kernel()
H A Darmv7m.c601 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { in armv7m_load_kernel()