1 #ifndef CPER_SECTION_ARM_H 2 #define CPER_SECTION_ARM_H 3 4 #ifdef __cplusplus 5 extern "C" { 6 #endif 7 8 #include <stdio.h> 9 #include <json.h> 10 #include <libcper/Cper.h> 11 12 #define ARM_SOCK_MASK 0xFF00000000 13 14 #define ARM_ERROR_VALID_BITFIELD_NAMES \ 15 (const char *[]){ "mpidrValid", "errorAffinityLevelValid", \ 16 "runningStateValid", "vendorSpecificInfoValid" } 17 #define ARM_ERROR_INFO_ENTRY_VALID_BITFIELD_NAMES \ 18 (const char *[]){ "multipleErrorValid", "flagsValid", \ 19 "errorInformationValid", "virtualFaultAddressValid", \ 20 "physicalFaultAddressValid" } 21 #define ARM_ERROR_INFO_ENTRY_FLAGS_NAMES \ 22 (const char *[]){ "firstErrorCaptured", "lastErrorCaptured", \ 23 "propagated", "overflow" } 24 #define ARM_CACHE_TLB_ERROR_VALID_BITFIELD_NAMES \ 25 (const char *[]){ \ 26 "transactionTypeValid", "operationValid", \ 27 "levelValid", "processorContextCorruptValid", \ 28 "correctedValid", "precisePCValid", \ 29 "restartablePCValid" \ 30 } 31 #define ARM_BUS_ERROR_VALID_BITFIELD_NAMES \ 32 (const char *[]){ "transactionTypeValid", \ 33 "operationValid", \ 34 "levelValid", \ 35 "processorContextCorruptValid", \ 36 "correctedValid", \ 37 "precisePCValid", \ 38 "restartablePCValid", \ 39 "participationTypeValid", \ 40 "timedOutValid", \ 41 "addressSpaceValid", \ 42 "memoryAttributesValid", \ 43 "accessModeValid" } 44 #define ARM_ERROR_TRANSACTION_TYPES_KEYS (int[]){ 0, 1, 2 } 45 #define ARM_ERROR_TRANSACTION_TYPES_VALUES \ 46 (const char *[]){ "Instruction", "Data Access", "Generic" } 47 #define ARM_ERROR_INFO_ENTRY_INFO_TYPES_KEYS (int[]){ 0, 1, 2, 3 } 48 #define ARM_ERROR_INFO_ENTRY_INFO_TYPES_VALUES \ 49 (const char *[]){ "Cache Error", "TLB Error", "Bus Error", \ 50 "Micro-Architectural Error" } 51 #define ARM_CACHE_BUS_OPERATION_TYPES_KEYS \ 52 (int[]){ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10 } 53 #define ARM_CACHE_BUS_OPERATION_TYPES_VALUES \ 54 (const char *[]){ "Generic Error", "Generic Read", "Generic Write", \ 55 "Data Read", "Data Write", "Instruction Fetch", \ 56 "Prefetch", "Eviction", "Snooping", \ 57 "Snooped", "Management" } 58 #define ARM_TLB_OPERATION_TYPES_KEYS (int[]){ 0, 1, 2, 3, 4, 5, 6, 7, 8 } 59 #define ARM_TLB_OPERATION_TYPES_VALUES \ 60 (const char *[]){ "Generic Error", \ 61 "Generic Read", \ 62 "Generic Write", \ 63 "Data Read", \ 64 "Data Write", \ 65 "Instruction Fetch", \ 66 "Prefetch", \ 67 "Local Management Operation", \ 68 "External Management Operation" } 69 #define ARM_BUS_PARTICIPATION_TYPES_KEYS (int[]){ 0, 1, 2, 3 } 70 #define ARM_BUS_PARTICIPATION_TYPES_VALUES \ 71 (const char *[]){ "Local Processor Originated Request", \ 72 "Local Processor Responded to Request", \ 73 "Local Processor Observed", "Generic" } 74 #define ARM_BUS_ADDRESS_SPACE_TYPES_KEYS (int[]){ 0, 1, 3 } 75 #define ARM_BUS_ADDRESS_SPACE_TYPES_VALUES \ 76 (const char *[]){ "External Memory Access", "Internal Memory Access", \ 77 "Device Memory Access" } 78 #define ARM_PROCESSOR_INFO_REGISTER_CONTEXT_TYPES_KEYS \ 79 (int[]){ 0, 1, 2, 3, 4, 5, 6, 7, 8 } 80 81 #define ARM_PROCESSOR_INFO_REGISTER_CONTEXT_TYPES_VALUES \ 82 (const char *[]){ "AArch32 General Purpose Registers", \ 83 "AArch32 EL1 Context Registers", \ 84 "AArch32 EL2 Context Registers", \ 85 "AArch32 Secure Context Registers", \ 86 "AArch64 General Purpose Registers", \ 87 "AArch64 EL1 Context Registers", \ 88 "AArch64 EL2 Context Registers", \ 89 "AArch64 EL3 Context Registers", \ 90 "Miscellaneous System Register Structure" } 91 92 #define ARM_PROCESSOR_INFO_REGISTER_CONTEXT_TYPES_COUNT 9 93 94 #define ARM_AARCH32_GPR_NAMES \ 95 (const char *[]){ "r0", "r1", "r2", "r3", "r4", "r5", \ 96 "r6", "r7", "r8", "r9", "r10", "r11", \ 97 "r12", "r13_sp", "r14_lr", "r15_pc" } 98 #define ARM_AARCH32_EL1_REGISTER_NAMES \ 99 (const char *[]){ "dfar", "dfsr", "ifar", "isr", \ 100 "mair0", "mair1", "midr", "mpidr", \ 101 "nmrr", "prrr", "sctlr_ns", "spsr", \ 102 "spsr_abt", "spsr_fiq", "spsr_irq", "spsr_svc", \ 103 "spsr_und", "tpidrprw", "tpidruro", "tpidrurw", \ 104 "ttbcr", "ttbr0", "ttbr1", "dacr" } 105 #define ARM_AARCH32_EL2_REGISTER_NAMES \ 106 (const char *[]){ "elr_hyp", "hamair0", "hamair1", "hcr", \ 107 "hcr2", "hdfar", "hifar", "hpfar", \ 108 "hsr", "htcr", "htpidr", "httbr", \ 109 "spsr_hyp", "vtcr", "vttbr", "dacr32_el2" } 110 #define ARM_AARCH32_SECURE_REGISTER_NAMES \ 111 (const char *[]){ "sctlr_s", "spsr_mon" } 112 #define ARM_AARCH64_GPR_NAMES \ 113 (const char *[]){ "x0", "x1", "x2", "x3", "x4", "x5", "x6", \ 114 "x7", "x8", "x9", "x10", "x11", "x12", "x13", \ 115 "x14", "x15", "x16", "x17", "x18", "x19", "x20", \ 116 "x21", "x22", "x23", "x24", "x25", "x26", "x27", \ 117 "x28", "x29", "x30", "sp" } 118 #define ARM_AARCH64_EL1_REGISTER_NAMES \ 119 (const char *[]){ \ 120 "elr_el1", "esr_el1", "far_el1", "isr_el1", \ 121 "mair_el1", "midr_el1", "mpidr_el1", "sctlr_el1", \ 122 "sp_el0", "sp_el1", "spsr_el1", "tcr_el1", \ 123 "tpidr_el0", "tpidr_el1", "tpidrro_el0", "ttbr0_el1", \ 124 "ttbr1_el1" \ 125 } 126 #define ARM_AARCH64_EL2_REGISTER_NAMES \ 127 (const char *[]){ "elr_el2", "esr_el2", "far_el2", "hacr_el2", \ 128 "hcr_el2", "hpfar_el2", "mair_el2", "sctlr_el2", \ 129 "sp_el2", "spsr_el2", "tcr_el2", "tpidr_el2", \ 130 "ttbr0_el2", "vtcr_el2", "vttbr_el2" } 131 #define ARM_AARCH64_EL3_REGISTER_NAMES \ 132 (const char *[]){ "elr_el3", "esr_el3", "far_el3", "mair_el3", \ 133 "sctlr_el3", "sp_el3", "spsr_el3", "tcr_el3", \ 134 "tpidr_el3", "ttbr0_el3" } 135 136 json_object *cper_section_arm_to_ir(const UINT8 *section, UINT32 size); 137 void ir_section_arm_to_cper(json_object *section, FILE *out); 138 139 #ifdef __cplusplus 140 } 141 #endif 142 143 #endif 144