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Searched refs:ARM_CP_STATE_AA64 (Results 1 – 10 of 10) sorted by relevance

/openbmc/qemu/target/arm/tcg/
H A Dtlb-insns.c634 { .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64,
640 { .name = "TLBI_VAE1IS", .state = ARM_CP_STATE_AA64,
646 { .name = "TLBI_ASIDE1IS", .state = ARM_CP_STATE_AA64,
652 { .name = "TLBI_VAAE1IS", .state = ARM_CP_STATE_AA64,
658 { .name = "TLBI_VALE1IS", .state = ARM_CP_STATE_AA64,
664 { .name = "TLBI_VAALE1IS", .state = ARM_CP_STATE_AA64,
670 { .name = "TLBI_VMALLE1", .state = ARM_CP_STATE_AA64,
676 { .name = "TLBI_VAE1", .state = ARM_CP_STATE_AA64,
682 { .name = "TLBI_ASIDE1", .state = ARM_CP_STATE_AA64,
688 { .name = "TLBI_VAAE1", .state = ARM_CP_STATE_AA64,
[all...]
H A Dcpu64.c556 { .name = "ATCR_EL1", .state = ARM_CP_STATE_AA64,
561 { .name = "ATCR_EL2", .state = ARM_CP_STATE_AA64,
564 { .name = "ATCR_EL3", .state = ARM_CP_STATE_AA64,
567 { .name = "ATCR_EL12", .state = ARM_CP_STATE_AA64,
570 { .name = "AVTCR_EL2", .state = ARM_CP_STATE_AA64,
573 { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64, in define_neoverse_v1_cp_reginfo()
577 { .name = "CPUACTLR2_EL1", .state = ARM_CP_STATE_AA64, in define_neoverse_v1_cp_reginfo()
581 { .name = "CPUACTLR3_EL1", .state = ARM_CP_STATE_AA64, in define_neoverse_v1_cp_reginfo()
589 { .name = "CPUCFR_EL1", .state = ARM_CP_STATE_AA64, in aarch64_neoverse_n1_initfn()
592 { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64, in aarch64_neoverse_n1_initfn()
[all...]
H A Dcpregs-at.c390 { .name = "AT_S1E1R", .state = ARM_CP_STATE_AA64,
395 { .name = "AT_S1E1W", .state = ARM_CP_STATE_AA64,
400 { .name = "AT_S1E0R", .state = ARM_CP_STATE_AA64,
405 { .name = "AT_S1E0W", .state = ARM_CP_STATE_AA64,
410 { .name = "AT_S12E1R", .state = ARM_CP_STATE_AA64,
414 { .name = "AT_S12E1W", .state = ARM_CP_STATE_AA64,
418 { .name = "AT_S12E0R", .state = ARM_CP_STATE_AA64,
422 { .name = "AT_S12E0W", .state = ARM_CP_STATE_AA64,
427 { .name = "AT_S1E3R", .state = ARM_CP_STATE_AA64,
431 { .name = "AT_S1E3W", .state = ARM_CP_STATE_AA64,
[all...]
/openbmc/qemu/target/arm/
H A Dcortex-regs.c30 { .name = "L2CTLR_EL1", .state = ARM_CP_STATE_AA64,
38 { .name = "L2ECTLR_EL1", .state = ARM_CP_STATE_AA64,
47 { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64,
53 { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64,
59 { .name = "CPUMERRSR_EL1", .state = ARM_CP_STATE_AA64,
65 { .name = "L2MERRSR_EL1", .state = ARM_CP_STATE_AA64,
H A Dhelper.c720 * passes the reginfo for SCR_EL3, which has type ARM_CP_STATE_AA64. in scr_write()
999 { .name = "MAIR_EL1", .state = ARM_CP_STATE_AA64, in teecr_access()
1008 { .name = "MAIR_EL3", .state = ARM_CP_STATE_AA64, in teehbr_access()
1080 { .name = "TPIDR_EL0", .state = ARM_CP_STATE_AA64, in gt_cntfrq_access()
1091 { .name = "TPIDRRO_EL0", .state = ARM_CP_STATE_AA64, in gt_cntfrq_access()
1103 { .name = "TPIDR_EL1", .state = ARM_CP_STATE_AA64, in gt_cntfrq_access()
2045 { .name = "CNTFRQ_EL0", .state = ARM_CP_STATE_AA64,
2079 { .name = "CNTP_CTL_EL0", .state = ARM_CP_STATE_AA64,
2097 { .name = "CNTV_CTL_EL0", .state = ARM_CP_STATE_AA64,
2121 { .name = "CNTP_TVAL_EL0", .state = ARM_CP_STATE_AA64,
[all...]
H A Dcpregs-pmu.c1030 { .name = "PMCNTENSET_EL0", .state = ARM_CP_STATE_AA64, .type = ARM_CP_IO,
1043 { .name = "PMCNTENCLR_EL0", .state = ARM_CP_STATE_AA64,
1057 { .name = "PMOVSCLR_EL0", .state = ARM_CP_STATE_AA64,
1070 { .name = "PMSWINC_EL0", .state = ARM_CP_STATE_AA64,
1082 { .name = "PMSELR_EL0", .state = ARM_CP_STATE_AA64,
1088 { .name = "PMCCNTR_EL0", .state = ARM_CP_STATE_AA64,
1102 { .name = "PMCCFILTR_EL0", .state = ARM_CP_STATE_AA64,
1115 { .name = "PMXEVTYPER_EL0", .state = ARM_CP_STATE_AA64,
1126 { .name = "PMXEVCNTR_EL0", .state = ARM_CP_STATE_AA64,
1137 { .name = "PMUSERENR_EL0", .state = ARM_CP_STATE_AA64,
[all …]
H A Ddebug_helper.c961 { .name = "MDRAR_EL1", .state = ARM_CP_STATE_AA64,
980 { .name = "MDCCSR_EL0", .state = ARM_CP_STATE_AA64,
999 { .name = "DBGDTRTX_EL0", .state = ARM_CP_STATE_AA64,
1008 { .name = "DBGDTR_EL0", .state = ARM_CP_STATE_AA64,
1115 { .name = "DBGVCR32_EL2", .state = ARM_CP_STATE_AA64,
H A Dcpregs.h268 ARM_CP_STATE_AA64 = 1,
1118 return (ri->state == ARM_CP_STATE_AA64 || (ri->type & ARM_CP_64BIT) in arm_cpreg_in_idspace()
1150 return ri->state == ARM_CP_STATE_AA64 && in arm_cpreg_traps_in_nv()
250 ARM_CP_STATE_AA64 = 1, global() enumerator
H A Dgdbstub.c297 if (ri->state == ARM_CP_STATE_AA64) { in arm_register_sysreg_for_feature()
/openbmc/qemu/hw/intc/
H A Darm_gicv3_cpuif.c2497 { .name = "ICC_SGI1R_EL1", .state = ARM_CP_STATE_AA64,
2509 { .name = "ICC_ASGI1R_EL1", .state = ARM_CP_STATE_AA64,
2521 { .name = "ICC_SGI0R_EL1", .state = ARM_CP_STATE_AA64,