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Searched refs:ARM_CP_STATE_AA32 (Results 1 – 5 of 5) sorted by relevance

/openbmc/qemu/target/arm/
H A Dhelper.c2315 { .name = "MAIR0", .state = ARM_CP_STATE_AA32,
2321 { .name = "MAIR1", .state = ARM_CP_STATE_AA32,
6324 { .name = "HCR", .state = ARM_CP_STATE_AA32,
6399 { .name = "VTCR", .state = ARM_CP_STATE_AA32,
6568 { .name = "HCR2", .state = ARM_CP_STATE_AA32,
9260 .state = ARM_CP_STATE_AA32, in register_cp_regs_for_features()
10008 case ARM_CP_STATE_AA32: in add_cpreg_to_hashtable()
10128 if (state == ARM_CP_STATE_AA32) { in add_cpreg_to_hashtable()
10246 case ARM_CP_STATE_AA32: in define_one_arm_cp_reg_with_opaque()
10267 if (r->state != ARM_CP_STATE_AA32) { in define_one_arm_cp_reg_with_opaque()
[all …]
H A Ddebug_helper.c898 if (ri->state == ARM_CP_STATE_AA32) { in oslar_write()
1008 { .name = "DBGDSCRint", .state = ARM_CP_STATE_AA32,
H A Dgdbstub.c280 if (ri->state == ARM_CP_STATE_AA32) { in arm_register_sysreg_for_feature()
H A Dcpregs.h240 ARM_CP_STATE_AA32 = 0, enumerator
/openbmc/qemu/hw/intc/
H A Darm_gicv3_cpuif.c2792 if (ri->state == ARM_CP_STATE_AA32) { in ich_lr_read()
2819 if (ri->state == ARM_CP_STATE_AA32) { in ich_lr_write()
3148 { .name = "ICH_LRCn_EL2", .state = ARM_CP_STATE_AA32, in gicv3_init_cpuif()