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Searched refs:ARM_CP_CONST (Results 1 – 11 of 11) sorted by relevance

/openbmc/qemu/target/arm/
H A Dcortex-regs.c40 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
43 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
46 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
49 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
52 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
55 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
58 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
61 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
64 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
67 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
[all …]
H A Ddebug_helper.c960 .type = ARM_CP_CONST | ARM_CP_NO_GDB, .resetvalue = 0 },
964 .type = ARM_CP_CONST, .resetvalue = 0 },
967 .type = ARM_CP_CONST | ARM_CP_NO_GDB, .resetvalue = 0 },
983 .type = ARM_CP_CONST, .resetvalue = 0 },
993 .type = ARM_CP_CONST, .resetvalue = 0 },
997 .type = ARM_CP_CONST, .resetvalue = 0 },
1002 .type = ARM_CP_CONST, .resetvalue = 0 },
1006 .type = ARM_CP_CONST, .resetvalue = 0 },
1011 .type = ARM_CP_CONST, .resetvalue = 0 },
1033 .type = ARM_CP_CONST | ARM_CP_NO_GDB, .resetvalue = 0 },
[all …]
H A Dhelper.c103 if (ri->type & ARM_CP_CONST) { in raw_accessors_invalid()
123 if (ri->type & ARM_CP_CONST) {
148 if ((ri->type & ARM_CP_CONST) || in write_cpustate_to_list()
532 .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW, in cpacr_write()
541 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 }, in cpacr_write()
678 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, }, in vbar_write()
971 .access = PL1_R, .type = ARM_CP_CONST,
986 .type = ARM_CP_CONST, .resetvalue = 0 }, in teecr_write()
994 .type = ARM_CP_CONST, .resetvalue = 0 }, in teecr_access()
2991 .type = ARM_CP_CONST | ARM_CP_OVERRID
[all...]
H A Dcpregs-pmu.c1291 .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, in define_pm_cpregs()
1296 .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, in define_pm_cpregs()
1301 .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, in define_pm_cpregs()
1306 .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, in define_pm_cpregs()
1324 .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, in define_pm_cpregs()
1329 .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, in define_pm_cpregs()
1340 .access = PL1_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, in define_pm_cpregs()
H A Dcpregs.h60 ARM_CP_CONST = 1 << 4,
983 * Value of this register, if it is ARM_CP_CONST. Otherwise, if
990 * 1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs
51 ARM_CP_CONST = 1 << 4, global() enumerator
/openbmc/qemu/target/arm/tcg/
H A Dcpu64.c558 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
563 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
566 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
569 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
572 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
575 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, in define_neoverse_v1_cp_reginfo()
579 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, in define_neoverse_v1_cp_reginfo()
583 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, in aarch64_neoverse_n1_initfn()
591 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 4 }, in aarch64_neoverse_n1_initfn()
594 .access = PL1_RW, .type = ARM_CP_CONST, in aarch64_neoverse_n1_initfn()
[all...]
H A Dcpu32.c337 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
339 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
398 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
405 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
407 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
409 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
477 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
581 .access = PL1_RW, .type = ARM_CP_CONST },
583 .access = PL1_RW, .type = ARM_CP_CONST },
621 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BI
[all...]
H A Dtranslate.c1885 if (ri->type & ARM_CP_CONST) { in disas_iwmmxt_insn()
1905 if (ri->type & ARM_CP_CONST) { in disas_iwmmxt_insn()
1927 if (ri->type & ARM_CP_CONST) { in disas_iwmmxt_insn()
H A Dtranslate-a64.c3103 if (ri->type & ARM_CP_CONST) { in gen_compare_and_swap_pair()
3114 if (ri->type & ARM_CP_CONST) { in gen_compare_and_swap_pair()
/openbmc/qemu/hw/intc/
H A Darm_gicv3_cpuif.c2569 .type = ARM_CP_NO_RAW | ARM_CP_CONST,
2597 .type = ARM_CP_NO_RAW | ARM_CP_CONST,
2613 .type = ARM_CP_NO_RAW | ARM_CP_CONST,
/openbmc/qemu/target/arm/hvf/
H A Dhvf.c1170 if (ri->type & ARM_CP_CONST) { in hvf_handle_psci_call()