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Searched refs:ARM_CP_64BIT (Results 1 – 9 of 9) sorted by relevance

/openbmc/qemu/target/arm/
H A Dcortex-regs.c52 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
58 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
64 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
70 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
H A Dhelper.c2140 .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_IO,
2150 .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_IO,
2163 .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS,
2172 .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS,
2189 .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS,
2241 .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_IO, in gt_virt_cnt_read()
2251 .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_IO,
3022 .access = PL1_W, .type = ARM_CP_NOP | ARM_CP_64BIT }, in midr_read()
3024 .access = PL1_W, .type = ARM_CP_NOP | ARM_CP_64BIT },
3026 .access = PL0_W, .type = ARM_CP_NOP | ARM_CP_64BIT }, in mpidr_read_val()
[all...]
H A Ddebug_helper.c1125 .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_64BIT | ARM_CP_NO_GDB,
1128 .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_64BIT | ARM_CP_NO_GDB,
H A Dcpregs.h62 ARM_CP_64BIT = 1 << 5,
1118 return (ri->state == ARM_CP_STATE_AA64 || (ri->type & ARM_CP_64BIT) in arm_cpreg_in_idspace()
53 ARM_CP_64BIT = 1 << 5, global() enumerator
H A Dgdbstub.c307 if (ri->type & ARM_CP_64BIT) { in arm_register_sysreg_for_feature()
H A Dcpregs-pmu.c1313 .type = ARM_CP_ALIAS | ARM_CP_IO | ARM_CP_64BIT, in define_pm_cpregs()
/openbmc/qemu/hw/intc/
H A Darm_gicv3_cpuif.c2505 .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_NO_RAW,
2517 .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_NO_RAW,
2529 .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_NO_RAW,
/openbmc/qemu/target/arm/tcg/
H A Dop_helper.c798 if (ri->type & ARM_CP_64BIT) { in HELPER()
H A Dcpu32.c621 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },