Home
last modified time | relevance | path

Searched refs:ARM (Results 1 – 25 of 354) sorted by relevance

12345678910>>...15

/openbmc/openbmc/meta-arm/meta-arm-bsp/recipes-bsp/uefi/files/
H A D0001-Platform-Sgi-workaround-ArmFfaLib-error.patch8 …p/work/sgi575-poky-linux/edk2-firmware/202502/edk2/edk2-platforms/Platform/ARM/SgiPkg/Sgi575/Sgi57…
12 …p/work/sgi575-poky-linux/edk2-firmware/202502/edk2/edk2-platforms/Platform/ARM/SgiPkg/Sgi575/Sgi57…
21 That file is referenced in Platform/ARM/SgiPkg/SgiPlatform.dsc.inc
28 Platform/ARM/SgiPkg/Sgi575/Sgi575.dsc | 3 +++
31 diff --git a/Platform/ARM/SgiPkg/Sgi575/Sgi575.dsc b/Platform/ARM/SgiPkg/Sgi575/Sgi575.dsc
33 --- a/Platform/ARM/SgiPkg/Sgi575/Sgi575.dsc
34 +++ b/Platform/ARM/SgiPkg/Sgi575/Sgi575.dsc
38 Platform/ARM/SgiPkg/AcpiTables/Sgi575AcpiTables.inf
/openbmc/u-boot/board/freescale/common/
H A DKconfig4 imply CMD_HASH if ARM
6 select SPL_BOARD_INIT if (ARM && SPL)
10 select CMD_EXT4 if ARM
11 select CMD_EXT4_WRITE if ARM
/openbmc/qemu/docs/system/arm/
H A Dstm32.rst4 The `STM32`_ chips are a family of 32-bit ARM-based microcontroller by
9 The STM32F1 series is based on ARM Cortex-M3 core. The following machines are
14 The STM32F2 series is based on ARM Cortex-M3 core. The following machines are
19 The STM32F4 series is based on ARM Cortex-M4F core, as well as the STM32L4
21 The following machines are based on this ARM Cortex-M4F chip :
32 * ARM Cortex-M3, Cortex M4F
/openbmc/u-boot/arch/arm/cpu/armv8/fsl-layerscape/doc/
H A DREADME.soc14 The LS1043A integrated multicore processor combines four ARM Cortex-A53
20 - Four 64-bit ARM Cortex-A53 CPUs
53 architecture combining eight ARM A53 processor cores
62 - 8 32-bit / 64-bit ARM v8 Cortex-A53 CPUs
84 The LS2080A integrated multicore processor combines eight ARM Cortex-A57
91 - Eight 64-bit ARM Cortex-A57 CPUs
128 The LS1012A features an advanced 64-bit ARM v8 Cortex-
134 - One 64-bit ARM v8 Cortex-A53 core with the following capabilities:
135 - ARM v8 cryptography extensions
138 - ARM core-link CCI-400 cache coherent interconnect
[all …]
/openbmc/openbmc/meta-arm/meta-arm/recipes-devtools/gator-daemon/
H A Dgator-daemon_7.8.0.bb2 DESCRIPTION = "Target-side daemon gathering data for ARM Streamline \
4 HOMEPAGE = "https://github.com/ARM-software/gator"
9 # https://github.com/ARM-software/gator#kernel-configuration
19 SRC_URI = "git://github.com/ARM-software/gator.git;protocol=http;branch=main;protocol=https \
/openbmc/u-boot/board/armltd/integrator/
H A DREADME2 U-Boot for ARM Integrator Development Platforms
4 Peter Pearse, ARM Ltd.
15 Each CM consists of a ARM processor core and associated hardware e.g
26 a) Run ARM boot monitor, manually run U-Boot image from flash
27 b) Run ARM boot monitor, automatically run U-Boot image from flash
30 In cases a) and b) the ARM boot monitor will have configured the CM and mapped
47 Code specific to initialization of a particular ARM processor has been placed in
51 for ARM Integrator CMs has been added
68 Integrator/AP is no longer available from ARM.
/openbmc/u-boot/arch/arm/cpu/armv7/
H A Dcache_v7_asm.S9 #define ARM(x...) macro
12 #define ARM(x...) x macro
52 ARM( orr r11, r10, r4, lsl r5 ) @ factor way and cache number into r11
55 ARM( orr r11, r11, r9, lsl r2 ) @ factor index number into r11
76 ARM( stmfd sp!, {r4-r5, r7, r9-r11, lr} )
79 ARM( ldmfd sp!, {r4-r5, r7, r9-r11, lr} )
122 ARM( orr r11, r10, r4, lsl r5 ) @ factor way and cache number into r11
125 ARM( orr r11, r11, r9, lsl r2 ) @ factor index number into r11
146 ARM( stmfd sp!, {r4-r5, r7, r9-r11, lr} )
149 ARM( ldmfd sp!, {r4-r5, r7, r9-r11, lr} )
/openbmc/openbmc/meta-arm/meta-arm/lib/oeqa/runtime/cases/
H A Dparselogs-ignores-qemuarm64-secureboot.txt2 ARM FF-A: Failed to register driver sched callback -95
3 ARM FF-A: Notification setup failed -95, not enabled
/openbmc/openbmc/meta-arm/meta-arm-bsp/lib/oeqa/runtime/cases/
H A Dparselogs-ignores-corstone1000-fvp.txt7 ARM FF-A: Notification setup failed -95, not enabled
8 ARM FF-A: Failed to register driver sched callback -95
/openbmc/qemu/target/arm/
H A DKconfig1 config ARM config
13 select ARM
/openbmc/u-boot/doc/
H A DREADME.s5pc1xx5 This README is about U-Boot support for SAMSUNG's ARM Cortex-A8 based S5PC1xx
15 While ARM Cortex-A8 support ARM v7 instruction set (-march=armv7a) we compile
H A DREADME.qemu-arm5 U-Boot on QEMU's 'virt' machine on ARM & AArch64
8 QEMU for ARM supports a special 'virt' machine designed for emulation and
10 Both 32-bit ARM and AArch64 are supported.
29 - For ARM:
41 - For ARM:
H A DREADME.ARM-memory-map1 Subject: Re: [PATCH][CFT] bring ARM memory layout in line with the documented behaviour
14 different parts of the (ARM) code.
/openbmc/u-boot/arch/arm/mach-rmobile/
H A DKconfig8 bool "Renesas ARM SoCs R-Car Gen1/Gen2 (32bit)"
12 bool "Renesas ARM SoCs R-Car Gen3 (64bit)"
/openbmc/qemu/hw/vmapple/
H A DKconfig17 depends on ARM
19 default y if ARM
/openbmc/u-boot/drivers/tee/
H A DKconfig4 depends on (ARM && (ARM64 || CPU_V7A)) || SANDBOX
5 select ARM_SMCCC if ARM
9 environment, for example, TrustZone on ARM cpus, or a separate
/openbmc/u-boot/
H A DMAINTAINERS77 ARM
83 ARM ALTERA SOCFPGA
89 ARM AMLOGIC SOC SUPPORT
111 ARM BROADCOM BCM283X
124 ARM BROADCOM BCMSTB
134 ARM/CZ.NIC TURRIS MOX SUPPORT
142 ARM FREESCALE IMX
158 ARM HISILICON
164 ARM MARVELL KIRKWOOD ARMADA-XP ARMADA-38X ARMADA-37XX ARMADA-7K/8K
178 ARM MARVELL PXA
[all …]
/openbmc/u-boot/drivers/ddr/fsl/
H A DKconfig5 PowerPC- based SoCs (such as mpc83xx, mpc85xx, mpc86xx) and ARM-
97 depends on ARM
99 Enable Freescale DDR3 controller for ARM SoCs.
134 select SYS_FSL_DDRC_ARM_GEN3 if ARM
/openbmc/libcper/specification/document/
H A Dcper-json-specification.tex276 cpuVersionInfo & uint64 & The CPU version information as reported by CPUID with EAX=1. On ARM, this…
278 cpuBrandString & string & The ASCII brand string of the CPU. This field is optional on ARM.\\
280 processorID & uint64 & The unique identifier of the logical processor. On ARM, this is MPIDR\_EL1.\\
708 % ARM processor error section.
709 \section{ARM Processor Error Section}
711 …on describes the JSON format for a single ARM Processor Error Section from a CPER record. The GUID…
713 validationBits & object & An ARM Processor Error Validation structure, as defined in Subsection \re…
730 …mat, or the newer "Extended StateID" format. For more information, see the ARM PSCI specification.…
732 errorInfo & array & Array of ARM Processor Error Info structures, as defined in Subsection \ref{sub…
734 contextInfo & array & Array of ARM Processor Context Info structures, as defined in Subsection \ref…
[all …]
/openbmc/openbmc/meta-openembedded/meta-oe/recipes-benchmark/cpuburn/
H A Dcpuburn-arm_git.bb1 SUMMARY = "A collection of cpuburn programs tuned for different ARM hardware"
22 # If the arch is set to ARM 64-bit - we only produce and ship burn-a53 version.
23 # In case of ARM 32-bit - we would build all variants, since burn-a53 supports both
/openbmc/openbmc/poky/meta/recipes-devtools/clang/clang/
H A D0001-libcxxabi-Find-libunwind-headers-when-LIBCXXABI_LIBU.patch9 especially for ARM targets
27 if (LIBCXXABI_USE_LLVM_UNWINDER OR LLVM_NATIVE_ARCH MATCHES ARM)
33 @@ -476,18 +476,23 @@ if (LIBCXXABI_USE_LLVM_UNWINDER OR LLVM_NATIVE_ARCH MATCHES ARM)
/openbmc/u-boot/arch/arm/cpu/arm926ejs/mxs/
H A Du-boot-spl.lds67 .ARM.exidx : { *(.ARM.exidx*) }
/openbmc/u-boot/board/freescale/ls1021atwr/
H A DREADME14 enterprise networking applications. Incorporating dual ARM Cortex-A7 cores
28 - ARM Cortex-A7 MPCore compliant with ARMv7-A architecture
29 - Dual high-preformance ARM Cortex-A7 cores, each core includes:
35 - ARM Core-Link CCI-400 Cache Coherent Interconnect
66 - QorIQ Trust Architecture, Secure Boot, and ARM TrustZone supported
75 - QorIQ TrustArchitecture with Secure Boot, as well as ARM TrustZone supported
/openbmc/u-boot/board/freescale/ls1021aqds/
H A DREADME14 enterprise networking applications. Incorporating dual ARM Cortex-A7 cores
28 - ARM Cortex-A7 MPCore compliant with ARMv7-A architecture
29 - Dual high-preformance ARM Cortex-A7 cores, each core includes:
35 - ARM Core-Link CCI-400 Cache Coherent Interconnect
66 - QorIQ Trust Architecture, Secure Boot, and ARM TrustZone supported
75 - QorIQ TrustArchitecture with Secure Boot, as well as ARM TrustZone supported
/openbmc/u-boot/arch/arm/include/asm/
H A Dunified.h32 #define ARM(x...) macro
45 #define ARM(x...) x

12345678910>>...15