1 /* SPDX-License-Identifier: GPL-2.0
2  *
3  * Copyright 2016-2020 HabanaLabs, Ltd.
4  * All Rights Reserved.
5  *
6  */
7 
8 /************************************
9  ** This is an auto-generated file **
10  **       DO NOT EDIT BELOW        **
11  ************************************/
12 
13 #ifndef ASIC_REG_ARC_FARM_ARC0_AUX_MASKS_H_
14 #define ASIC_REG_ARC_FARM_ARC0_AUX_MASKS_H_
15 
16 /*
17  *****************************************
18  *   ARC_FARM_ARC0_AUX
19  *   (Prototype: QMAN_ARC_AUX)
20  *****************************************
21  */
22 
23 /* ARC_FARM_ARC0_AUX_RUN_HALT_REQ */
24 #define ARC_FARM_ARC0_AUX_RUN_HALT_REQ_RUN_REQ_SHIFT 0
25 #define ARC_FARM_ARC0_AUX_RUN_HALT_REQ_RUN_REQ_MASK 0x1
26 #define ARC_FARM_ARC0_AUX_RUN_HALT_REQ_HALT_REQ_SHIFT 1
27 #define ARC_FARM_ARC0_AUX_RUN_HALT_REQ_HALT_REQ_MASK 0x2
28 
29 /* ARC_FARM_ARC0_AUX_RUN_HALT_ACK */
30 #define ARC_FARM_ARC0_AUX_RUN_HALT_ACK_RUN_ACK_SHIFT 0
31 #define ARC_FARM_ARC0_AUX_RUN_HALT_ACK_RUN_ACK_MASK 0x1
32 #define ARC_FARM_ARC0_AUX_RUN_HALT_ACK_HALT_ACK_SHIFT 4
33 #define ARC_FARM_ARC0_AUX_RUN_HALT_ACK_HALT_ACK_MASK 0x10
34 #define ARC_FARM_ARC0_AUX_RUN_HALT_ACK_SYS_HALT_R_SHIFT 8
35 #define ARC_FARM_ARC0_AUX_RUN_HALT_ACK_SYS_HALT_R_MASK 0x100
36 #define ARC_FARM_ARC0_AUX_RUN_HALT_ACK_SYS_TF_HALT_R_SHIFT 12
37 #define ARC_FARM_ARC0_AUX_RUN_HALT_ACK_SYS_TF_HALT_R_MASK 0x1000
38 #define ARC_FARM_ARC0_AUX_RUN_HALT_ACK_SYS_SLEEP_R_SHIFT 16
39 #define ARC_FARM_ARC0_AUX_RUN_HALT_ACK_SYS_SLEEP_R_MASK 0x10000
40 #define ARC_FARM_ARC0_AUX_RUN_HALT_ACK_SYS_SLEEP_MODE_R_SHIFT 17
41 #define ARC_FARM_ARC0_AUX_RUN_HALT_ACK_SYS_SLEEP_MODE_R_MASK 0xE0000
42 #define ARC_FARM_ARC0_AUX_RUN_HALT_ACK_WATCHDOG_RESET_SHIFT 20
43 #define ARC_FARM_ARC0_AUX_RUN_HALT_ACK_WATCHDOG_RESET_MASK 0x100000
44 
45 /* ARC_FARM_ARC0_AUX_RST_VEC_ADDR */
46 #define ARC_FARM_ARC0_AUX_RST_VEC_ADDR_VAL_SHIFT 0
47 #define ARC_FARM_ARC0_AUX_RST_VEC_ADDR_VAL_MASK 0x3FFFFF
48 
49 /* ARC_FARM_ARC0_AUX_DBG_MODE */
50 #define ARC_FARM_ARC0_AUX_DBG_MODE_DBG_PROT_SEL_SHIFT 0
51 #define ARC_FARM_ARC0_AUX_DBG_MODE_DBG_PROT_SEL_MASK 0x1
52 #define ARC_FARM_ARC0_AUX_DBG_MODE_DBGEN_SHIFT 4
53 #define ARC_FARM_ARC0_AUX_DBG_MODE_DBGEN_MASK 0x10
54 #define ARC_FARM_ARC0_AUX_DBG_MODE_NIDEN_SHIFT 8
55 #define ARC_FARM_ARC0_AUX_DBG_MODE_NIDEN_MASK 0x100
56 #define ARC_FARM_ARC0_AUX_DBG_MODE_CASHE_RST_DISABLE_SHIFT 12
57 #define ARC_FARM_ARC0_AUX_DBG_MODE_CASHE_RST_DISABLE_MASK 0x1000
58 #define ARC_FARM_ARC0_AUX_DBG_MODE_DDCM_DMI_PRIORITY_SHIFT 16
59 #define ARC_FARM_ARC0_AUX_DBG_MODE_DDCM_DMI_PRIORITY_MASK 0x10000
60 
61 /* ARC_FARM_ARC0_AUX_CLUSTER_NUM */
62 #define ARC_FARM_ARC0_AUX_CLUSTER_NUM_VAL_SHIFT 0
63 #define ARC_FARM_ARC0_AUX_CLUSTER_NUM_VAL_MASK 0xFF
64 
65 /* ARC_FARM_ARC0_AUX_ARC_NUM */
66 #define ARC_FARM_ARC0_AUX_ARC_NUM_VAL_SHIFT 0
67 #define ARC_FARM_ARC0_AUX_ARC_NUM_VAL_MASK 0xFF
68 
69 /* ARC_FARM_ARC0_AUX_WAKE_UP_EVENT */
70 #define ARC_FARM_ARC0_AUX_WAKE_UP_EVENT_VAL_SHIFT 0
71 #define ARC_FARM_ARC0_AUX_WAKE_UP_EVENT_VAL_MASK 0x1
72 
73 /* ARC_FARM_ARC0_AUX_DCCM_SYS_ADDR_BASE */
74 #define ARC_FARM_ARC0_AUX_DCCM_SYS_ADDR_BASE_VAL_SHIFT 0
75 #define ARC_FARM_ARC0_AUX_DCCM_SYS_ADDR_BASE_VAL_MASK 0xFFFFFFFF
76 
77 /* ARC_FARM_ARC0_AUX_CTI_AP_STS */
78 #define ARC_FARM_ARC0_AUX_CTI_AP_STS_VAL_SHIFT 0
79 #define ARC_FARM_ARC0_AUX_CTI_AP_STS_VAL_MASK 0xFF
80 
81 /* ARC_FARM_ARC0_AUX_CTI_CFG_MUX_SEL */
82 #define ARC_FARM_ARC0_AUX_CTI_CFG_MUX_SEL_RUN_HALT_SHIFT 0
83 #define ARC_FARM_ARC0_AUX_CTI_CFG_MUX_SEL_RUN_HALT_MASK 0x1
84 
85 /* ARC_FARM_ARC0_AUX_ARC_RST */
86 #define ARC_FARM_ARC0_AUX_ARC_RST_CORE_SHIFT 0
87 #define ARC_FARM_ARC0_AUX_ARC_RST_CORE_MASK 0x1
88 #define ARC_FARM_ARC0_AUX_ARC_RST_PRESETDBGN_SHIFT 4
89 #define ARC_FARM_ARC0_AUX_ARC_RST_PRESETDBGN_MASK 0x10
90 
91 /* ARC_FARM_ARC0_AUX_ARC_RST_REQ */
92 #define ARC_FARM_ARC0_AUX_ARC_RST_REQ_VAL_SHIFT 0
93 #define ARC_FARM_ARC0_AUX_ARC_RST_REQ_VAL_MASK 0x1
94 
95 /* ARC_FARM_ARC0_AUX_SRAM_LSB_ADDR */
96 #define ARC_FARM_ARC0_AUX_SRAM_LSB_ADDR_VAL_SHIFT 0
97 #define ARC_FARM_ARC0_AUX_SRAM_LSB_ADDR_VAL_MASK 0x3F
98 
99 /* ARC_FARM_ARC0_AUX_SRAM_MSB_ADDR */
100 #define ARC_FARM_ARC0_AUX_SRAM_MSB_ADDR_VAL_SHIFT 0
101 #define ARC_FARM_ARC0_AUX_SRAM_MSB_ADDR_VAL_MASK 0xFFFFFFFF
102 
103 /* ARC_FARM_ARC0_AUX_PCIE_LSB_ADDR */
104 #define ARC_FARM_ARC0_AUX_PCIE_LSB_ADDR_VAL_SHIFT 0
105 #define ARC_FARM_ARC0_AUX_PCIE_LSB_ADDR_VAL_MASK 0xF
106 
107 /* ARC_FARM_ARC0_AUX_PCIE_MSB_ADDR */
108 #define ARC_FARM_ARC0_AUX_PCIE_MSB_ADDR_VAL_SHIFT 0
109 #define ARC_FARM_ARC0_AUX_PCIE_MSB_ADDR_VAL_MASK 0xFFFFFFFF
110 
111 /* ARC_FARM_ARC0_AUX_CFG_LSB_ADDR */
112 #define ARC_FARM_ARC0_AUX_CFG_LSB_ADDR_VAL_SHIFT 0
113 #define ARC_FARM_ARC0_AUX_CFG_LSB_ADDR_VAL_MASK 0xF
114 
115 /* ARC_FARM_ARC0_AUX_CFG_MSB_ADDR */
116 #define ARC_FARM_ARC0_AUX_CFG_MSB_ADDR_VAL_SHIFT 0
117 #define ARC_FARM_ARC0_AUX_CFG_MSB_ADDR_VAL_MASK 0xFFFFFFFF
118 
119 /* ARC_FARM_ARC0_AUX_HBM0_LSB_ADDR */
120 #define ARC_FARM_ARC0_AUX_HBM0_LSB_ADDR_VAL_SHIFT 0
121 #define ARC_FARM_ARC0_AUX_HBM0_LSB_ADDR_VAL_MASK 0xF
122 
123 /* ARC_FARM_ARC0_AUX_HBM0_MSB_ADDR */
124 #define ARC_FARM_ARC0_AUX_HBM0_MSB_ADDR_VAL_SHIFT 0
125 #define ARC_FARM_ARC0_AUX_HBM0_MSB_ADDR_VAL_MASK 0xFFFFFFFF
126 
127 /* ARC_FARM_ARC0_AUX_HBM1_LSB_ADDR */
128 #define ARC_FARM_ARC0_AUX_HBM1_LSB_ADDR_VAL_SHIFT 0
129 #define ARC_FARM_ARC0_AUX_HBM1_LSB_ADDR_VAL_MASK 0xF
130 
131 /* ARC_FARM_ARC0_AUX_HBM1_MSB_ADDR */
132 #define ARC_FARM_ARC0_AUX_HBM1_MSB_ADDR_VAL_SHIFT 0
133 #define ARC_FARM_ARC0_AUX_HBM1_MSB_ADDR_VAL_MASK 0xFFFFFFFF
134 
135 /* ARC_FARM_ARC0_AUX_HBM2_LSB_ADDR */
136 #define ARC_FARM_ARC0_AUX_HBM2_LSB_ADDR_VAL_SHIFT 0
137 #define ARC_FARM_ARC0_AUX_HBM2_LSB_ADDR_VAL_MASK 0xF
138 
139 /* ARC_FARM_ARC0_AUX_HBM2_MSB_ADDR */
140 #define ARC_FARM_ARC0_AUX_HBM2_MSB_ADDR_VAL_SHIFT 0
141 #define ARC_FARM_ARC0_AUX_HBM2_MSB_ADDR_VAL_MASK 0xFFFFFFFF
142 
143 /* ARC_FARM_ARC0_AUX_HBM3_LSB_ADDR */
144 #define ARC_FARM_ARC0_AUX_HBM3_LSB_ADDR_VAL_SHIFT 0
145 #define ARC_FARM_ARC0_AUX_HBM3_LSB_ADDR_VAL_MASK 0xF
146 
147 /* ARC_FARM_ARC0_AUX_HBM3_MSB_ADDR */
148 #define ARC_FARM_ARC0_AUX_HBM3_MSB_ADDR_VAL_SHIFT 0
149 #define ARC_FARM_ARC0_AUX_HBM3_MSB_ADDR_VAL_MASK 0xFFFFFFFF
150 
151 /* ARC_FARM_ARC0_AUX_HBM0_OFFSET */
152 #define ARC_FARM_ARC0_AUX_HBM0_OFFSET_VAL_SHIFT 0
153 #define ARC_FARM_ARC0_AUX_HBM0_OFFSET_VAL_MASK 0xFFFFFFF
154 
155 /* ARC_FARM_ARC0_AUX_HBM1_OFFSET */
156 #define ARC_FARM_ARC0_AUX_HBM1_OFFSET_VAL_SHIFT 0
157 #define ARC_FARM_ARC0_AUX_HBM1_OFFSET_VAL_MASK 0xFFFFFFF
158 
159 /* ARC_FARM_ARC0_AUX_HBM2_OFFSET */
160 #define ARC_FARM_ARC0_AUX_HBM2_OFFSET_VAL_SHIFT 0
161 #define ARC_FARM_ARC0_AUX_HBM2_OFFSET_VAL_MASK 0xFFFFFFF
162 
163 /* ARC_FARM_ARC0_AUX_HBM3_OFFSET */
164 #define ARC_FARM_ARC0_AUX_HBM3_OFFSET_VAL_SHIFT 0
165 #define ARC_FARM_ARC0_AUX_HBM3_OFFSET_VAL_MASK 0xFFFFFFF
166 
167 /* ARC_FARM_ARC0_AUX_GENERAL_PURPOSE_LSB_ADDR */
168 #define ARC_FARM_ARC0_AUX_GENERAL_PURPOSE_LSB_ADDR_VAL_SHIFT 0
169 #define ARC_FARM_ARC0_AUX_GENERAL_PURPOSE_LSB_ADDR_VAL_MASK 0xF
170 
171 /* ARC_FARM_ARC0_AUX_GENERAL_PURPOSE_MSB_ADDR */
172 #define ARC_FARM_ARC0_AUX_GENERAL_PURPOSE_MSB_ADDR_VAL_SHIFT 0
173 #define ARC_FARM_ARC0_AUX_GENERAL_PURPOSE_MSB_ADDR_VAL_MASK 0xFFFFFFFF
174 
175 /* ARC_FARM_ARC0_AUX_ARC_CBU_AWCACHE_OVR */
176 #define ARC_FARM_ARC0_AUX_ARC_CBU_AWCACHE_OVR_AXI_WRITE_SHIFT 0
177 #define ARC_FARM_ARC0_AUX_ARC_CBU_AWCACHE_OVR_AXI_WRITE_MASK 0xF
178 #define ARC_FARM_ARC0_AUX_ARC_CBU_AWCACHE_OVR_AXI_WRITE_EN_SHIFT 4
179 #define ARC_FARM_ARC0_AUX_ARC_CBU_AWCACHE_OVR_AXI_WRITE_EN_MASK 0xF0
180 
181 /* ARC_FARM_ARC0_AUX_ARC_LBU_AWCACHE_OVR */
182 #define ARC_FARM_ARC0_AUX_ARC_LBU_AWCACHE_OVR_AXI_WRITE_SHIFT 0
183 #define ARC_FARM_ARC0_AUX_ARC_LBU_AWCACHE_OVR_AXI_WRITE_MASK 0xF
184 #define ARC_FARM_ARC0_AUX_ARC_LBU_AWCACHE_OVR_AXI_WRITE_EN_SHIFT 4
185 #define ARC_FARM_ARC0_AUX_ARC_LBU_AWCACHE_OVR_AXI_WRITE_EN_MASK 0xF0
186 
187 /* ARC_FARM_ARC0_AUX_CONTEXT_ID */
188 #define ARC_FARM_ARC0_AUX_CONTEXT_ID_VAL_SHIFT 0
189 #define ARC_FARM_ARC0_AUX_CONTEXT_ID_VAL_MASK 0xFFFFFFFF
190 
191 /* ARC_FARM_ARC0_AUX_CID_OFFSET */
192 #define ARC_FARM_ARC0_AUX_CID_OFFSET_VAL_SHIFT 0
193 #define ARC_FARM_ARC0_AUX_CID_OFFSET_VAL_MASK 0xFF
194 
195 /* ARC_FARM_ARC0_AUX_SW_INTR */
196 #define ARC_FARM_ARC0_AUX_SW_INTR_VAL_SHIFT 0
197 #define ARC_FARM_ARC0_AUX_SW_INTR_VAL_MASK 0xFFFFFFFF
198 
199 /* ARC_FARM_ARC0_AUX_IRQ_INTR_MASK */
200 #define ARC_FARM_ARC0_AUX_IRQ_INTR_MASK_VAL_SHIFT 0
201 #define ARC_FARM_ARC0_AUX_IRQ_INTR_MASK_VAL_MASK 0xFFFFFFFF
202 
203 /* ARC_FARM_ARC0_AUX_ARC_SEI_INTR_STS */
204 #define ARC_FARM_ARC0_AUX_ARC_SEI_INTR_STS_VAL_SHIFT 0
205 #define ARC_FARM_ARC0_AUX_ARC_SEI_INTR_STS_VAL_MASK 0x3FFF
206 
207 /* ARC_FARM_ARC0_AUX_ARC_SEI_INTR_CLR */
208 #define ARC_FARM_ARC0_AUX_ARC_SEI_INTR_CLR_VAL_SHIFT 0
209 #define ARC_FARM_ARC0_AUX_ARC_SEI_INTR_CLR_VAL_MASK 0x3FFF
210 
211 /* ARC_FARM_ARC0_AUX_ARC_SEI_INTR_MASK */
212 #define ARC_FARM_ARC0_AUX_ARC_SEI_INTR_MASK_VAL_SHIFT 0
213 #define ARC_FARM_ARC0_AUX_ARC_SEI_INTR_MASK_VAL_MASK 0x3FFF
214 
215 /* ARC_FARM_ARC0_AUX_ARC_EXCPTN_CAUSE */
216 #define ARC_FARM_ARC0_AUX_ARC_EXCPTN_CAUSE_VAL_SHIFT 0
217 #define ARC_FARM_ARC0_AUX_ARC_EXCPTN_CAUSE_VAL_MASK 0xFFFFFFFF
218 
219 /* ARC_FARM_ARC0_AUX_SEI_INTR_HALT_EN */
220 #define ARC_FARM_ARC0_AUX_SEI_INTR_HALT_EN_INTR_EN_SHIFT 0
221 #define ARC_FARM_ARC0_AUX_SEI_INTR_HALT_EN_INTR_EN_MASK 0x1
222 #define ARC_FARM_ARC0_AUX_SEI_INTR_HALT_EN_HALT_EN_SHIFT 1
223 #define ARC_FARM_ARC0_AUX_SEI_INTR_HALT_EN_HALT_EN_MASK 0x2
224 
225 /* ARC_FARM_ARC0_AUX_ARC_SEI_INTR_HALT_MASK */
226 #define ARC_FARM_ARC0_AUX_ARC_SEI_INTR_HALT_MASK_VAL_SHIFT 0
227 #define ARC_FARM_ARC0_AUX_ARC_SEI_INTR_HALT_MASK_VAL_MASK 0x3FFF
228 
229 /* ARC_FARM_ARC0_AUX_QMAN_SEI_INTR_HALT_MASK */
230 #define ARC_FARM_ARC0_AUX_QMAN_SEI_INTR_HALT_MASK_VAL_SHIFT 0
231 #define ARC_FARM_ARC0_AUX_QMAN_SEI_INTR_HALT_MASK_VAL_MASK 0x3FFF
232 
233 /* ARC_FARM_ARC0_AUX_ARC_REI_INTR_STS */
234 #define ARC_FARM_ARC0_AUX_ARC_REI_INTR_STS_SERR_SHIFT 0
235 #define ARC_FARM_ARC0_AUX_ARC_REI_INTR_STS_SERR_MASK 0x1
236 #define ARC_FARM_ARC0_AUX_ARC_REI_INTR_STS_DERR_SHIFT 1
237 #define ARC_FARM_ARC0_AUX_ARC_REI_INTR_STS_DERR_MASK 0x2
238 
239 /* ARC_FARM_ARC0_AUX_ARC_REI_INTR_CLR */
240 #define ARC_FARM_ARC0_AUX_ARC_REI_INTR_CLR_VAL_SHIFT 0
241 #define ARC_FARM_ARC0_AUX_ARC_REI_INTR_CLR_VAL_MASK 0x3
242 
243 /* ARC_FARM_ARC0_AUX_ARC_REI_INTR_MASK */
244 #define ARC_FARM_ARC0_AUX_ARC_REI_INTR_MASK_VAL_SHIFT 0
245 #define ARC_FARM_ARC0_AUX_ARC_REI_INTR_MASK_VAL_MASK 0x3
246 
247 /* ARC_FARM_ARC0_AUX_DCCM_ECC_ERR_ADDR */
248 #define ARC_FARM_ARC0_AUX_DCCM_ECC_ERR_ADDR_VAL_SHIFT 0
249 #define ARC_FARM_ARC0_AUX_DCCM_ECC_ERR_ADDR_VAL_MASK 0xFFFFFFFF
250 
251 /* ARC_FARM_ARC0_AUX_DCCM_ECC_SYNDROME */
252 #define ARC_FARM_ARC0_AUX_DCCM_ECC_SYNDROME_VAL_SHIFT 0
253 #define ARC_FARM_ARC0_AUX_DCCM_ECC_SYNDROME_VAL_MASK 0xFFFFFFFF
254 
255 /* ARC_FARM_ARC0_AUX_I_CACHE_ECC_ERR_ADDR */
256 #define ARC_FARM_ARC0_AUX_I_CACHE_ECC_ERR_ADDR_VAL_SHIFT 0
257 #define ARC_FARM_ARC0_AUX_I_CACHE_ECC_ERR_ADDR_VAL_MASK 0xFFFFFFFF
258 
259 /* ARC_FARM_ARC0_AUX_I_CACHE_ECC_SYNDROME */
260 #define ARC_FARM_ARC0_AUX_I_CACHE_ECC_SYNDROME_VAL_SHIFT 0
261 #define ARC_FARM_ARC0_AUX_I_CACHE_ECC_SYNDROME_VAL_MASK 0xFFFFFFFF
262 
263 /* ARC_FARM_ARC0_AUX_D_CACHE_ECC_ERR_ADDR */
264 #define ARC_FARM_ARC0_AUX_D_CACHE_ECC_ERR_ADDR_VAL_SHIFT 0
265 #define ARC_FARM_ARC0_AUX_D_CACHE_ECC_ERR_ADDR_VAL_MASK 0xFFFFFFFF
266 
267 /* ARC_FARM_ARC0_AUX_D_CACHE_ECC_SYNDROME */
268 #define ARC_FARM_ARC0_AUX_D_CACHE_ECC_SYNDROME_VAL_SHIFT 0
269 #define ARC_FARM_ARC0_AUX_D_CACHE_ECC_SYNDROME_VAL_MASK 0xFFFFFFFF
270 
271 /* ARC_FARM_ARC0_AUX_LBW_TRMINATE_AWADDR_ERR */
272 #define ARC_FARM_ARC0_AUX_LBW_TRMINATE_AWADDR_ERR_VAL_SHIFT 0
273 #define ARC_FARM_ARC0_AUX_LBW_TRMINATE_AWADDR_ERR_VAL_MASK 0xFFFFFFFF
274 
275 /* ARC_FARM_ARC0_AUX_LBW_TRMINATE_ARADDR_ERR */
276 #define ARC_FARM_ARC0_AUX_LBW_TRMINATE_ARADDR_ERR_VAL_SHIFT 0
277 #define ARC_FARM_ARC0_AUX_LBW_TRMINATE_ARADDR_ERR_VAL_MASK 0xFFFFFFFF
278 
279 /* ARC_FARM_ARC0_AUX_CFG_LBW_TERMINATE_BRESP */
280 #define ARC_FARM_ARC0_AUX_CFG_LBW_TERMINATE_BRESP_VAL_SHIFT 0
281 #define ARC_FARM_ARC0_AUX_CFG_LBW_TERMINATE_BRESP_VAL_MASK 0x3
282 
283 /* ARC_FARM_ARC0_AUX_CFG_LBW_TERMINATE_RRESP */
284 #define ARC_FARM_ARC0_AUX_CFG_LBW_TERMINATE_RRESP_VAL_SHIFT 0
285 #define ARC_FARM_ARC0_AUX_CFG_LBW_TERMINATE_RRESP_VAL_MASK 0x3
286 
287 /* ARC_FARM_ARC0_AUX_CFG_LBW_TERMINATE_AXLEN */
288 #define ARC_FARM_ARC0_AUX_CFG_LBW_TERMINATE_AXLEN_VAL_SHIFT 0
289 #define ARC_FARM_ARC0_AUX_CFG_LBW_TERMINATE_AXLEN_VAL_MASK 0xFF
290 
291 /* ARC_FARM_ARC0_AUX_CFG_LBW_TERMINATE_AXSIZE */
292 #define ARC_FARM_ARC0_AUX_CFG_LBW_TERMINATE_AXSIZE_VAL_SHIFT 0
293 #define ARC_FARM_ARC0_AUX_CFG_LBW_TERMINATE_AXSIZE_VAL_MASK 0x7
294 
295 /* ARC_FARM_ARC0_AUX_SCRATCHPAD */
296 #define ARC_FARM_ARC0_AUX_SCRATCHPAD_VAL_SHIFT 0
297 #define ARC_FARM_ARC0_AUX_SCRATCHPAD_VAL_MASK 0xFFFFFFFF
298 
299 /* ARC_FARM_ARC0_AUX_TOTAL_CBU_WR_CNT */
300 #define ARC_FARM_ARC0_AUX_TOTAL_CBU_WR_CNT_VAL_SHIFT 0
301 #define ARC_FARM_ARC0_AUX_TOTAL_CBU_WR_CNT_VAL_MASK 0xFFFFFFFF
302 
303 /* ARC_FARM_ARC0_AUX_INFLIGHT_CBU_WR_CNT */
304 #define ARC_FARM_ARC0_AUX_INFLIGHT_CBU_WR_CNT_VAL_SHIFT 0
305 #define ARC_FARM_ARC0_AUX_INFLIGHT_CBU_WR_CNT_VAL_MASK 0xFFFFFFFF
306 
307 /* ARC_FARM_ARC0_AUX_TOTAL_CBU_RD_CNT */
308 #define ARC_FARM_ARC0_AUX_TOTAL_CBU_RD_CNT_VAL_SHIFT 0
309 #define ARC_FARM_ARC0_AUX_TOTAL_CBU_RD_CNT_VAL_MASK 0xFFFFFFFF
310 
311 /* ARC_FARM_ARC0_AUX_INFLIGHT_CBU_RD_CNT */
312 #define ARC_FARM_ARC0_AUX_INFLIGHT_CBU_RD_CNT_VAL_SHIFT 0
313 #define ARC_FARM_ARC0_AUX_INFLIGHT_CBU_RD_CNT_VAL_MASK 0xFFFFFFFF
314 
315 /* ARC_FARM_ARC0_AUX_TOTAL_LBU_WR_CNT */
316 #define ARC_FARM_ARC0_AUX_TOTAL_LBU_WR_CNT_VAL_SHIFT 0
317 #define ARC_FARM_ARC0_AUX_TOTAL_LBU_WR_CNT_VAL_MASK 0xFFFFFFFF
318 
319 /* ARC_FARM_ARC0_AUX_INFLIGHT_LBU_WR_CNT */
320 #define ARC_FARM_ARC0_AUX_INFLIGHT_LBU_WR_CNT_VAL_SHIFT 0
321 #define ARC_FARM_ARC0_AUX_INFLIGHT_LBU_WR_CNT_VAL_MASK 0xFFFFFFFF
322 
323 /* ARC_FARM_ARC0_AUX_TOTAL_LBU_RD_CNT */
324 #define ARC_FARM_ARC0_AUX_TOTAL_LBU_RD_CNT_VAL_SHIFT 0
325 #define ARC_FARM_ARC0_AUX_TOTAL_LBU_RD_CNT_VAL_MASK 0xFFFFFFFF
326 
327 /* ARC_FARM_ARC0_AUX_INFLIGHT_LBU_RD_CNT */
328 #define ARC_FARM_ARC0_AUX_INFLIGHT_LBU_RD_CNT_VAL_SHIFT 0
329 #define ARC_FARM_ARC0_AUX_INFLIGHT_LBU_RD_CNT_VAL_MASK 0xFFFFFFFF
330 
331 /* ARC_FARM_ARC0_AUX_CBU_ARUSER_OVR */
332 #define ARC_FARM_ARC0_AUX_CBU_ARUSER_OVR_VAL_SHIFT 0
333 #define ARC_FARM_ARC0_AUX_CBU_ARUSER_OVR_VAL_MASK 0xFFFFFFFF
334 
335 /* ARC_FARM_ARC0_AUX_CBU_ARUSER_OVR_EN */
336 #define ARC_FARM_ARC0_AUX_CBU_ARUSER_OVR_EN_VAL_SHIFT 0
337 #define ARC_FARM_ARC0_AUX_CBU_ARUSER_OVR_EN_VAL_MASK 0xFFFFFFFF
338 
339 /* ARC_FARM_ARC0_AUX_CBU_AWUSER_OVR */
340 #define ARC_FARM_ARC0_AUX_CBU_AWUSER_OVR_VAL_SHIFT 0
341 #define ARC_FARM_ARC0_AUX_CBU_AWUSER_OVR_VAL_MASK 0xFFFFFFFF
342 
343 /* ARC_FARM_ARC0_AUX_CBU_AWUSER_OVR_EN */
344 #define ARC_FARM_ARC0_AUX_CBU_AWUSER_OVR_EN_VAL_SHIFT 0
345 #define ARC_FARM_ARC0_AUX_CBU_AWUSER_OVR_EN_VAL_MASK 0xFFFFFFFF
346 
347 /* ARC_FARM_ARC0_AUX_CBU_ARUSER_MSB_OVR */
348 #define ARC_FARM_ARC0_AUX_CBU_ARUSER_MSB_OVR_VAL_SHIFT 0
349 #define ARC_FARM_ARC0_AUX_CBU_ARUSER_MSB_OVR_VAL_MASK 0x3FF
350 
351 /* ARC_FARM_ARC0_AUX_CBU_ARUSER_MSB_OVR_EN */
352 #define ARC_FARM_ARC0_AUX_CBU_ARUSER_MSB_OVR_EN_VAL_SHIFT 0
353 #define ARC_FARM_ARC0_AUX_CBU_ARUSER_MSB_OVR_EN_VAL_MASK 0x3FF
354 
355 /* ARC_FARM_ARC0_AUX_CBU_AWUSER_MSB_OVR */
356 #define ARC_FARM_ARC0_AUX_CBU_AWUSER_MSB_OVR_VAL_SHIFT 0
357 #define ARC_FARM_ARC0_AUX_CBU_AWUSER_MSB_OVR_VAL_MASK 0x3FF
358 
359 /* ARC_FARM_ARC0_AUX_CBU_AWUSER_MSB_OVR_EN */
360 #define ARC_FARM_ARC0_AUX_CBU_AWUSER_MSB_OVR_EN_VAL_SHIFT 0
361 #define ARC_FARM_ARC0_AUX_CBU_AWUSER_MSB_OVR_EN_VAL_MASK 0x3FF
362 
363 /* ARC_FARM_ARC0_AUX_CBU_AXCACHE_OVR */
364 #define ARC_FARM_ARC0_AUX_CBU_AXCACHE_OVR_CBU_READ_SHIFT 0
365 #define ARC_FARM_ARC0_AUX_CBU_AXCACHE_OVR_CBU_READ_MASK 0xF
366 #define ARC_FARM_ARC0_AUX_CBU_AXCACHE_OVR_CBU_WRITE_SHIFT 4
367 #define ARC_FARM_ARC0_AUX_CBU_AXCACHE_OVR_CBU_WRITE_MASK 0xF0
368 #define ARC_FARM_ARC0_AUX_CBU_AXCACHE_OVR_CBU_RD_EN_SHIFT 8
369 #define ARC_FARM_ARC0_AUX_CBU_AXCACHE_OVR_CBU_RD_EN_MASK 0xF00
370 #define ARC_FARM_ARC0_AUX_CBU_AXCACHE_OVR_CBU_WR_EN_SHIFT 12
371 #define ARC_FARM_ARC0_AUX_CBU_AXCACHE_OVR_CBU_WR_EN_MASK 0xF000
372 
373 /* ARC_FARM_ARC0_AUX_CBU_LOCK_OVR */
374 #define ARC_FARM_ARC0_AUX_CBU_LOCK_OVR_CBU_READ_SHIFT 0
375 #define ARC_FARM_ARC0_AUX_CBU_LOCK_OVR_CBU_READ_MASK 0x3
376 #define ARC_FARM_ARC0_AUX_CBU_LOCK_OVR_CBU_WRITE_SHIFT 4
377 #define ARC_FARM_ARC0_AUX_CBU_LOCK_OVR_CBU_WRITE_MASK 0x30
378 #define ARC_FARM_ARC0_AUX_CBU_LOCK_OVR_CBU_RD_EN_SHIFT 8
379 #define ARC_FARM_ARC0_AUX_CBU_LOCK_OVR_CBU_RD_EN_MASK 0x300
380 #define ARC_FARM_ARC0_AUX_CBU_LOCK_OVR_CBU_WR_EN_SHIFT 12
381 #define ARC_FARM_ARC0_AUX_CBU_LOCK_OVR_CBU_WR_EN_MASK 0x3000
382 
383 /* ARC_FARM_ARC0_AUX_CBU_PROT_OVR */
384 #define ARC_FARM_ARC0_AUX_CBU_PROT_OVR_CBU_READ_SHIFT 0
385 #define ARC_FARM_ARC0_AUX_CBU_PROT_OVR_CBU_READ_MASK 0x7
386 #define ARC_FARM_ARC0_AUX_CBU_PROT_OVR_CBU_WRITE_SHIFT 4
387 #define ARC_FARM_ARC0_AUX_CBU_PROT_OVR_CBU_WRITE_MASK 0x70
388 #define ARC_FARM_ARC0_AUX_CBU_PROT_OVR_CBU_RD_EN_SHIFT 8
389 #define ARC_FARM_ARC0_AUX_CBU_PROT_OVR_CBU_RD_EN_MASK 0x700
390 #define ARC_FARM_ARC0_AUX_CBU_PROT_OVR_CBU_WR_EN_SHIFT 12
391 #define ARC_FARM_ARC0_AUX_CBU_PROT_OVR_CBU_WR_EN_MASK 0x7000
392 
393 /* ARC_FARM_ARC0_AUX_CBU_MAX_OUTSTANDING */
394 #define ARC_FARM_ARC0_AUX_CBU_MAX_OUTSTANDING_CBU_READ_SHIFT 0
395 #define ARC_FARM_ARC0_AUX_CBU_MAX_OUTSTANDING_CBU_READ_MASK 0xFF
396 #define ARC_FARM_ARC0_AUX_CBU_MAX_OUTSTANDING_CBU_WRITE_SHIFT 8
397 #define ARC_FARM_ARC0_AUX_CBU_MAX_OUTSTANDING_CBU_WRITE_MASK 0xFF00
398 
399 /* ARC_FARM_ARC0_AUX_CBU_EARLY_BRESP_EN */
400 #define ARC_FARM_ARC0_AUX_CBU_EARLY_BRESP_EN_CBU_VAL_SHIFT 0
401 #define ARC_FARM_ARC0_AUX_CBU_EARLY_BRESP_EN_CBU_VAL_MASK 0x1
402 
403 /* ARC_FARM_ARC0_AUX_CBU_FORCE_RSP_OK */
404 #define ARC_FARM_ARC0_AUX_CBU_FORCE_RSP_OK_CBU_VAL_SHIFT 0
405 #define ARC_FARM_ARC0_AUX_CBU_FORCE_RSP_OK_CBU_VAL_MASK 0x1
406 
407 /* ARC_FARM_ARC0_AUX_CBU_NO_WR_INFLIGHT */
408 #define ARC_FARM_ARC0_AUX_CBU_NO_WR_INFLIGHT_VAL_SHIFT 0
409 #define ARC_FARM_ARC0_AUX_CBU_NO_WR_INFLIGHT_VAL_MASK 0x1
410 
411 /* ARC_FARM_ARC0_AUX_CBU_SEI_INTR_ID */
412 #define ARC_FARM_ARC0_AUX_CBU_SEI_INTR_ID_VAL_SHIFT 0
413 #define ARC_FARM_ARC0_AUX_CBU_SEI_INTR_ID_VAL_MASK 0x7F
414 
415 /* ARC_FARM_ARC0_AUX_LBU_ARUSER_OVR */
416 #define ARC_FARM_ARC0_AUX_LBU_ARUSER_OVR_VAL_SHIFT 0
417 #define ARC_FARM_ARC0_AUX_LBU_ARUSER_OVR_VAL_MASK 0xFFFFFFFF
418 
419 /* ARC_FARM_ARC0_AUX_LBU_ARUSER_OVR_EN */
420 #define ARC_FARM_ARC0_AUX_LBU_ARUSER_OVR_EN_VAL_SHIFT 0
421 #define ARC_FARM_ARC0_AUX_LBU_ARUSER_OVR_EN_VAL_MASK 0xFFFFFFFF
422 
423 /* ARC_FARM_ARC0_AUX_LBU_AWUSER_OVR */
424 #define ARC_FARM_ARC0_AUX_LBU_AWUSER_OVR_VAL_SHIFT 0
425 #define ARC_FARM_ARC0_AUX_LBU_AWUSER_OVR_VAL_MASK 0xFFFFFFFF
426 
427 /* ARC_FARM_ARC0_AUX_LBU_AWUSER_OVR_EN */
428 #define ARC_FARM_ARC0_AUX_LBU_AWUSER_OVR_EN_VAL_SHIFT 0
429 #define ARC_FARM_ARC0_AUX_LBU_AWUSER_OVR_EN_VAL_MASK 0xFFFFFFFF
430 
431 /* ARC_FARM_ARC0_AUX_LBU_AXCACHE_OVR */
432 #define ARC_FARM_ARC0_AUX_LBU_AXCACHE_OVR_LBU_READ_SHIFT 0
433 #define ARC_FARM_ARC0_AUX_LBU_AXCACHE_OVR_LBU_READ_MASK 0xF
434 #define ARC_FARM_ARC0_AUX_LBU_AXCACHE_OVR_LBU_WRITE_SHIFT 4
435 #define ARC_FARM_ARC0_AUX_LBU_AXCACHE_OVR_LBU_WRITE_MASK 0xF0
436 #define ARC_FARM_ARC0_AUX_LBU_AXCACHE_OVR_LBU_RD_EN_SHIFT 8
437 #define ARC_FARM_ARC0_AUX_LBU_AXCACHE_OVR_LBU_RD_EN_MASK 0xF00
438 #define ARC_FARM_ARC0_AUX_LBU_AXCACHE_OVR_LBU_WR_EN_SHIFT 12
439 #define ARC_FARM_ARC0_AUX_LBU_AXCACHE_OVR_LBU_WR_EN_MASK 0xF000
440 
441 /* ARC_FARM_ARC0_AUX_LBU_LOCK_OVR */
442 #define ARC_FARM_ARC0_AUX_LBU_LOCK_OVR_LBU_READ_SHIFT 0
443 #define ARC_FARM_ARC0_AUX_LBU_LOCK_OVR_LBU_READ_MASK 0x3
444 #define ARC_FARM_ARC0_AUX_LBU_LOCK_OVR_LBU_WRITE_SHIFT 4
445 #define ARC_FARM_ARC0_AUX_LBU_LOCK_OVR_LBU_WRITE_MASK 0x30
446 #define ARC_FARM_ARC0_AUX_LBU_LOCK_OVR_LBU_RD_EN_SHIFT 8
447 #define ARC_FARM_ARC0_AUX_LBU_LOCK_OVR_LBU_RD_EN_MASK 0x300
448 #define ARC_FARM_ARC0_AUX_LBU_LOCK_OVR_LBU_WR_EN_SHIFT 12
449 #define ARC_FARM_ARC0_AUX_LBU_LOCK_OVR_LBU_WR_EN_MASK 0x3000
450 
451 /* ARC_FARM_ARC0_AUX_LBU_PROT_OVR */
452 #define ARC_FARM_ARC0_AUX_LBU_PROT_OVR_LBU_READ_SHIFT 0
453 #define ARC_FARM_ARC0_AUX_LBU_PROT_OVR_LBU_READ_MASK 0x7
454 #define ARC_FARM_ARC0_AUX_LBU_PROT_OVR_LBU_WRITE_SHIFT 4
455 #define ARC_FARM_ARC0_AUX_LBU_PROT_OVR_LBU_WRITE_MASK 0x70
456 #define ARC_FARM_ARC0_AUX_LBU_PROT_OVR_LBU_RD_EN_SHIFT 8
457 #define ARC_FARM_ARC0_AUX_LBU_PROT_OVR_LBU_RD_EN_MASK 0x700
458 #define ARC_FARM_ARC0_AUX_LBU_PROT_OVR_LBU_WR_EN_SHIFT 12
459 #define ARC_FARM_ARC0_AUX_LBU_PROT_OVR_LBU_WR_EN_MASK 0x7000
460 
461 /* ARC_FARM_ARC0_AUX_LBU_MAX_OUTSTANDING */
462 #define ARC_FARM_ARC0_AUX_LBU_MAX_OUTSTANDING_LBU_READ_SHIFT 0
463 #define ARC_FARM_ARC0_AUX_LBU_MAX_OUTSTANDING_LBU_READ_MASK 0xFF
464 #define ARC_FARM_ARC0_AUX_LBU_MAX_OUTSTANDING_LBU_WRITE_SHIFT 8
465 #define ARC_FARM_ARC0_AUX_LBU_MAX_OUTSTANDING_LBU_WRITE_MASK 0xFF00
466 
467 /* ARC_FARM_ARC0_AUX_LBU_EARLY_BRESP_EN */
468 #define ARC_FARM_ARC0_AUX_LBU_EARLY_BRESP_EN_VAL_SHIFT 0
469 #define ARC_FARM_ARC0_AUX_LBU_EARLY_BRESP_EN_VAL_MASK 0x1
470 
471 /* ARC_FARM_ARC0_AUX_LBU_FORCE_RSP_OK */
472 #define ARC_FARM_ARC0_AUX_LBU_FORCE_RSP_OK_VAL_SHIFT 0
473 #define ARC_FARM_ARC0_AUX_LBU_FORCE_RSP_OK_VAL_MASK 0x1
474 
475 /* ARC_FARM_ARC0_AUX_LBU_NO_WR_INFLIGHT */
476 #define ARC_FARM_ARC0_AUX_LBU_NO_WR_INFLIGHT_VAL_SHIFT 0
477 #define ARC_FARM_ARC0_AUX_LBU_NO_WR_INFLIGHT_VAL_MASK 0x1
478 
479 /* ARC_FARM_ARC0_AUX_LBU_SEI_INTR_ID */
480 #define ARC_FARM_ARC0_AUX_LBU_SEI_INTR_ID_VAL_SHIFT 0
481 #define ARC_FARM_ARC0_AUX_LBU_SEI_INTR_ID_VAL_MASK 0x3FF
482 
483 /* ARC_FARM_ARC0_AUX_DCCM_QUEUE_BASE_ADDR */
484 #define ARC_FARM_ARC0_AUX_DCCM_QUEUE_BASE_ADDR_VAL_SHIFT 0
485 #define ARC_FARM_ARC0_AUX_DCCM_QUEUE_BASE_ADDR_VAL_MASK 0xFFFFFF
486 
487 /* ARC_FARM_ARC0_AUX_DCCM_QUEUE_SIZE */
488 #define ARC_FARM_ARC0_AUX_DCCM_QUEUE_SIZE_VAL_SHIFT 0
489 #define ARC_FARM_ARC0_AUX_DCCM_QUEUE_SIZE_VAL_MASK 0xFFFFFF
490 
491 /* ARC_FARM_ARC0_AUX_DCCM_QUEUE_PI */
492 #define ARC_FARM_ARC0_AUX_DCCM_QUEUE_PI_VAL_SHIFT 0
493 #define ARC_FARM_ARC0_AUX_DCCM_QUEUE_PI_VAL_MASK 0xFFFFFF
494 
495 /* ARC_FARM_ARC0_AUX_DCCM_QUEUE_CI */
496 #define ARC_FARM_ARC0_AUX_DCCM_QUEUE_CI_VAL_SHIFT 0
497 #define ARC_FARM_ARC0_AUX_DCCM_QUEUE_CI_VAL_MASK 0xFFFFFF
498 
499 /* ARC_FARM_ARC0_AUX_DCCM_QUEUE_PUSH_REG */
500 #define ARC_FARM_ARC0_AUX_DCCM_QUEUE_PUSH_REG_VAL_SHIFT 0
501 #define ARC_FARM_ARC0_AUX_DCCM_QUEUE_PUSH_REG_VAL_MASK 0xFFFFFFFF
502 
503 /* ARC_FARM_ARC0_AUX_DCCM_QUEUE_MAX_OCCUPANCY */
504 #define ARC_FARM_ARC0_AUX_DCCM_QUEUE_MAX_OCCUPANCY_VAL_SHIFT 0
505 #define ARC_FARM_ARC0_AUX_DCCM_QUEUE_MAX_OCCUPANCY_VAL_MASK 0xFFFFFF
506 
507 /* ARC_FARM_ARC0_AUX_DCCM_QUEUE_VALID_ENTRIES */
508 #define ARC_FARM_ARC0_AUX_DCCM_QUEUE_VALID_ENTRIES_VAL_SHIFT 0
509 #define ARC_FARM_ARC0_AUX_DCCM_QUEUE_VALID_ENTRIES_VAL_MASK 0xFFFFFF
510 
511 /* ARC_FARM_ARC0_AUX_GENERAL_Q_VLD_ENTRY_MASK */
512 #define ARC_FARM_ARC0_AUX_GENERAL_Q_VLD_ENTRY_MASK_VAL_SHIFT 0
513 #define ARC_FARM_ARC0_AUX_GENERAL_Q_VLD_ENTRY_MASK_VAL_MASK 0xFF
514 
515 /* ARC_FARM_ARC0_AUX_NIC_Q_VLD_ENTRY_MASK */
516 #define ARC_FARM_ARC0_AUX_NIC_Q_VLD_ENTRY_MASK_VAL_SHIFT 0
517 #define ARC_FARM_ARC0_AUX_NIC_Q_VLD_ENTRY_MASK_VAL_MASK 0xFF
518 
519 /* ARC_FARM_ARC0_AUX_DCCM_QUEUE_DROP_EN */
520 #define ARC_FARM_ARC0_AUX_DCCM_QUEUE_DROP_EN_VAL_SHIFT 0
521 #define ARC_FARM_ARC0_AUX_DCCM_QUEUE_DROP_EN_VAL_MASK 0x1
522 
523 /* ARC_FARM_ARC0_AUX_DCCM_QUEUE_WARN_MSG */
524 #define ARC_FARM_ARC0_AUX_DCCM_QUEUE_WARN_MSG_VAL_SHIFT 0
525 #define ARC_FARM_ARC0_AUX_DCCM_QUEUE_WARN_MSG_VAL_MASK 0xFFFF
526 
527 /* ARC_FARM_ARC0_AUX_DCCM_QUEUE_ALERT_MSG */
528 #define ARC_FARM_ARC0_AUX_DCCM_QUEUE_ALERT_MSG_VAL_SHIFT 0
529 #define ARC_FARM_ARC0_AUX_DCCM_QUEUE_ALERT_MSG_VAL_MASK 0xFFFF
530 
531 /* ARC_FARM_ARC0_AUX_DCCM_GEN_AXI_AWPROT */
532 #define ARC_FARM_ARC0_AUX_DCCM_GEN_AXI_AWPROT_VAL_SHIFT 0
533 #define ARC_FARM_ARC0_AUX_DCCM_GEN_AXI_AWPROT_VAL_MASK 0x7
534 
535 /* ARC_FARM_ARC0_AUX_DCCM_GEN_AXI_AWUSER */
536 #define ARC_FARM_ARC0_AUX_DCCM_GEN_AXI_AWUSER_VAL_SHIFT 0
537 #define ARC_FARM_ARC0_AUX_DCCM_GEN_AXI_AWUSER_VAL_MASK 0xFFFFFFFF
538 
539 /* ARC_FARM_ARC0_AUX_DCCM_GEN_AXI_AWBURST */
540 #define ARC_FARM_ARC0_AUX_DCCM_GEN_AXI_AWBURST_VAL_SHIFT 0
541 #define ARC_FARM_ARC0_AUX_DCCM_GEN_AXI_AWBURST_VAL_MASK 0x3
542 
543 /* ARC_FARM_ARC0_AUX_DCCM_GEN_AXI_AWLOCK */
544 #define ARC_FARM_ARC0_AUX_DCCM_GEN_AXI_AWLOCK_VAL_SHIFT 0
545 #define ARC_FARM_ARC0_AUX_DCCM_GEN_AXI_AWLOCK_VAL_MASK 0x1
546 
547 /* ARC_FARM_ARC0_AUX_DCCM_GEN_AXI_AWCACHE */
548 #define ARC_FARM_ARC0_AUX_DCCM_GEN_AXI_AWCACHE_VAL_SHIFT 0
549 #define ARC_FARM_ARC0_AUX_DCCM_GEN_AXI_AWCACHE_VAL_MASK 0xF
550 
551 /* ARC_FARM_ARC0_AUX_DCCM_WRR_ARB_WEIGHT */
552 #define ARC_FARM_ARC0_AUX_DCCM_WRR_ARB_WEIGHT_LBW_SLV_AXI_SHIFT 0
553 #define ARC_FARM_ARC0_AUX_DCCM_WRR_ARB_WEIGHT_LBW_SLV_AXI_MASK 0xF
554 #define ARC_FARM_ARC0_AUX_DCCM_WRR_ARB_WEIGHT_GEN_AXI_SHIFT 4
555 #define ARC_FARM_ARC0_AUX_DCCM_WRR_ARB_WEIGHT_GEN_AXI_MASK 0xF0
556 
557 /* ARC_FARM_ARC0_AUX_DCCM_Q_PUSH_FIFO_FULL_CFG */
558 #define ARC_FARM_ARC0_AUX_DCCM_Q_PUSH_FIFO_FULL_CFG_VAL_SHIFT 0
559 #define ARC_FARM_ARC0_AUX_DCCM_Q_PUSH_FIFO_FULL_CFG_VAL_MASK 0x1F
560 
561 /* ARC_FARM_ARC0_AUX_DCCM_Q_PUSH_FIFO_CNT */
562 #define ARC_FARM_ARC0_AUX_DCCM_Q_PUSH_FIFO_CNT_VAL_SHIFT 0
563 #define ARC_FARM_ARC0_AUX_DCCM_Q_PUSH_FIFO_CNT_VAL_MASK 0x1F
564 
565 /* ARC_FARM_ARC0_AUX_QMAN_CQ_IFIFO_SHADOW_CI */
566 #define ARC_FARM_ARC0_AUX_QMAN_CQ_IFIFO_SHADOW_CI_VAL_SHIFT 0
567 #define ARC_FARM_ARC0_AUX_QMAN_CQ_IFIFO_SHADOW_CI_VAL_MASK 0xFFFFFFFF
568 
569 /* ARC_FARM_ARC0_AUX_QMAN_ARC_CQ_IFIFO_SHADOW_CI */
570 #define ARC_FARM_ARC0_AUX_QMAN_ARC_CQ_IFIFO_SHADOW_CI_VAL_SHIFT 0
571 #define ARC_FARM_ARC0_AUX_QMAN_ARC_CQ_IFIFO_SHADOW_CI_VAL_MASK 0xFFFFFFFF
572 
573 /* ARC_FARM_ARC0_AUX_QMAN_CQ_SHADOW_CI */
574 #define ARC_FARM_ARC0_AUX_QMAN_CQ_SHADOW_CI_VAL_SHIFT 0
575 #define ARC_FARM_ARC0_AUX_QMAN_CQ_SHADOW_CI_VAL_MASK 0xFFFFFFFF
576 
577 /* ARC_FARM_ARC0_AUX_QMAN_ARC_CQ_SHADOW_CI */
578 #define ARC_FARM_ARC0_AUX_QMAN_ARC_CQ_SHADOW_CI_VAL_SHIFT 0
579 #define ARC_FARM_ARC0_AUX_QMAN_ARC_CQ_SHADOW_CI_VAL_MASK 0xFFFFFFFF
580 
581 /* ARC_FARM_ARC0_AUX_AUX2APB_PROT */
582 #define ARC_FARM_ARC0_AUX_AUX2APB_PROT_VAL_SHIFT 0
583 #define ARC_FARM_ARC0_AUX_AUX2APB_PROT_VAL_MASK 0x7
584 
585 /* ARC_FARM_ARC0_AUX_LBW_FORK_WIN_EN */
586 #define ARC_FARM_ARC0_AUX_LBW_FORK_WIN_EN_VAL_SHIFT 0
587 #define ARC_FARM_ARC0_AUX_LBW_FORK_WIN_EN_VAL_MASK 0x3
588 
589 /* ARC_FARM_ARC0_AUX_QMAN_LBW_FORK_BASE_ADDR0 */
590 #define ARC_FARM_ARC0_AUX_QMAN_LBW_FORK_BASE_ADDR0_VAL_SHIFT 0
591 #define ARC_FARM_ARC0_AUX_QMAN_LBW_FORK_BASE_ADDR0_VAL_MASK 0x7FFFFFF
592 
593 /* ARC_FARM_ARC0_AUX_QMAN_LBW_FORK_ADDR_MASK0 */
594 #define ARC_FARM_ARC0_AUX_QMAN_LBW_FORK_ADDR_MASK0_VAL_SHIFT 0
595 #define ARC_FARM_ARC0_AUX_QMAN_LBW_FORK_ADDR_MASK0_VAL_MASK 0x7FFFFFF
596 
597 /* ARC_FARM_ARC0_AUX_QMAN_LBW_FORK_BASE_ADDR1 */
598 #define ARC_FARM_ARC0_AUX_QMAN_LBW_FORK_BASE_ADDR1_VAL_SHIFT 0
599 #define ARC_FARM_ARC0_AUX_QMAN_LBW_FORK_BASE_ADDR1_VAL_MASK 0x7FFFFFF
600 
601 /* ARC_FARM_ARC0_AUX_QMAN_LBW_FORK_ADDR_MASK1 */
602 #define ARC_FARM_ARC0_AUX_QMAN_LBW_FORK_ADDR_MASK1_VAL_SHIFT 0
603 #define ARC_FARM_ARC0_AUX_QMAN_LBW_FORK_ADDR_MASK1_VAL_MASK 0x7FFFFFF
604 
605 /* ARC_FARM_ARC0_AUX_FARM_LBW_FORK_BASE_ADDR0 */
606 #define ARC_FARM_ARC0_AUX_FARM_LBW_FORK_BASE_ADDR0_VAL_SHIFT 0
607 #define ARC_FARM_ARC0_AUX_FARM_LBW_FORK_BASE_ADDR0_VAL_MASK 0x7FFFFFF
608 
609 /* ARC_FARM_ARC0_AUX_FARM_LBW_FORK_ADDR_MASK0 */
610 #define ARC_FARM_ARC0_AUX_FARM_LBW_FORK_ADDR_MASK0_VAL_SHIFT 0
611 #define ARC_FARM_ARC0_AUX_FARM_LBW_FORK_ADDR_MASK0_VAL_MASK 0x7FFFFFF
612 
613 /* ARC_FARM_ARC0_AUX_FARM_LBW_FORK_BASE_ADDR1 */
614 #define ARC_FARM_ARC0_AUX_FARM_LBW_FORK_BASE_ADDR1_VAL_SHIFT 0
615 #define ARC_FARM_ARC0_AUX_FARM_LBW_FORK_BASE_ADDR1_VAL_MASK 0x7FFFFFF
616 
617 /* ARC_FARM_ARC0_AUX_FARM_LBW_FORK_ADDR_MASK1 */
618 #define ARC_FARM_ARC0_AUX_FARM_LBW_FORK_ADDR_MASK1_VAL_SHIFT 0
619 #define ARC_FARM_ARC0_AUX_FARM_LBW_FORK_ADDR_MASK1_VAL_MASK 0x7FFFFFF
620 
621 /* ARC_FARM_ARC0_AUX_LBW_APB_FORK_MAX_ADDR0 */
622 #define ARC_FARM_ARC0_AUX_LBW_APB_FORK_MAX_ADDR0_VAL_SHIFT 0
623 #define ARC_FARM_ARC0_AUX_LBW_APB_FORK_MAX_ADDR0_VAL_MASK 0xFFFFFFFF
624 
625 /* ARC_FARM_ARC0_AUX_LBW_APB_FORK_MAX_ADDR1 */
626 #define ARC_FARM_ARC0_AUX_LBW_APB_FORK_MAX_ADDR1_VAL_SHIFT 0
627 #define ARC_FARM_ARC0_AUX_LBW_APB_FORK_MAX_ADDR1_VAL_MASK 0xFFFFFFFF
628 
629 /* ARC_FARM_ARC0_AUX_ARC_ACC_ENGS_LBW_FORK_MASK */
630 #define ARC_FARM_ARC0_AUX_ARC_ACC_ENGS_LBW_FORK_MASK_VAL_SHIFT 0
631 #define ARC_FARM_ARC0_AUX_ARC_ACC_ENGS_LBW_FORK_MASK_VAL_MASK 0x7FFFFFF
632 
633 /* ARC_FARM_ARC0_AUX_ARC_DUP_ENG_LBW_FORK_ADDR */
634 #define ARC_FARM_ARC0_AUX_ARC_DUP_ENG_LBW_FORK_ADDR_VAL_SHIFT 0
635 #define ARC_FARM_ARC0_AUX_ARC_DUP_ENG_LBW_FORK_ADDR_VAL_MASK 0x7FFFFFF
636 
637 /* ARC_FARM_ARC0_AUX_ARC_ACP_ENG_LBW_FORK_ADDR */
638 #define ARC_FARM_ARC0_AUX_ARC_ACP_ENG_LBW_FORK_ADDR_VAL_SHIFT 0
639 #define ARC_FARM_ARC0_AUX_ARC_ACP_ENG_LBW_FORK_ADDR_VAL_MASK 0x7FFFFFF
640 
641 /* ARC_FARM_ARC0_AUX_ARC_ACC_ENGS_VIRTUAL_ADDR */
642 #define ARC_FARM_ARC0_AUX_ARC_ACC_ENGS_VIRTUAL_ADDR_VAL_SHIFT 0
643 #define ARC_FARM_ARC0_AUX_ARC_ACC_ENGS_VIRTUAL_ADDR_VAL_MASK 0x7FFFFFF
644 
645 /* ARC_FARM_ARC0_AUX_CBU_FORK_WIN_EN */
646 #define ARC_FARM_ARC0_AUX_CBU_FORK_WIN_EN_VAL_SHIFT 0
647 #define ARC_FARM_ARC0_AUX_CBU_FORK_WIN_EN_VAL_MASK 0xF
648 
649 /* ARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR0_LSB */
650 #define ARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR0_LSB_VAL_SHIFT 0
651 #define ARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR0_LSB_VAL_MASK 0xFFFFFFFF
652 
653 /* ARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR0_MSB */
654 #define ARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR0_MSB_VAL_SHIFT 0
655 #define ARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR0_MSB_VAL_MASK 0xFFFFFFFF
656 
657 /* ARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK0_LSB */
658 #define ARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK0_LSB_VAL_SHIFT 0
659 #define ARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK0_LSB_VAL_MASK 0xFFFFFFFF
660 
661 /* ARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK0_MSB */
662 #define ARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK0_MSB_VAL_SHIFT 0
663 #define ARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK0_MSB_VAL_MASK 0xFFFFFFFF
664 
665 /* ARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR1_LSB */
666 #define ARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR1_LSB_VAL_SHIFT 0
667 #define ARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR1_LSB_VAL_MASK 0xFFFFFFFF
668 
669 /* ARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR1_MSB */
670 #define ARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR1_MSB_VAL_SHIFT 0
671 #define ARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR1_MSB_VAL_MASK 0xFFFFFFFF
672 
673 /* ARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK1_LSB */
674 #define ARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK1_LSB_VAL_SHIFT 0
675 #define ARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK1_LSB_VAL_MASK 0xFFFFFFFF
676 
677 /* ARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK1_MSB */
678 #define ARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK1_MSB_VAL_SHIFT 0
679 #define ARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK1_MSB_VAL_MASK 0xFFFFFFFF
680 
681 /* ARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR2_LSB */
682 #define ARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR2_LSB_VAL_SHIFT 0
683 #define ARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR2_LSB_VAL_MASK 0xFFFFFFFF
684 
685 /* ARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR2_MSB */
686 #define ARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR2_MSB_VAL_SHIFT 0
687 #define ARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR2_MSB_VAL_MASK 0xFFFFFFFF
688 
689 /* ARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK2_LSB */
690 #define ARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK2_LSB_VAL_SHIFT 0
691 #define ARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK2_LSB_VAL_MASK 0xFFFFFFFF
692 
693 /* ARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK2_MSB */
694 #define ARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK2_MSB_VAL_SHIFT 0
695 #define ARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK2_MSB_VAL_MASK 0xFFFFFFFF
696 
697 /* ARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR3_LSB */
698 #define ARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR3_LSB_VAL_SHIFT 0
699 #define ARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR3_LSB_VAL_MASK 0xFFFFFFFF
700 
701 /* ARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR3_MSB */
702 #define ARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR3_MSB_VAL_SHIFT 0
703 #define ARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR3_MSB_VAL_MASK 0xFFFFFFFF
704 
705 /* ARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK3_LSB */
706 #define ARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK3_LSB_VAL_SHIFT 0
707 #define ARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK3_LSB_VAL_MASK 0xFFFFFFFF
708 
709 /* ARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK3_MSB */
710 #define ARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK3_MSB_VAL_SHIFT 0
711 #define ARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK3_MSB_VAL_MASK 0xFFFFFFFF
712 
713 /* ARC_FARM_ARC0_AUX_CBU_TRMINATE_ARADDR_LSB */
714 #define ARC_FARM_ARC0_AUX_CBU_TRMINATE_ARADDR_LSB_VAL_SHIFT 0
715 #define ARC_FARM_ARC0_AUX_CBU_TRMINATE_ARADDR_LSB_VAL_MASK 0xFFFFFFFF
716 
717 /* ARC_FARM_ARC0_AUX_CBU_TRMINATE_ARADDR_MSB */
718 #define ARC_FARM_ARC0_AUX_CBU_TRMINATE_ARADDR_MSB_VAL_SHIFT 0
719 #define ARC_FARM_ARC0_AUX_CBU_TRMINATE_ARADDR_MSB_VAL_MASK 0xFFFFFFFF
720 
721 /* ARC_FARM_ARC0_AUX_CFG_CBU_TERMINATE_BRESP */
722 #define ARC_FARM_ARC0_AUX_CFG_CBU_TERMINATE_BRESP_VAL_SHIFT 0
723 #define ARC_FARM_ARC0_AUX_CFG_CBU_TERMINATE_BRESP_VAL_MASK 0x3
724 
725 /* ARC_FARM_ARC0_AUX_CFG_CBU_TERMINATE_RRESP */
726 #define ARC_FARM_ARC0_AUX_CFG_CBU_TERMINATE_RRESP_VAL_SHIFT 0
727 #define ARC_FARM_ARC0_AUX_CFG_CBU_TERMINATE_RRESP_VAL_MASK 0x3
728 
729 /* ARC_FARM_ARC0_AUX_ARC_REGION_CFG */
730 #define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_0_ASID_SHIFT 0
731 #define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_0_ASID_MASK 0x3FF
732 #define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_1_ASID_SHIFT 0
733 #define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_1_ASID_MASK 0x3FF
734 #define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_2_ASID_SHIFT 0
735 #define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_2_ASID_MASK 0x3FF
736 #define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_3_ASID_SHIFT 0
737 #define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_3_ASID_MASK 0x3FF
738 #define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_4_ASID_SHIFT 0
739 #define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_4_ASID_MASK 0x3FF
740 #define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_5_ASID_SHIFT 0
741 #define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_5_ASID_MASK 0x3FF
742 #define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_6_ASID_SHIFT 0
743 #define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_6_ASID_MASK 0x3FF
744 #define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_7_ASID_SHIFT 0
745 #define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_7_ASID_MASK 0x3FF
746 #define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_8_ASID_SHIFT 0
747 #define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_8_ASID_MASK 0x3FF
748 #define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_9_ASID_SHIFT 0
749 #define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_9_ASID_MASK 0x3FF
750 #define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_10_ASID_SHIFT 0
751 #define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_10_ASID_MASK 0x3FF
752 #define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_11_ASID_SHIFT 0
753 #define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_11_ASID_MASK 0x3FF
754 #define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_12_ASID_SHIFT 0
755 #define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_12_ASID_MASK 0x3FF
756 #define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_13_ASID_SHIFT 0
757 #define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_13_ASID_MASK 0x3FF
758 #define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_14_ASID_SHIFT 0
759 #define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_14_ASID_MASK 0x3FF
760 #define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_15_ASID_SHIFT 0
761 #define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_15_ASID_MASK 0x3FF
762 #define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_MMU_BP_SHIFT 12
763 #define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_MMU_BP_MASK 0x1000
764 #define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_PROT_VAL_SHIFT 16
765 #define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_PROT_VAL_MASK 0x70000
766 #define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_PROT_VAL_EN_SHIFT 20
767 #define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_PROT_VAL_EN_MASK 0x700000
768 
769 /* ARC_FARM_ARC0_AUX_DCCM_TRMINATE_AWADDR_ERR */
770 #define ARC_FARM_ARC0_AUX_DCCM_TRMINATE_AWADDR_ERR_VAL_SHIFT 0
771 #define ARC_FARM_ARC0_AUX_DCCM_TRMINATE_AWADDR_ERR_VAL_MASK 0xFFFFFF
772 
773 /* ARC_FARM_ARC0_AUX_DCCM_TRMINATE_ARADDR_ERR */
774 #define ARC_FARM_ARC0_AUX_DCCM_TRMINATE_ARADDR_ERR_VAL_SHIFT 0
775 #define ARC_FARM_ARC0_AUX_DCCM_TRMINATE_ARADDR_ERR_VAL_MASK 0xFFFFFF
776 
777 /* ARC_FARM_ARC0_AUX_CFG_DCCM_TERMINATE_BRESP */
778 #define ARC_FARM_ARC0_AUX_CFG_DCCM_TERMINATE_BRESP_VAL_SHIFT 0
779 #define ARC_FARM_ARC0_AUX_CFG_DCCM_TERMINATE_BRESP_VAL_MASK 0x3
780 
781 /* ARC_FARM_ARC0_AUX_CFG_DCCM_TERMINATE_RRESP */
782 #define ARC_FARM_ARC0_AUX_CFG_DCCM_TERMINATE_RRESP_VAL_SHIFT 0
783 #define ARC_FARM_ARC0_AUX_CFG_DCCM_TERMINATE_RRESP_VAL_MASK 0x3
784 
785 /* ARC_FARM_ARC0_AUX_CFG_DCCM_TERMINATE_EN */
786 #define ARC_FARM_ARC0_AUX_CFG_DCCM_TERMINATE_EN_VAL_SHIFT 0
787 #define ARC_FARM_ARC0_AUX_CFG_DCCM_TERMINATE_EN_VAL_MASK 0x1
788 
789 /* ARC_FARM_ARC0_AUX_CFG_DCCM_SECURE_REGION */
790 #define ARC_FARM_ARC0_AUX_CFG_DCCM_SECURE_REGION_VAL_SHIFT 0
791 #define ARC_FARM_ARC0_AUX_CFG_DCCM_SECURE_REGION_VAL_MASK 0xFFFFFF
792 
793 /* ARC_FARM_ARC0_AUX_ARC_AXI_ORDERING_WR_IF_CNT */
794 #define ARC_FARM_ARC0_AUX_ARC_AXI_ORDERING_WR_IF_CNT_VAL_SHIFT 0
795 #define ARC_FARM_ARC0_AUX_ARC_AXI_ORDERING_WR_IF_CNT_VAL_MASK 0xFFFFFFFF
796 
797 /* ARC_FARM_ARC0_AUX_ARC_AXI_ORDERING_CTL */
798 #define ARC_FARM_ARC0_AUX_ARC_AXI_ORDERING_CTL_ENABLE_BP_SHIFT 0
799 #define ARC_FARM_ARC0_AUX_ARC_AXI_ORDERING_CTL_ENABLE_BP_MASK 0x1
800 #define ARC_FARM_ARC0_AUX_ARC_AXI_ORDERING_CTL_RD_DELAY_CC_SHIFT 1
801 #define ARC_FARM_ARC0_AUX_ARC_AXI_ORDERING_CTL_RD_DELAY_CC_MASK 0x3E
802 
803 /* ARC_FARM_ARC0_AUX_ARC_AXI_ORDERING_ADDR_MSK */
804 #define ARC_FARM_ARC0_AUX_ARC_AXI_ORDERING_ADDR_MSK_VAL_SHIFT 0
805 #define ARC_FARM_ARC0_AUX_ARC_AXI_ORDERING_ADDR_MSK_VAL_MASK 0x7FFFFFF
806 
807 /* ARC_FARM_ARC0_AUX_ARC_AXI_ORDERING_ADDR */
808 #define ARC_FARM_ARC0_AUX_ARC_AXI_ORDERING_ADDR_VAL_SHIFT 0
809 #define ARC_FARM_ARC0_AUX_ARC_AXI_ORDERING_ADDR_VAL_MASK 0x7FFFFFF
810 
811 /* ARC_FARM_ARC0_AUX_ARC_ACC_ENGS_BUSER */
812 #define ARC_FARM_ARC0_AUX_ARC_ACC_ENGS_BUSER_VAL_SHIFT 0
813 #define ARC_FARM_ARC0_AUX_ARC_ACC_ENGS_BUSER_VAL_MASK 0x3
814 
815 /* ARC_FARM_ARC0_AUX_MME_ARC_UPPER_DCCM_EN */
816 #define ARC_FARM_ARC0_AUX_MME_ARC_UPPER_DCCM_EN_VAL_SHIFT 0
817 #define ARC_FARM_ARC0_AUX_MME_ARC_UPPER_DCCM_EN_VAL_MASK 0x1
818 
819 #endif /* ASIC_REG_ARC_FARM_ARC0_AUX_MASKS_H_ */
820