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Searched refs:AR933X_SRIF_DDR_DPLL3_REG (Results 1 – 2 of 2) sorted by relevance

/openbmc/u-boot/arch/mips/mach-ath79/ar933x/
H A Dlowlevel_init.S148 lw t1, AR933X_SRIF_DDR_DPLL3_REG(t0)
153 sw t1, AR933X_SRIF_DDR_DPLL3_REG(t0)
234 lw t1, AR933X_SRIF_DDR_DPLL3_REG(t0)
237 sw t1, AR933X_SRIF_DDR_DPLL3_REG(t0)
249 sw t1, AR933X_SRIF_DDR_DPLL3_REG(t0)
259 lw t1, AR933X_SRIF_DDR_DPLL3_REG(t0)
/openbmc/u-boot/arch/mips/mach-ath79/include/mach/
H A Dar71xx_regs.h1120 #define AR933X_SRIF_DDR_DPLL3_REG 0x248 macro