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Searched refs:AR933X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT (Results 1 – 2 of 2) sorted by relevance

/openbmc/u-boot/arch/mips/mach-ath79/ar933x/
H A Dclk.c64 div = ((val >> AR933X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) in get_clocks()
/openbmc/u-boot/arch/mips/mach-ath79/include/mach/
H A Dar71xx_regs.h345 #define AR933X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10 macro