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Searched refs:AR71XX_RESET_REG_PCI_INT_ENABLE (Results 1 – 3 of 3) sorted by relevance

/openbmc/linux/arch/mips/pci/
H A Dpci-ar71xx.c235 __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); in ar71xx_pci_irq_handler()
263 t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); in ar71xx_pci_irq_unmask()
264 __raw_writel(t | (1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE); in ar71xx_pci_irq_unmask()
267 __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); in ar71xx_pci_irq_unmask()
280 t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); in ar71xx_pci_irq_mask()
281 __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE); in ar71xx_pci_irq_mask()
284 __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); in ar71xx_pci_irq_mask()
299 __raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_ENABLE); in ar71xx_pci_irq_init()
/openbmc/u-boot/arch/mips/mach-ath79/include/mach/
H A Dar71xx_regs.h576 #define AR71XX_RESET_REG_PCI_INT_ENABLE 0x1c macro
/openbmc/linux/arch/mips/include/asm/mach-ath79/
H A Dar71xx_regs.h519 #define AR71XX_RESET_REG_PCI_INT_ENABLE 0x1c macro