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Searched refs:AR5K_REG_SM (Results 1 – 7 of 7) sorted by relevance

/openbmc/linux/drivers/net/wireless/ath/ath5k/
H A Dqcu.c293 | AR5K_REG_SM(ah->ah_retry_long, in ath5k_hw_set_tx_retry_limits()
295 | AR5K_REG_SM(ah->ah_retry_short, in ath5k_hw_set_tx_retry_limits()
297 | AR5K_REG_SM(ah->ah_retry_long, in ath5k_hw_set_tx_retry_limits()
299 | AR5K_REG_SM(ah->ah_retry_short, in ath5k_hw_set_tx_retry_limits()
305 AR5K_REG_SM(ah->ah_retry_long, in ath5k_hw_set_tx_retry_limits()
307 | AR5K_REG_SM(ah->ah_retry_long, in ath5k_hw_set_tx_retry_limits()
369 AR5K_REG_SM(tq->tqi_cbr_overflow_limit, in ath5k_hw_reset_tx_queue()
504 AR5K_REG_SM(ah->ah_txq_imr_txdesc, in ath5k_hw_reset_tx_queue()
510 AR5K_REG_SM(ah->ah_txq_imr_txeol, in ath5k_hw_reset_tx_queue()
517 AR5K_REG_SM(ah->ah_txq_imr_txurn, in ath5k_hw_reset_tx_queue()
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H A Ddesc.c143 AR5K_REG_SM(hdr_len, AR5K_2W_TX_DESC_CTL0_HEADER_LEN_5210); in ath5k_hw_setup_2word_tx_desc()
163 AR5K_REG_SM(tx_rate0, AR5K_2W_TX_DESC_CTL0_XMIT_RATE); in ath5k_hw_setup_2word_tx_desc()
167 AR5K_REG_SM(tx_rate0, AR5K_2W_TX_DESC_CTL0_XMIT_RATE) | in ath5k_hw_setup_2word_tx_desc()
168 AR5K_REG_SM(antenna_mode, in ath5k_hw_setup_2word_tx_desc()
171 AR5K_REG_SM(type, AR5K_2W_TX_DESC_CTL1_FRAME_TYPE_5211); in ath5k_hw_setup_2word_tx_desc()
203 AR5K_REG_SM(key_index, in ath5k_hw_setup_2word_tx_desc()
314 txctl1 |= AR5K_REG_SM(type, AR5K_4W_TX_DESC_CTL1_FRAME_TYPE); in ath5k_hw_setup_4word_tx_desc()
337 txctl1 |= AR5K_REG_SM(key_index, in ath5k_hw_setup_4word_tx_desc()
349 txctl3 |= AR5K_REG_SM(rtscts_rate, in ath5k_hw_setup_4word_tx_desc()
411 AR5K_REG_SM(tx_tries##_n, \ in ath5k_hw_setup_mrr_tx_desc()
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H A Dreset.c177 usec = AR5K_REG_SM(usec, AR5K_USEC_1); in ath5k_hw_init_core_clock()
195 sclock = AR5K_REG_SM(sclock, AR5K_USEC_32); in ath5k_hw_init_core_clock()
233 txlat = AR5K_REG_SM(txlat * 2, in ath5k_hw_init_core_clock()
235 rxlat = AR5K_REG_SM(AR5K_INIT_RX_LAT_MAX, in ath5k_hw_init_core_clock()
240 txlat = AR5K_REG_SM(txlat * 4, in ath5k_hw_init_core_clock()
242 rxlat = AR5K_REG_SM(AR5K_INIT_RX_LAT_MAX, in ath5k_hw_init_core_clock()
248 rxlat = AR5K_REG_SM(rxlat / 2, in ath5k_hw_init_core_clock()
856 (AR5K_REG_SM(2, in ath5k_hw_tweak_initval_settings()
858 AR5K_REG_SM(2, in ath5k_hw_tweak_initval_settings()
1003 AR5K_REG_SM((ee->ee_cck_ofdm_gain_delta * -1), in ath5k_hw_commit_eeprom_settings()
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H A Dphy.c1714 AR5K_REG_SM(-1, AR5K_PHY_SIG_FIRPWR), AR5K_PHY_SIG); in ath5k_hw_rf5110_calibrate()
1718 AR5K_REG_SM(-1, AR5K_PHY_AGCCOARSE_HI) | in ath5k_hw_rf5110_calibrate()
1723 AR5K_REG_SM(2, AR5K_PHY_ADCSAT_ICNT) | in ath5k_hw_rf5110_calibrate()
1724 AR5K_REG_SM(12, AR5K_PHY_ADCSAT_THR), AR5K_PHY_ADCSAT); in ath5k_hw_rf5110_calibrate()
2063 AR5K_REG_SM(spur_delta_phase, in ath5k_hw_set_spur_mitigation_filter()
2065 AR5K_REG_SM(spur_freq_sigma_delta, in ath5k_hw_set_spur_mitigation_filter()
3175 AR5K_REG_SM(pd_gain_overlap, in ath5k_combine_pwr_to_pdadc_curves()
3177 AR5K_REG_SM(gain_boundaries[0], in ath5k_combine_pwr_to_pdadc_curves()
3179 AR5K_REG_SM(gain_boundaries[1], in ath5k_combine_pwr_to_pdadc_curves()
3181 AR5K_REG_SM(gain_boundaries[2], in ath5k_combine_pwr_to_pdadc_curves()
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H A Ddma.c261 AR5K_REG_SM(100, AR5K_QUIET_CTL2_QT_PER)| in ath5k_hw_stop_tx_dma()
262 AR5K_REG_SM(10, AR5K_QUIET_CTL2_QT_DUR), in ath5k_hw_stop_tx_dma()
268 AR5K_REG_SM(ath5k_hw_reg_read(ah, in ath5k_hw_stop_tx_dma()
H A Dpcu.c992 AR5K_REG_SM(2, AR5K_QOS_NOACK_2BIT_VALUES) | in ath5k_hw_pcu_init()
993 AR5K_REG_SM(5, AR5K_QOS_NOACK_BIT_OFFSET) | in ath5k_hw_pcu_init()
994 AR5K_REG_SM(0, AR5K_QOS_NOACK_BYTE_OFFSET), in ath5k_hw_pcu_init()
H A Dath5k.h112 #define AR5K_REG_SM(_val, _flags) \ macro