Searched refs:APIC_BASE_MSR (Results 1 – 9 of 9) sorted by relevance
25 #define APIC_BASE_MSR 0x800 macro85 return rdmsr(APIC_BASE_MSR + (reg >> 4)); in x2apic_read_reg()90 wrmsr(APIC_BASE_MSR + (reg >> 4), value); in x2apic_write_reg()
196 wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0); in native_apic_msr_write()201 __wrmsr(APIC_BASE_MSR + (APIC_EOI >> 4), APIC_EOI_ACK, 0); in native_apic_msr_eoi()211 rdmsrl(APIC_BASE_MSR + (reg >> 4), msr); in native_apic_msr_read()217 wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low); in native_x2apic_icr_write()224 rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val); in native_x2apic_icr_read()
143 #define APIC_BASE_MSR 0x800 macro
508 return (msr >= APIC_BASE_MSR) && in is_x2apic_msrpm_offset()509 (msr < (APIC_BASE_MSR + 0x100)); in is_x2apic_msrpm_offset()
81 #define X2APIC_MSR(x) (APIC_BASE_MSR + (x >> 4))924 if ((index < APIC_BASE_MSR) || in svm_set_x2apic_msr_interception()925 (index > APIC_BASE_MSR + 0xff)) in svm_set_x2apic_msr_interception()
23 #define X2APIC_MSR(r) (APIC_BASE_MSR + ((r) >> 4))
4051 const int read_idx = APIC_BASE_MSR / BITS_PER_LONG_LONG; in vmx_update_msr_bitmap_x2apic()
3216 u32 reg = (msr - APIC_BASE_MSR) << 4; in kvm_x2apic_msr_write()3227 u32 reg = (msr - APIC_BASE_MSR) << 4; in kvm_x2apic_msr_read()
2192 case APIC_BASE_MSR + (APIC_ICR >> 4): in handle_fastpath_set_msr_irqoff()3732 case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff: in kvm_set_msr_common()4163 case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff: in kvm_get_msr_common()