Searched refs:ANADIG_DDR_PLL (Results 1 – 1 of 1) sorted by relevance
64 #define ANADIG_DDR_PLL 0x70 macro484 ANATOP_BASE_ADDR + ANADIG_DDR_PLL + REG_SET); in imx_pll_suspend()500 ANATOP_BASE_ADDR + ANADIG_DDR_PLL + REG_CLR); in imx_pll_resume()