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Searched refs:ALT_RSTMGR_PER1MODRST_WD0_SET_MSK (Results 1 – 2 of 2) sorted by relevance

/openbmc/u-boot/arch/arm/mach-socfpga/
H A Dreset_manager_arria10.c67 ALT_RSTMGR_PER1MODRST_WD0_SET_MSK); in socfpga_watchdog_disable()
117 ALT_RSTMGR_PER1MODRST_WD0_SET_MSK); in socfpga_reset_deassert_osc1wd0()
/openbmc/u-boot/arch/arm/mach-socfpga/include/mach/
H A Dreset_manager_arria10.h112 #define ALT_RSTMGR_PER1MODRST_WD0_SET_MSK BIT(0) macro