Searched refs:AK4375_11_PLL_FB_CLK_DIVIDER1 (Results 1 – 1 of 1) sorted by relevance
67 #define AK4375_11_PLL_FB_CLK_DIVIDER1 0x11 /* Feedback clock divider [15:8] bits */ macro351 snd_soc_component_write(component, AK4375_11_PLL_FB_CLK_DIVIDER1, (plm & 0xff00) >> 8); in ak4375_dai_set_pll()