1 /* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
2 /*
3  * Copyright (C) 2023, Intel Corporation
4  */
5 
6 #ifndef __DT_BINDINGS_INTEL_AGILEX5_CLKMGR_H
7 #define __DT_BINDINGS_INTEL_AGILEX5_CLKMGR_H
8 
9 /* fixed rate clocks */
10 #define AGILEX5_OSC1			0
11 #define AGILEX5_CB_INTOSC_HS_DIV2_CLK	1
12 #define AGILEX5_CB_INTOSC_LS_CLK	2
13 #define AGILEX5_F2S_FREE_CLK		3
14 
15 /* PLL clocks */
16 #define AGILEX5_MAIN_PLL_CLK		4
17 #define AGILEX5_MAIN_PLL_C0_CLK		5
18 #define AGILEX5_MAIN_PLL_C1_CLK		6
19 #define AGILEX5_MAIN_PLL_C2_CLK		7
20 #define AGILEX5_MAIN_PLL_C3_CLK		8
21 #define AGILEX5_PERIPH_PLL_CLK		9
22 #define AGILEX5_PERIPH_PLL_C0_CLK	10
23 #define AGILEX5_PERIPH_PLL_C1_CLK	11
24 #define AGILEX5_PERIPH_PLL_C2_CLK	12
25 #define AGILEX5_PERIPH_PLL_C3_CLK	13
26 #define AGILEX5_CORE0_FREE_CLK		14
27 #define AGILEX5_CORE1_FREE_CLK		15
28 #define AGILEX5_CORE2_FREE_CLK		16
29 #define AGILEX5_CORE3_FREE_CLK		17
30 #define AGILEX5_DSU_FREE_CLK		18
31 #define AGILEX5_BOOT_CLK		19
32 
33 /* fixed factor clocks */
34 #define AGILEX5_L3_MAIN_FREE_CLK	20
35 #define AGILEX5_NOC_FREE_CLK		21
36 #define AGILEX5_S2F_USR0_CLK		22
37 #define AGILEX5_NOC_CLK			23
38 #define AGILEX5_EMAC_A_FREE_CLK		24
39 #define AGILEX5_EMAC_B_FREE_CLK		25
40 #define AGILEX5_EMAC_PTP_FREE_CLK	26
41 #define AGILEX5_GPIO_DB_FREE_CLK	27
42 #define AGILEX5_S2F_USER0_FREE_CLK	28
43 #define AGILEX5_S2F_USER1_FREE_CLK	29
44 #define AGILEX5_PSI_REF_FREE_CLK	30
45 #define AGILEX5_USB31_FREE_CLK		31
46 
47 /* Gate clocks */
48 #define AGILEX5_CORE0_CLK		32
49 #define AGILEX5_CORE1_CLK		33
50 #define AGILEX5_CORE2_CLK		34
51 #define AGILEX5_CORE3_CLK		35
52 #define AGILEX5_MPU_CLK			36
53 #define AGILEX5_MPU_PERIPH_CLK		37
54 #define AGILEX5_MPU_CCU_CLK		38
55 #define AGILEX5_L4_MAIN_CLK		39
56 #define AGILEX5_L4_MP_CLK		40
57 #define AGILEX5_L4_SYS_FREE_CLK		41
58 #define AGILEX5_L4_SP_CLK		42
59 #define AGILEX5_CS_AT_CLK		43
60 #define AGILEX5_CS_TRACE_CLK		44
61 #define AGILEX5_CS_PDBG_CLK		45
62 #define AGILEX5_EMAC1_CLK		47
63 #define AGILEX5_EMAC2_CLK		48
64 #define AGILEX5_EMAC_PTP_CLK		49
65 #define AGILEX5_GPIO_DB_CLK		50
66 #define AGILEX5_S2F_USER0_CLK		51
67 #define AGILEX5_S2F_USER1_CLK		52
68 #define AGILEX5_PSI_REF_CLK		53
69 #define AGILEX5_USB31_SUSPEND_CLK	54
70 #define AGILEX5_EMAC0_CLK		46
71 #define AGILEX5_USB31_BUS_CLK_EARLY	55
72 #define AGILEX5_USB2OTG_HCLK		56
73 #define AGILEX5_SPIM_0_CLK		57
74 #define AGILEX5_SPIM_1_CLK		58
75 #define AGILEX5_SPIS_0_CLK		59
76 #define AGILEX5_SPIS_1_CLK		60
77 #define AGILEX5_DMA_CORE_CLK		61
78 #define AGILEX5_DMA_HS_CLK		62
79 #define AGILEX5_I3C_0_CORE_CLK		63
80 #define AGILEX5_I3C_1_CORE_CLK		64
81 #define AGILEX5_I2C_0_PCLK		65
82 #define AGILEX5_I2C_1_PCLK		66
83 #define AGILEX5_I2C_EMAC0_PCLK		67
84 #define AGILEX5_I2C_EMAC1_PCLK		68
85 #define AGILEX5_I2C_EMAC2_PCLK		69
86 #define AGILEX5_UART_0_PCLK		70
87 #define AGILEX5_UART_1_PCLK		71
88 #define AGILEX5_SPTIMER_0_PCLK		72
89 #define AGILEX5_SPTIMER_1_PCLK		73
90 #define AGILEX5_DFI_CLK			74
91 #define AGILEX5_NAND_NF_CLK		75
92 #define AGILEX5_NAND_BCH_CLK		76
93 #define AGILEX5_SDMMC_SDPHY_REG_CLK	77
94 #define AGILEX5_SDMCLK			78
95 #define AGILEX5_SOFTPHY_REG_PCLK	79
96 #define AGILEX5_SOFTPHY_PHY_CLK		80
97 #define AGILEX5_SOFTPHY_CTRL_CLK	81
98 #define AGILEX5_NUM_CLKS		82
99 
100 #endif	/* __DT_BINDINGS_INTEL_AGILEX5_CLKMGR_H */
101