1 // SPDX-License-Identifier: GPL-2.0-only
2
3 #include <linux/clk.h>
4 #include <linux/clkdev.h>
5 #include <linux/clk-provider.h>
6 #include <linux/delay.h>
7 #include <linux/err.h>
8 #include <linux/io.h>
9 #include <linux/math64.h>
10 #include <linux/module.h>
11 #include <linux/of_device.h>
12 #include <linux/string.h>
13
14 #define ADPLL_PLLSS_MMR_LOCK_OFFSET 0x00 /* Managed by MPPULL */
15 #define ADPLL_PLLSS_MMR_LOCK_ENABLED 0x1f125B64
16 #define ADPLL_PLLSS_MMR_UNLOCK_MAGIC 0x1eda4c3d
17
18 #define ADPLL_PWRCTRL_OFFSET 0x00
19 #define ADPLL_PWRCTRL_PONIN 5
20 #define ADPLL_PWRCTRL_PGOODIN 4
21 #define ADPLL_PWRCTRL_RET 3
22 #define ADPLL_PWRCTRL_ISORET 2
23 #define ADPLL_PWRCTRL_ISOSCAN 1
24 #define ADPLL_PWRCTRL_OFFMODE 0
25
26 #define ADPLL_CLKCTRL_OFFSET 0x04
27 #define ADPLL_CLKCTRL_CLKDCOLDOEN 29
28 #define ADPLL_CLKCTRL_IDLE 23
29 #define ADPLL_CLKCTRL_CLKOUTEN 20
30 #define ADPLL_CLKINPHIFSEL_ADPLL_S 19 /* REVISIT: which bit? */
31 #define ADPLL_CLKCTRL_CLKOUTLDOEN_ADPLL_LJ 19
32 #define ADPLL_CLKCTRL_ULOWCLKEN 18
33 #define ADPLL_CLKCTRL_CLKDCOLDOPWDNZ 17
34 #define ADPLL_CLKCTRL_M2PWDNZ 16
35 #define ADPLL_CLKCTRL_M3PWDNZ_ADPLL_S 15
36 #define ADPLL_CLKCTRL_LOWCURRSTDBY_ADPLL_S 13
37 #define ADPLL_CLKCTRL_LPMODE_ADPLL_S 12
38 #define ADPLL_CLKCTRL_REGM4XEN_ADPLL_S 10
39 #define ADPLL_CLKCTRL_SELFREQDCO_ADPLL_LJ 10
40 #define ADPLL_CLKCTRL_TINITZ 0
41
42 #define ADPLL_TENABLE_OFFSET 0x08
43 #define ADPLL_TENABLEDIV_OFFSET 0x8c
44
45 #define ADPLL_M2NDIV_OFFSET 0x10
46 #define ADPLL_M2NDIV_M2 16
47 #define ADPLL_M2NDIV_M2_ADPLL_S_WIDTH 5
48 #define ADPLL_M2NDIV_M2_ADPLL_LJ_WIDTH 7
49
50 #define ADPLL_MN2DIV_OFFSET 0x14
51 #define ADPLL_MN2DIV_N2 16
52
53 #define ADPLL_FRACDIV_OFFSET 0x18
54 #define ADPLL_FRACDIV_REGSD 24
55 #define ADPLL_FRACDIV_FRACTIONALM 0
56 #define ADPLL_FRACDIV_FRACTIONALM_MASK 0x3ffff
57
58 #define ADPLL_BWCTRL_OFFSET 0x1c
59 #define ADPLL_BWCTRL_BWCONTROL 1
60 #define ADPLL_BWCTRL_BW_INCR_DECRZ 0
61
62 #define ADPLL_RESERVED_OFFSET 0x20
63
64 #define ADPLL_STATUS_OFFSET 0x24
65 #define ADPLL_STATUS_PONOUT 31
66 #define ADPLL_STATUS_PGOODOUT 30
67 #define ADPLL_STATUS_LDOPWDN 29
68 #define ADPLL_STATUS_RECAL_BSTATUS3 28
69 #define ADPLL_STATUS_RECAL_OPPIN 27
70 #define ADPLL_STATUS_PHASELOCK 10
71 #define ADPLL_STATUS_FREQLOCK 9
72 #define ADPLL_STATUS_BYPASSACK 8
73 #define ADPLL_STATUS_LOSSREF 6
74 #define ADPLL_STATUS_CLKOUTENACK 5
75 #define ADPLL_STATUS_LOCK2 4
76 #define ADPLL_STATUS_M2CHANGEACK 3
77 #define ADPLL_STATUS_HIGHJITTER 1
78 #define ADPLL_STATUS_BYPASS 0
79 #define ADPLL_STATUS_PREPARED_MASK (BIT(ADPLL_STATUS_PHASELOCK) | \
80 BIT(ADPLL_STATUS_FREQLOCK))
81
82 #define ADPLL_M3DIV_OFFSET 0x28 /* Only on MPUPLL */
83 #define ADPLL_M3DIV_M3 0
84 #define ADPLL_M3DIV_M3_WIDTH 5
85 #define ADPLL_M3DIV_M3_MASK 0x1f
86
87 #define ADPLL_RAMPCTRL_OFFSET 0x2c /* Only on MPUPLL */
88 #define ADPLL_RAMPCTRL_CLKRAMPLEVEL 19
89 #define ADPLL_RAMPCTRL_CLKRAMPRATE 16
90 #define ADPLL_RAMPCTRL_RELOCK_RAMP_EN 0
91
92 #define MAX_ADPLL_INPUTS 3
93 #define MAX_ADPLL_OUTPUTS 4
94 #define ADPLL_MAX_RETRIES 5
95
96 #define to_dco(_hw) container_of(_hw, struct ti_adpll_dco_data, hw)
97 #define to_adpll(_hw) container_of(_hw, struct ti_adpll_data, dco)
98 #define to_clkout(_hw) container_of(_hw, struct ti_adpll_clkout_data, hw)
99
100 enum ti_adpll_clocks {
101 TI_ADPLL_DCO,
102 TI_ADPLL_DCO_GATE,
103 TI_ADPLL_N2,
104 TI_ADPLL_M2,
105 TI_ADPLL_M2_GATE,
106 TI_ADPLL_BYPASS,
107 TI_ADPLL_HIF,
108 TI_ADPLL_DIV2,
109 TI_ADPLL_CLKOUT,
110 TI_ADPLL_CLKOUT2,
111 TI_ADPLL_M3,
112 };
113
114 #define TI_ADPLL_NR_CLOCKS (TI_ADPLL_M3 + 1)
115
116 enum ti_adpll_inputs {
117 TI_ADPLL_CLKINP,
118 TI_ADPLL_CLKINPULOW,
119 TI_ADPLL_CLKINPHIF,
120 };
121
122 enum ti_adpll_s_outputs {
123 TI_ADPLL_S_DCOCLKLDO,
124 TI_ADPLL_S_CLKOUT,
125 TI_ADPLL_S_CLKOUTX2,
126 TI_ADPLL_S_CLKOUTHIF,
127 };
128
129 enum ti_adpll_lj_outputs {
130 TI_ADPLL_LJ_CLKDCOLDO,
131 TI_ADPLL_LJ_CLKOUT,
132 TI_ADPLL_LJ_CLKOUTLDO,
133 };
134
135 struct ti_adpll_platform_data {
136 const bool is_type_s;
137 const int nr_max_inputs;
138 const int nr_max_outputs;
139 const int output_index;
140 };
141
142 struct ti_adpll_clock {
143 struct clk *clk;
144 struct clk_lookup *cl;
145 void (*unregister)(struct clk *clk);
146 };
147
148 struct ti_adpll_dco_data {
149 struct clk_hw hw;
150 };
151
152 struct ti_adpll_clkout_data {
153 struct ti_adpll_data *adpll;
154 struct clk_gate gate;
155 struct clk_hw hw;
156 };
157
158 struct ti_adpll_data {
159 struct device *dev;
160 const struct ti_adpll_platform_data *c;
161 struct device_node *np;
162 unsigned long pa;
163 void __iomem *iobase;
164 void __iomem *regs;
165 spinlock_t lock; /* For ADPLL shared register access */
166 const char *parent_names[MAX_ADPLL_INPUTS];
167 struct clk *parent_clocks[MAX_ADPLL_INPUTS];
168 struct ti_adpll_clock *clocks;
169 struct clk_onecell_data outputs;
170 struct ti_adpll_dco_data dco;
171 };
172
ti_adpll_clk_get_name(struct ti_adpll_data * d,int output_index,const char * postfix)173 static const char *ti_adpll_clk_get_name(struct ti_adpll_data *d,
174 int output_index,
175 const char *postfix)
176 {
177 const char *name;
178 int err;
179
180 if (output_index >= 0) {
181 err = of_property_read_string_index(d->np,
182 "clock-output-names",
183 output_index,
184 &name);
185 if (err)
186 return NULL;
187 } else {
188 name = devm_kasprintf(d->dev, GFP_KERNEL, "%08lx.adpll.%s",
189 d->pa, postfix);
190 }
191
192 return name;
193 }
194
195 #define ADPLL_MAX_CON_ID 16 /* See MAX_CON_ID */
196
ti_adpll_setup_clock(struct ti_adpll_data * d,struct clk * clock,int index,int output_index,const char * name,void (* unregister)(struct clk * clk))197 static int ti_adpll_setup_clock(struct ti_adpll_data *d, struct clk *clock,
198 int index, int output_index, const char *name,
199 void (*unregister)(struct clk *clk))
200 {
201 struct clk_lookup *cl;
202 const char *postfix = NULL;
203 char con_id[ADPLL_MAX_CON_ID];
204
205 d->clocks[index].clk = clock;
206 d->clocks[index].unregister = unregister;
207
208 /* Separate con_id in format "pll040dcoclkldo" to fit MAX_CON_ID */
209 postfix = strrchr(name, '.');
210 if (postfix && strlen(postfix) > 1) {
211 if (strlen(postfix) > ADPLL_MAX_CON_ID)
212 dev_warn(d->dev, "clock %s con_id lookup may fail\n",
213 name);
214 snprintf(con_id, 16, "pll%03lx%s", d->pa & 0xfff, postfix + 1);
215 cl = clkdev_create(clock, con_id, NULL);
216 if (!cl)
217 return -ENOMEM;
218 d->clocks[index].cl = cl;
219 } else {
220 dev_warn(d->dev, "no con_id for clock %s\n", name);
221 }
222
223 if (output_index < 0)
224 return 0;
225
226 d->outputs.clks[output_index] = clock;
227 d->outputs.clk_num++;
228
229 return 0;
230 }
231
ti_adpll_init_divider(struct ti_adpll_data * d,enum ti_adpll_clocks index,int output_index,char * name,struct clk * parent_clock,void __iomem * reg,u8 shift,u8 width,u8 clk_divider_flags)232 static int ti_adpll_init_divider(struct ti_adpll_data *d,
233 enum ti_adpll_clocks index,
234 int output_index, char *name,
235 struct clk *parent_clock,
236 void __iomem *reg,
237 u8 shift, u8 width,
238 u8 clk_divider_flags)
239 {
240 const char *child_name;
241 const char *parent_name;
242 struct clk *clock;
243
244 child_name = ti_adpll_clk_get_name(d, output_index, name);
245 if (!child_name)
246 return -EINVAL;
247
248 parent_name = __clk_get_name(parent_clock);
249 clock = clk_register_divider(d->dev, child_name, parent_name, 0,
250 reg, shift, width, clk_divider_flags,
251 &d->lock);
252 if (IS_ERR(clock)) {
253 dev_err(d->dev, "failed to register divider %s: %li\n",
254 name, PTR_ERR(clock));
255 return PTR_ERR(clock);
256 }
257
258 return ti_adpll_setup_clock(d, clock, index, output_index, child_name,
259 clk_unregister_divider);
260 }
261
ti_adpll_init_mux(struct ti_adpll_data * d,enum ti_adpll_clocks index,char * name,struct clk * clk0,struct clk * clk1,void __iomem * reg,u8 shift)262 static int ti_adpll_init_mux(struct ti_adpll_data *d,
263 enum ti_adpll_clocks index,
264 char *name, struct clk *clk0,
265 struct clk *clk1,
266 void __iomem *reg,
267 u8 shift)
268 {
269 const char *child_name;
270 const char *parents[2];
271 struct clk *clock;
272
273 child_name = ti_adpll_clk_get_name(d, -ENODEV, name);
274 if (!child_name)
275 return -ENOMEM;
276 parents[0] = __clk_get_name(clk0);
277 parents[1] = __clk_get_name(clk1);
278 clock = clk_register_mux(d->dev, child_name, parents, 2, 0,
279 reg, shift, 1, 0, &d->lock);
280 if (IS_ERR(clock)) {
281 dev_err(d->dev, "failed to register mux %s: %li\n",
282 name, PTR_ERR(clock));
283 return PTR_ERR(clock);
284 }
285
286 return ti_adpll_setup_clock(d, clock, index, -ENODEV, child_name,
287 clk_unregister_mux);
288 }
289
ti_adpll_init_gate(struct ti_adpll_data * d,enum ti_adpll_clocks index,int output_index,char * name,struct clk * parent_clock,void __iomem * reg,u8 bit_idx,u8 clk_gate_flags)290 static int ti_adpll_init_gate(struct ti_adpll_data *d,
291 enum ti_adpll_clocks index,
292 int output_index, char *name,
293 struct clk *parent_clock,
294 void __iomem *reg,
295 u8 bit_idx,
296 u8 clk_gate_flags)
297 {
298 const char *child_name;
299 const char *parent_name;
300 struct clk *clock;
301
302 child_name = ti_adpll_clk_get_name(d, output_index, name);
303 if (!child_name)
304 return -EINVAL;
305
306 parent_name = __clk_get_name(parent_clock);
307 clock = clk_register_gate(d->dev, child_name, parent_name, 0,
308 reg, bit_idx, clk_gate_flags,
309 &d->lock);
310 if (IS_ERR(clock)) {
311 dev_err(d->dev, "failed to register gate %s: %li\n",
312 name, PTR_ERR(clock));
313 return PTR_ERR(clock);
314 }
315
316 return ti_adpll_setup_clock(d, clock, index, output_index, child_name,
317 clk_unregister_gate);
318 }
319
ti_adpll_init_fixed_factor(struct ti_adpll_data * d,enum ti_adpll_clocks index,char * name,struct clk * parent_clock,unsigned int mult,unsigned int div)320 static int ti_adpll_init_fixed_factor(struct ti_adpll_data *d,
321 enum ti_adpll_clocks index,
322 char *name,
323 struct clk *parent_clock,
324 unsigned int mult,
325 unsigned int div)
326 {
327 const char *child_name;
328 const char *parent_name;
329 struct clk *clock;
330
331 child_name = ti_adpll_clk_get_name(d, -ENODEV, name);
332 if (!child_name)
333 return -ENOMEM;
334
335 parent_name = __clk_get_name(parent_clock);
336 clock = clk_register_fixed_factor(d->dev, child_name, parent_name,
337 0, mult, div);
338 if (IS_ERR(clock))
339 return PTR_ERR(clock);
340
341 return ti_adpll_setup_clock(d, clock, index, -ENODEV, child_name,
342 clk_unregister);
343 }
344
ti_adpll_set_idle_bypass(struct ti_adpll_data * d)345 static void ti_adpll_set_idle_bypass(struct ti_adpll_data *d)
346 {
347 unsigned long flags;
348 u32 v;
349
350 spin_lock_irqsave(&d->lock, flags);
351 v = readl_relaxed(d->regs + ADPLL_CLKCTRL_OFFSET);
352 v |= BIT(ADPLL_CLKCTRL_IDLE);
353 writel_relaxed(v, d->regs + ADPLL_CLKCTRL_OFFSET);
354 spin_unlock_irqrestore(&d->lock, flags);
355 }
356
ti_adpll_clear_idle_bypass(struct ti_adpll_data * d)357 static void ti_adpll_clear_idle_bypass(struct ti_adpll_data *d)
358 {
359 unsigned long flags;
360 u32 v;
361
362 spin_lock_irqsave(&d->lock, flags);
363 v = readl_relaxed(d->regs + ADPLL_CLKCTRL_OFFSET);
364 v &= ~BIT(ADPLL_CLKCTRL_IDLE);
365 writel_relaxed(v, d->regs + ADPLL_CLKCTRL_OFFSET);
366 spin_unlock_irqrestore(&d->lock, flags);
367 }
368
ti_adpll_clock_is_bypass(struct ti_adpll_data * d)369 static bool ti_adpll_clock_is_bypass(struct ti_adpll_data *d)
370 {
371 u32 v;
372
373 v = readl_relaxed(d->regs + ADPLL_STATUS_OFFSET);
374
375 return v & BIT(ADPLL_STATUS_BYPASS);
376 }
377
378 /*
379 * Locked and bypass are not actually mutually exclusive: if you only care
380 * about the DCO clock and not CLKOUT you can clear M2PWDNZ before enabling
381 * the PLL, resulting in status (FREQLOCK | PHASELOCK | BYPASS) after lock.
382 */
ti_adpll_is_locked(struct ti_adpll_data * d)383 static bool ti_adpll_is_locked(struct ti_adpll_data *d)
384 {
385 u32 v = readl_relaxed(d->regs + ADPLL_STATUS_OFFSET);
386
387 return (v & ADPLL_STATUS_PREPARED_MASK) == ADPLL_STATUS_PREPARED_MASK;
388 }
389
ti_adpll_wait_lock(struct ti_adpll_data * d)390 static int ti_adpll_wait_lock(struct ti_adpll_data *d)
391 {
392 int retries = ADPLL_MAX_RETRIES;
393
394 do {
395 if (ti_adpll_is_locked(d))
396 return 0;
397 usleep_range(200, 300);
398 } while (retries--);
399
400 dev_err(d->dev, "pll failed to lock\n");
401 return -ETIMEDOUT;
402 }
403
ti_adpll_prepare(struct clk_hw * hw)404 static int ti_adpll_prepare(struct clk_hw *hw)
405 {
406 struct ti_adpll_dco_data *dco = to_dco(hw);
407 struct ti_adpll_data *d = to_adpll(dco);
408
409 ti_adpll_clear_idle_bypass(d);
410 ti_adpll_wait_lock(d);
411
412 return 0;
413 }
414
ti_adpll_unprepare(struct clk_hw * hw)415 static void ti_adpll_unprepare(struct clk_hw *hw)
416 {
417 struct ti_adpll_dco_data *dco = to_dco(hw);
418 struct ti_adpll_data *d = to_adpll(dco);
419
420 ti_adpll_set_idle_bypass(d);
421 }
422
ti_adpll_is_prepared(struct clk_hw * hw)423 static int ti_adpll_is_prepared(struct clk_hw *hw)
424 {
425 struct ti_adpll_dco_data *dco = to_dco(hw);
426 struct ti_adpll_data *d = to_adpll(dco);
427
428 return ti_adpll_is_locked(d);
429 }
430
431 /*
432 * Note that the DCO clock is never subject to bypass: if the PLL is off,
433 * dcoclk is low.
434 */
ti_adpll_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)435 static unsigned long ti_adpll_recalc_rate(struct clk_hw *hw,
436 unsigned long parent_rate)
437 {
438 struct ti_adpll_dco_data *dco = to_dco(hw);
439 struct ti_adpll_data *d = to_adpll(dco);
440 u32 frac_m, divider, v;
441 u64 rate;
442 unsigned long flags;
443
444 if (ti_adpll_clock_is_bypass(d))
445 return 0;
446
447 spin_lock_irqsave(&d->lock, flags);
448 frac_m = readl_relaxed(d->regs + ADPLL_FRACDIV_OFFSET);
449 frac_m &= ADPLL_FRACDIV_FRACTIONALM_MASK;
450 rate = (u64)readw_relaxed(d->regs + ADPLL_MN2DIV_OFFSET) << 18;
451 rate += frac_m;
452 rate *= parent_rate;
453 divider = (readw_relaxed(d->regs + ADPLL_M2NDIV_OFFSET) + 1) << 18;
454 spin_unlock_irqrestore(&d->lock, flags);
455
456 do_div(rate, divider);
457
458 if (d->c->is_type_s) {
459 v = readl_relaxed(d->regs + ADPLL_CLKCTRL_OFFSET);
460 if (v & BIT(ADPLL_CLKCTRL_REGM4XEN_ADPLL_S))
461 rate *= 4;
462 rate *= 2;
463 }
464
465 return rate;
466 }
467
468 /* PLL parent is always clkinp, bypass only affects the children */
ti_adpll_get_parent(struct clk_hw * hw)469 static u8 ti_adpll_get_parent(struct clk_hw *hw)
470 {
471 return 0;
472 }
473
474 static const struct clk_ops ti_adpll_ops = {
475 .prepare = ti_adpll_prepare,
476 .unprepare = ti_adpll_unprepare,
477 .is_prepared = ti_adpll_is_prepared,
478 .recalc_rate = ti_adpll_recalc_rate,
479 .get_parent = ti_adpll_get_parent,
480 };
481
ti_adpll_init_dco(struct ti_adpll_data * d)482 static int ti_adpll_init_dco(struct ti_adpll_data *d)
483 {
484 struct clk_init_data init;
485 struct clk *clock;
486 const char *postfix;
487 int width, err;
488
489 d->outputs.clks = devm_kcalloc(d->dev,
490 MAX_ADPLL_OUTPUTS,
491 sizeof(struct clk *),
492 GFP_KERNEL);
493 if (!d->outputs.clks)
494 return -ENOMEM;
495
496 if (d->c->output_index < 0)
497 postfix = "dco";
498 else
499 postfix = NULL;
500
501 init.name = ti_adpll_clk_get_name(d, d->c->output_index, postfix);
502 if (!init.name)
503 return -EINVAL;
504
505 init.parent_names = d->parent_names;
506 init.num_parents = d->c->nr_max_inputs;
507 init.ops = &ti_adpll_ops;
508 init.flags = CLK_GET_RATE_NOCACHE;
509 d->dco.hw.init = &init;
510
511 if (d->c->is_type_s)
512 width = 5;
513 else
514 width = 4;
515
516 /* Internal input clock divider N2 */
517 err = ti_adpll_init_divider(d, TI_ADPLL_N2, -ENODEV, "n2",
518 d->parent_clocks[TI_ADPLL_CLKINP],
519 d->regs + ADPLL_MN2DIV_OFFSET,
520 ADPLL_MN2DIV_N2, width, 0);
521 if (err)
522 return err;
523
524 clock = devm_clk_register(d->dev, &d->dco.hw);
525 if (IS_ERR(clock))
526 return PTR_ERR(clock);
527
528 return ti_adpll_setup_clock(d, clock, TI_ADPLL_DCO, d->c->output_index,
529 init.name, NULL);
530 }
531
ti_adpll_clkout_enable(struct clk_hw * hw)532 static int ti_adpll_clkout_enable(struct clk_hw *hw)
533 {
534 struct ti_adpll_clkout_data *co = to_clkout(hw);
535 struct clk_hw *gate_hw = &co->gate.hw;
536
537 __clk_hw_set_clk(gate_hw, hw);
538
539 return clk_gate_ops.enable(gate_hw);
540 }
541
ti_adpll_clkout_disable(struct clk_hw * hw)542 static void ti_adpll_clkout_disable(struct clk_hw *hw)
543 {
544 struct ti_adpll_clkout_data *co = to_clkout(hw);
545 struct clk_hw *gate_hw = &co->gate.hw;
546
547 __clk_hw_set_clk(gate_hw, hw);
548 clk_gate_ops.disable(gate_hw);
549 }
550
ti_adpll_clkout_is_enabled(struct clk_hw * hw)551 static int ti_adpll_clkout_is_enabled(struct clk_hw *hw)
552 {
553 struct ti_adpll_clkout_data *co = to_clkout(hw);
554 struct clk_hw *gate_hw = &co->gate.hw;
555
556 __clk_hw_set_clk(gate_hw, hw);
557
558 return clk_gate_ops.is_enabled(gate_hw);
559 }
560
561 /* Setting PLL bypass puts clkout and clkoutx2 into bypass */
ti_adpll_clkout_get_parent(struct clk_hw * hw)562 static u8 ti_adpll_clkout_get_parent(struct clk_hw *hw)
563 {
564 struct ti_adpll_clkout_data *co = to_clkout(hw);
565 struct ti_adpll_data *d = co->adpll;
566
567 return ti_adpll_clock_is_bypass(d);
568 }
569
ti_adpll_init_clkout(struct ti_adpll_data * d,enum ti_adpll_clocks index,int output_index,int gate_bit,char * name,struct clk * clk0,struct clk * clk1)570 static int ti_adpll_init_clkout(struct ti_adpll_data *d,
571 enum ti_adpll_clocks index,
572 int output_index, int gate_bit,
573 char *name, struct clk *clk0,
574 struct clk *clk1)
575 {
576 struct ti_adpll_clkout_data *co;
577 struct clk_init_data init;
578 struct clk_ops *ops;
579 const char *parent_names[2];
580 const char *child_name;
581 struct clk *clock;
582 int err;
583
584 co = devm_kzalloc(d->dev, sizeof(*co), GFP_KERNEL);
585 if (!co)
586 return -ENOMEM;
587 co->adpll = d;
588
589 err = of_property_read_string_index(d->np,
590 "clock-output-names",
591 output_index,
592 &child_name);
593 if (err)
594 return err;
595
596 ops = devm_kzalloc(d->dev, sizeof(*ops), GFP_KERNEL);
597 if (!ops)
598 return -ENOMEM;
599
600 init.name = child_name;
601 init.ops = ops;
602 init.flags = 0;
603 co->hw.init = &init;
604 parent_names[0] = __clk_get_name(clk0);
605 parent_names[1] = __clk_get_name(clk1);
606 init.parent_names = parent_names;
607 init.num_parents = 2;
608
609 ops->get_parent = ti_adpll_clkout_get_parent;
610 ops->determine_rate = __clk_mux_determine_rate;
611 if (gate_bit) {
612 co->gate.lock = &d->lock;
613 co->gate.reg = d->regs + ADPLL_CLKCTRL_OFFSET;
614 co->gate.bit_idx = gate_bit;
615 ops->enable = ti_adpll_clkout_enable;
616 ops->disable = ti_adpll_clkout_disable;
617 ops->is_enabled = ti_adpll_clkout_is_enabled;
618 }
619
620 clock = devm_clk_register(d->dev, &co->hw);
621 if (IS_ERR(clock)) {
622 dev_err(d->dev, "failed to register output %s: %li\n",
623 name, PTR_ERR(clock));
624 return PTR_ERR(clock);
625 }
626
627 return ti_adpll_setup_clock(d, clock, index, output_index, child_name,
628 NULL);
629 }
630
ti_adpll_init_children_adpll_s(struct ti_adpll_data * d)631 static int ti_adpll_init_children_adpll_s(struct ti_adpll_data *d)
632 {
633 int err;
634
635 if (!d->c->is_type_s)
636 return 0;
637
638 /* Internal mux, sources from divider N2 or clkinpulow */
639 err = ti_adpll_init_mux(d, TI_ADPLL_BYPASS, "bypass",
640 d->clocks[TI_ADPLL_N2].clk,
641 d->parent_clocks[TI_ADPLL_CLKINPULOW],
642 d->regs + ADPLL_CLKCTRL_OFFSET,
643 ADPLL_CLKCTRL_ULOWCLKEN);
644 if (err)
645 return err;
646
647 /* Internal divider M2, sources DCO */
648 err = ti_adpll_init_divider(d, TI_ADPLL_M2, -ENODEV, "m2",
649 d->clocks[TI_ADPLL_DCO].clk,
650 d->regs + ADPLL_M2NDIV_OFFSET,
651 ADPLL_M2NDIV_M2,
652 ADPLL_M2NDIV_M2_ADPLL_S_WIDTH,
653 CLK_DIVIDER_ONE_BASED);
654 if (err)
655 return err;
656
657 /* Internal fixed divider, after M2 before clkout */
658 err = ti_adpll_init_fixed_factor(d, TI_ADPLL_DIV2, "div2",
659 d->clocks[TI_ADPLL_M2].clk,
660 1, 2);
661 if (err)
662 return err;
663
664 /* Output clkout with a mux and gate, sources from div2 or bypass */
665 err = ti_adpll_init_clkout(d, TI_ADPLL_CLKOUT, TI_ADPLL_S_CLKOUT,
666 ADPLL_CLKCTRL_CLKOUTEN, "clkout",
667 d->clocks[TI_ADPLL_DIV2].clk,
668 d->clocks[TI_ADPLL_BYPASS].clk);
669 if (err)
670 return err;
671
672 /* Output clkoutx2 with a mux and gate, sources from M2 or bypass */
673 err = ti_adpll_init_clkout(d, TI_ADPLL_CLKOUT2, TI_ADPLL_S_CLKOUTX2, 0,
674 "clkout2", d->clocks[TI_ADPLL_M2].clk,
675 d->clocks[TI_ADPLL_BYPASS].clk);
676 if (err)
677 return err;
678
679 /* Internal mux, sources from DCO and clkinphif */
680 if (d->parent_clocks[TI_ADPLL_CLKINPHIF]) {
681 err = ti_adpll_init_mux(d, TI_ADPLL_HIF, "hif",
682 d->clocks[TI_ADPLL_DCO].clk,
683 d->parent_clocks[TI_ADPLL_CLKINPHIF],
684 d->regs + ADPLL_CLKCTRL_OFFSET,
685 ADPLL_CLKINPHIFSEL_ADPLL_S);
686 if (err)
687 return err;
688 }
689
690 /* Output clkouthif with a divider M3, sources from hif */
691 err = ti_adpll_init_divider(d, TI_ADPLL_M3, TI_ADPLL_S_CLKOUTHIF, "m3",
692 d->clocks[TI_ADPLL_HIF].clk,
693 d->regs + ADPLL_M3DIV_OFFSET,
694 ADPLL_M3DIV_M3,
695 ADPLL_M3DIV_M3_WIDTH,
696 CLK_DIVIDER_ONE_BASED);
697 if (err)
698 return err;
699
700 /* Output clock dcoclkldo is the DCO */
701
702 return 0;
703 }
704
ti_adpll_init_children_adpll_lj(struct ti_adpll_data * d)705 static int ti_adpll_init_children_adpll_lj(struct ti_adpll_data *d)
706 {
707 int err;
708
709 if (d->c->is_type_s)
710 return 0;
711
712 /* Output clkdcoldo, gated output of DCO */
713 err = ti_adpll_init_gate(d, TI_ADPLL_DCO_GATE, TI_ADPLL_LJ_CLKDCOLDO,
714 "clkdcoldo", d->clocks[TI_ADPLL_DCO].clk,
715 d->regs + ADPLL_CLKCTRL_OFFSET,
716 ADPLL_CLKCTRL_CLKDCOLDOEN, 0);
717 if (err)
718 return err;
719
720 /* Internal divider M2, sources from DCO */
721 err = ti_adpll_init_divider(d, TI_ADPLL_M2, -ENODEV,
722 "m2", d->clocks[TI_ADPLL_DCO].clk,
723 d->regs + ADPLL_M2NDIV_OFFSET,
724 ADPLL_M2NDIV_M2,
725 ADPLL_M2NDIV_M2_ADPLL_LJ_WIDTH,
726 CLK_DIVIDER_ONE_BASED);
727 if (err)
728 return err;
729
730 /* Output clkoutldo, gated output of M2 */
731 err = ti_adpll_init_gate(d, TI_ADPLL_M2_GATE, TI_ADPLL_LJ_CLKOUTLDO,
732 "clkoutldo", d->clocks[TI_ADPLL_M2].clk,
733 d->regs + ADPLL_CLKCTRL_OFFSET,
734 ADPLL_CLKCTRL_CLKOUTLDOEN_ADPLL_LJ,
735 0);
736 if (err)
737 return err;
738
739 /* Internal mux, sources from divider N2 or clkinpulow */
740 err = ti_adpll_init_mux(d, TI_ADPLL_BYPASS, "bypass",
741 d->clocks[TI_ADPLL_N2].clk,
742 d->parent_clocks[TI_ADPLL_CLKINPULOW],
743 d->regs + ADPLL_CLKCTRL_OFFSET,
744 ADPLL_CLKCTRL_ULOWCLKEN);
745 if (err)
746 return err;
747
748 /* Output clkout, sources M2 or bypass */
749 err = ti_adpll_init_clkout(d, TI_ADPLL_CLKOUT, TI_ADPLL_S_CLKOUT,
750 ADPLL_CLKCTRL_CLKOUTEN, "clkout",
751 d->clocks[TI_ADPLL_M2].clk,
752 d->clocks[TI_ADPLL_BYPASS].clk);
753 if (err)
754 return err;
755
756 return 0;
757 }
758
ti_adpll_free_resources(struct ti_adpll_data * d)759 static void ti_adpll_free_resources(struct ti_adpll_data *d)
760 {
761 int i;
762
763 for (i = TI_ADPLL_M3; i >= 0; i--) {
764 struct ti_adpll_clock *ac = &d->clocks[i];
765
766 if (!ac || IS_ERR_OR_NULL(ac->clk))
767 continue;
768 if (ac->cl)
769 clkdev_drop(ac->cl);
770 if (ac->unregister)
771 ac->unregister(ac->clk);
772 }
773 }
774
775 /* MPU PLL manages the lock register for all PLLs */
ti_adpll_unlock_all(void __iomem * reg)776 static void ti_adpll_unlock_all(void __iomem *reg)
777 {
778 u32 v;
779
780 v = readl_relaxed(reg);
781 if (v == ADPLL_PLLSS_MMR_LOCK_ENABLED)
782 writel_relaxed(ADPLL_PLLSS_MMR_UNLOCK_MAGIC, reg);
783 }
784
ti_adpll_init_registers(struct ti_adpll_data * d)785 static int ti_adpll_init_registers(struct ti_adpll_data *d)
786 {
787 int register_offset = 0;
788
789 if (d->c->is_type_s) {
790 register_offset = 8;
791 ti_adpll_unlock_all(d->iobase + ADPLL_PLLSS_MMR_LOCK_OFFSET);
792 }
793
794 d->regs = d->iobase + register_offset + ADPLL_PWRCTRL_OFFSET;
795
796 return 0;
797 }
798
ti_adpll_init_inputs(struct ti_adpll_data * d)799 static int ti_adpll_init_inputs(struct ti_adpll_data *d)
800 {
801 static const char error[] = "need at least %i inputs";
802 struct clk *clock;
803 int nr_inputs;
804
805 nr_inputs = of_clk_get_parent_count(d->np);
806 if (nr_inputs < d->c->nr_max_inputs) {
807 dev_err(d->dev, error, nr_inputs);
808 return -EINVAL;
809 }
810 of_clk_parent_fill(d->np, d->parent_names, nr_inputs);
811
812 clock = devm_clk_get(d->dev, d->parent_names[0]);
813 if (IS_ERR(clock)) {
814 dev_err(d->dev, "could not get clkinp\n");
815 return PTR_ERR(clock);
816 }
817 d->parent_clocks[TI_ADPLL_CLKINP] = clock;
818
819 clock = devm_clk_get(d->dev, d->parent_names[1]);
820 if (IS_ERR(clock)) {
821 dev_err(d->dev, "could not get clkinpulow clock\n");
822 return PTR_ERR(clock);
823 }
824 d->parent_clocks[TI_ADPLL_CLKINPULOW] = clock;
825
826 if (d->c->is_type_s) {
827 clock = devm_clk_get(d->dev, d->parent_names[2]);
828 if (IS_ERR(clock)) {
829 dev_err(d->dev, "could not get clkinphif clock\n");
830 return PTR_ERR(clock);
831 }
832 d->parent_clocks[TI_ADPLL_CLKINPHIF] = clock;
833 }
834
835 return 0;
836 }
837
838 static const struct ti_adpll_platform_data ti_adpll_type_s = {
839 .is_type_s = true,
840 .nr_max_inputs = MAX_ADPLL_INPUTS,
841 .nr_max_outputs = MAX_ADPLL_OUTPUTS,
842 .output_index = TI_ADPLL_S_DCOCLKLDO,
843 };
844
845 static const struct ti_adpll_platform_data ti_adpll_type_lj = {
846 .is_type_s = false,
847 .nr_max_inputs = MAX_ADPLL_INPUTS - 1,
848 .nr_max_outputs = MAX_ADPLL_OUTPUTS - 1,
849 .output_index = -EINVAL,
850 };
851
852 static const struct of_device_id ti_adpll_match[] = {
853 { .compatible = "ti,dm814-adpll-s-clock", &ti_adpll_type_s },
854 { .compatible = "ti,dm814-adpll-lj-clock", &ti_adpll_type_lj },
855 {},
856 };
857 MODULE_DEVICE_TABLE(of, ti_adpll_match);
858
ti_adpll_probe(struct platform_device * pdev)859 static int ti_adpll_probe(struct platform_device *pdev)
860 {
861 struct device_node *node = pdev->dev.of_node;
862 struct device *dev = &pdev->dev;
863 const struct of_device_id *match;
864 const struct ti_adpll_platform_data *pdata;
865 struct ti_adpll_data *d;
866 struct resource *res;
867 int err;
868
869 match = of_match_device(ti_adpll_match, dev);
870 if (match)
871 pdata = match->data;
872 else
873 return -ENODEV;
874
875 d = devm_kzalloc(dev, sizeof(*d), GFP_KERNEL);
876 if (!d)
877 return -ENOMEM;
878 d->dev = dev;
879 d->np = node;
880 d->c = pdata;
881 dev_set_drvdata(d->dev, d);
882 spin_lock_init(&d->lock);
883
884 d->iobase = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
885 if (IS_ERR(d->iobase))
886 return PTR_ERR(d->iobase);
887 d->pa = res->start;
888
889 err = ti_adpll_init_registers(d);
890 if (err)
891 return err;
892
893 err = ti_adpll_init_inputs(d);
894 if (err)
895 return err;
896
897 d->clocks = devm_kcalloc(d->dev,
898 TI_ADPLL_NR_CLOCKS,
899 sizeof(struct ti_adpll_clock),
900 GFP_KERNEL);
901 if (!d->clocks)
902 return -ENOMEM;
903
904 err = ti_adpll_init_dco(d);
905 if (err) {
906 dev_err(dev, "could not register dco: %i\n", err);
907 goto free;
908 }
909
910 err = ti_adpll_init_children_adpll_s(d);
911 if (err)
912 goto free;
913 err = ti_adpll_init_children_adpll_lj(d);
914 if (err)
915 goto free;
916
917 err = of_clk_add_provider(d->np, of_clk_src_onecell_get, &d->outputs);
918 if (err)
919 goto free;
920
921 return 0;
922
923 free:
924 WARN_ON(1);
925 ti_adpll_free_resources(d);
926
927 return err;
928 }
929
ti_adpll_remove(struct platform_device * pdev)930 static void ti_adpll_remove(struct platform_device *pdev)
931 {
932 struct ti_adpll_data *d = dev_get_drvdata(&pdev->dev);
933
934 ti_adpll_free_resources(d);
935 }
936
937 static struct platform_driver ti_adpll_driver = {
938 .driver = {
939 .name = "ti-adpll",
940 .of_match_table = ti_adpll_match,
941 },
942 .probe = ti_adpll_probe,
943 .remove_new = ti_adpll_remove,
944 };
945
ti_adpll_init(void)946 static int __init ti_adpll_init(void)
947 {
948 return platform_driver_register(&ti_adpll_driver);
949 }
950 core_initcall(ti_adpll_init);
951
ti_adpll_exit(void)952 static void __exit ti_adpll_exit(void)
953 {
954 platform_driver_unregister(&ti_adpll_driver);
955 }
956 module_exit(ti_adpll_exit);
957
958 MODULE_DESCRIPTION("Clock driver for dm814x ADPLL");
959 MODULE_ALIAS("platform:dm814-adpll-clock");
960 MODULE_AUTHOR("Tony LIndgren <tony@atomide.com>");
961 MODULE_LICENSE("GPL v2");
962