Searched refs:ADDR_MASK (Results 1 – 9 of 9) sorted by relevance
66 #define RCR(addr) (RCRCODE | (addr & ADDR_MASK)) /* Read Control Register */67 #define WCR(addr) (WCRCODE | (addr & ADDR_MASK)) /* Write Control Register */70 #define BFS(addr) (BFSCODE | (addr & ADDR_MASK)) /* Bit Field Set */71 #define BFC(addr) (BFCCODE | (addr & ADDR_MASK)) /* Bit Field Clear */89 #define ADDR_MASK 0x1F macro
64 u8 banked_reg = reg & ADDR_MASK; in regmap_encx24j600_sfr_read()115 u8 banked_reg = reg & ADDR_MASK; in regmap_encx24j600_sfr_update()
19 #define ADDR_MASK 0x1F macro
155 tx_buf[0] = op | (addr & ADDR_MASK); in spi_read_op()174 priv->spi_transfer_buf[0] = op | (addr & ADDR_MASK); in spi_write_op()
47 #define ADDR_MASK 0xF0 macro104 u8 addr = (amsg->cmd & ADDR_MASK) >> 4; in adb_iop_listen()
79 #define ADDR_MASK 0xF0 macro198 poll_addr = (last_poll_cmd & ADDR_MASK) >> 4; in macii_queue_poll()
41 #define ADDR_MASK 0x03ffffff /* op_code|addr : 31...26|25 ....0 */ macro46 ((unsigned int)(JAL | (((addr) >> 2) & ADDR_MASK)))
318 adrmask = ioread32(&hw->reg->ADDR_MASK); in pch_gbe_mac_mar_set()319 iowrite32((adrmask | (0x0001 << index)), &hw->reg->ADDR_MASK); in pch_gbe_mac_mar_set()321 pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY); in pch_gbe_mac_mar_set()328 pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY); in pch_gbe_mac_mar_set()380 iowrite32(0xFFFE, &hw->reg->ADDR_MASK); in pch_gbe_mac_init_rx_addrs()382 pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY); in pch_gbe_mac_init_rx_addrs()444 wu_evt, ioread32(&hw->reg->ADDR_MASK)); in pch_gbe_mac_set_wol_event()448 addr_mask = ioread32(&hw->reg->ADDR_MASK); in pch_gbe_mac_set_wol_event()2105 adrmask = ioread32(&hw->reg->ADDR_MASK); in pch_gbe_set_multi()2106 iowrite32(adrmask | BIT(i), &hw->reg->ADDR_MASK); in pch_gbe_set_multi()[all …]
62 u32 ADDR_MASK; member