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Searched refs:ACC_W1C (Results 1 – 4 of 4) sorted by relevance

/openbmc/qemu/hw/net/fsl_etsec/
H A Dregisters.c30 {0x010, "IEVENT", "Interrupt event register", ACC_W1C, 0x00000000},
49 {0x104, "TSTAT", "Transmit status register", ACC_W1C, 0x00000000},
83 {0x304, "RSTAT", "Receive status register", ACC_W1C, 0x00000000},
213 {0x730, "CAR1", "Carry register one register", ACC_W1C, 0x00000000},
214 {0x734, "CAR2", "Carry register two register ", ACC_W1C, 0x00000000},
270 {0xE04, "TMR_TEVENT", "time stamp event register", ACC_W1C, 0x00000000},
H A Dmiim.c127 case ACC_W1C: in etsec_write_miim()
H A Detsec.c96 case ACC_W1C: in etsec_read()
269 case ACC_W1C: in etsec_write()
H A Dregisters.h32 ACC_W1C = 4, /* Write 1 to clear */ enumerator