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/openbmc/qemu/target/arm/tcg/
H A Dcpu32.c23 void aa32_max_features(ARMCPU *cpu) in aa32_max_features() argument
28 t = cpu->isar.id_isar5; in aa32_max_features()
35 cpu->isar.id_isar5 = t; in aa32_max_features()
37 t = cpu->isar.id_isar6; in aa32_max_features()
45 cpu->isar.id_isar6 = t; in aa32_max_features()
47 t = cpu->isar.mvfr1; in aa32_max_features()
50 cpu->isar.mvfr1 = t; in aa32_max_features()
52 t = cpu->isar.mvfr2; in aa32_max_features()
55 cpu->isar.mvfr2 = t; in aa32_max_features()
57 t = cpu->isar.id_mmfr3; in aa32_max_features()
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H A Dcpu-v7m.c23 ARMCPU *cpu = ARM_CPU(cs); in arm_v7m_cpu_exec_interrupt() local
24 CPUARMState *env = &cpu->env; in arm_v7m_cpu_exec_interrupt()
48 ARMCPU *cpu = ARM_CPU(obj); in cortex_m0_initfn() local
49 set_feature(&cpu->env, ARM_FEATURE_V6); in cortex_m0_initfn()
50 set_feature(&cpu->env, ARM_FEATURE_M); in cortex_m0_initfn()
52 cpu->midr = 0x410cc200; in cortex_m0_initfn()
62 cpu->isar.id_pfr0 = 0x00000030; in cortex_m0_initfn()
63 cpu->isar.id_pfr1 = 0x00000200; in cortex_m0_initfn()
64 cpu->isar.id_dfr0 = 0x00100000; in cortex_m0_initfn()
65 cpu->id_afr0 = 0x00000000; in cortex_m0_initfn()
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H A Dcpu64.c34 ARMCPU *cpu = ARM_CPU(obj); in aarch64_a35_initfn() local
36 cpu->dtb_compatible = "arm,cortex-a35"; in aarch64_a35_initfn()
37 set_feature(&cpu->env, ARM_FEATURE_V8); in aarch64_a35_initfn()
38 set_feature(&cpu->env, ARM_FEATURE_NEON); in aarch64_a35_initfn()
39 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); in aarch64_a35_initfn()
40 set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); in aarch64_a35_initfn()
41 set_feature(&cpu->env, ARM_FEATURE_AARCH64); in aarch64_a35_initfn()
42 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); in aarch64_a35_initfn()
43 set_feature(&cpu->env, ARM_FEATURE_EL2); in aarch64_a35_initfn()
44 set_feature(&cpu->env, ARM_FEATURE_EL3); in aarch64_a35_initfn()
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/openbmc/qemu/tests/tcg/mips/user/ase/msa/
H A Dtest_msa_run_64r6eb.sh8 $PATH_TO_QEMU -cpu I6400 /tmp/test_msa_nloc_b_64r6eb
9 $PATH_TO_QEMU -cpu I6400 /tmp/test_msa_nloc_h_64r6eb
10 $PATH_TO_QEMU -cpu I6400 /tmp/test_msa_nloc_w_64r6eb
11 $PATH_TO_QEMU -cpu I6400 /tmp/test_msa_nloc_d_64r6eb
12 $PATH_TO_QEMU -cpu I6400 /tmp/test_msa_nlzc_b_64r6eb
13 $PATH_TO_QEMU -cpu I6400 /tmp/test_msa_nlzc_h_64r6eb
14 $PATH_TO_QEMU -cpu I6400 /tmp/test_msa_nlzc_w_64r6eb
15 $PATH_TO_QEMU -cpu I6400 /tmp/test_msa_nlzc_d_64r6eb
16 $PATH_TO_QEMU -cpu I6400 /tmp/test_msa_pcnt_b_64r6eb
17 $PATH_TO_QEMU -cpu I6400 /tmp/test_msa_pcnt_h_64r6eb
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H A Dtest_msa_run_32r5eb.sh8 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nloc_b_32r5eb
9 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nloc_h_32r5eb
10 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nloc_w_32r5eb
11 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nloc_d_32r5eb
12 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nlzc_b_32r5eb
13 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nlzc_h_32r5eb
14 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nlzc_w_32r5eb
15 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nlzc_d_32r5eb
16 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_pcnt_b_32r5eb
17 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_pcnt_h_32r5eb
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H A Dtest_msa_run_64r6el.sh8 $PATH_TO_QEMU -cpu I6400 /tmp/test_msa_nloc_b_64r6el
9 $PATH_TO_QEMU -cpu I6400 /tmp/test_msa_nloc_h_64r6el
10 $PATH_TO_QEMU -cpu I6400 /tmp/test_msa_nloc_w_64r6el
11 $PATH_TO_QEMU -cpu I6400 /tmp/test_msa_nloc_d_64r6el
12 $PATH_TO_QEMU -cpu I6400 /tmp/test_msa_nlzc_b_64r6el
13 $PATH_TO_QEMU -cpu I6400 /tmp/test_msa_nlzc_h_64r6el
14 $PATH_TO_QEMU -cpu I6400 /tmp/test_msa_nlzc_w_64r6el
15 $PATH_TO_QEMU -cpu I6400 /tmp/test_msa_nlzc_d_64r6el
16 $PATH_TO_QEMU -cpu I6400 /tmp/test_msa_pcnt_b_64r6el
17 $PATH_TO_QEMU -cpu I6400 /tmp/test_msa_pcnt_h_64r6el
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H A Dtest_msa_run_32r5el.sh8 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nloc_b_32r5el
9 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nloc_h_32r5el
10 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nloc_w_32r5el
11 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nloc_d_32r5el
12 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nlzc_b_32r5el
13 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nlzc_h_32r5el
14 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nlzc_w_32r5el
15 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nlzc_d_32r5el
16 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_pcnt_b_32r5el
17 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_pcnt_h_32r5el
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/openbmc/qemu/accel/tcg/
H A Dtcg-accel-ops-rr.c43 CPUState *cpu; in rr_kick_vcpu_thread() local
45 CPU_FOREACH(cpu) { in rr_kick_vcpu_thread()
46 cpu_exit(cpu); in rr_kick_vcpu_thread()
73 CPUState *cpu; in rr_kick_next_cpu() local
75 cpu = qatomic_read(&rr_current_cpu); in rr_kick_next_cpu()
76 if (cpu) { in rr_kick_next_cpu()
77 cpu_exit(cpu); in rr_kick_next_cpu()
81 } while (cpu != qatomic_read(&rr_current_cpu)); in rr_kick_next_cpu()
110 CPUState *cpu; in rr_wait_io_event() local
119 CPU_FOREACH(cpu) { in rr_wait_io_event()
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H A Dcpu-exec.c66 static void align_clocks(SyncClocks *sc, CPUState *cpu) in align_clocks() argument
74 cpu_icount = cpu->icount_extra + cpu->neg.icount_decr.u16.low; in align_clocks()
117 static void init_delay_params(SyncClocks *sc, CPUState *cpu) in init_delay_params() argument
125 = cpu->icount_extra + cpu->neg.icount_decr.u16.low; in init_delay_params()
138 static void align_clocks(SyncClocks *sc, const CPUState *cpu) in align_clocks() argument
142 static void init_delay_params(SyncClocks *sc, const CPUState *cpu) in init_delay_params() argument
147 bool tcg_cflags_has(CPUState *cpu, uint32_t flags) in tcg_cflags_has() argument
149 return cpu->tcg_cflags & flags; in tcg_cflags_has()
152 void tcg_cflags_set(CPUState *cpu, uint32_t flags) in tcg_cflags_set() argument
154 cpu->tcg_cflags |= flags; in tcg_cflags_set()
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/openbmc/qemu/target/arm/
H A Dcpu64.c39 void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) in arm_cpu_sve_finalize() argument
56 uint32_t vq_map = cpu->sve_vq.map; in arm_cpu_sve_finalize()
57 uint32_t vq_init = cpu->sve_vq.init; in arm_cpu_sve_finalize()
70 cpu->sve_vq.supported = kvm_arm_sve_get_vls(cpu); in arm_cpu_sve_finalize()
71 vq_supported = cpu->sve_vq.supported; in arm_cpu_sve_finalize()
73 assert(!cpu_isar_feature(aa64_sve, cpu)); in arm_cpu_sve_finalize()
77 vq_supported = cpu->sve_vq.supported; in arm_cpu_sve_finalize()
89 if (cpu->sve_max_vq && max_vq > cpu->sve_max_vq) { in arm_cpu_sve_finalize()
93 max_vq * 128, cpu->sve_max_vq, in arm_cpu_sve_finalize()
94 cpu->sve_max_vq * 128); in arm_cpu_sve_finalize()
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/openbmc/qemu/target/i386/hvf/
H A Dx86.h198 #define x86_reg(cpu, reg) ((x86_register *) &cpu->regs[reg]) argument
200 #define RRX(cpu, reg) (x86_reg(cpu, reg)->rrx) argument
201 #define RAX(cpu) RRX(cpu, R_EAX) argument
202 #define RCX(cpu) RRX(cpu, R_ECX) argument
203 #define RDX(cpu) RRX(cpu, R_EDX) argument
204 #define RBX(cpu) RRX(cpu, R_EBX) argument
205 #define RSP(cpu) RRX(cpu, R_ESP) argument
206 #define RBP(cpu) RRX(cpu, R_EBP) argument
207 #define RSI(cpu) RRX(cpu, R_ESI) argument
208 #define RDI(cpu) RRX(cpu, R_EDI) argument
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/openbmc/qemu/system/
H A Dcpus.c76 bool cpu_is_stopped(CPUState *cpu) in cpu_is_stopped() argument
78 return cpu->stopped || !runstate_is_running(); in cpu_is_stopped()
81 bool cpu_work_list_empty(CPUState *cpu) in cpu_work_list_empty() argument
83 return QSIMPLEQ_EMPTY_ATOMIC(&cpu->work_list); in cpu_work_list_empty()
86 bool cpu_thread_is_idle(CPUState *cpu) in cpu_thread_is_idle() argument
88 if (cpu->stop || !cpu_work_list_empty(cpu)) { in cpu_thread_is_idle()
91 if (cpu_is_stopped(cpu)) { in cpu_thread_is_idle()
94 if (!cpu->halted || cpu_has_work(cpu)) { in cpu_thread_is_idle()
98 return cpus_accel->cpu_thread_is_idle(cpu); in cpu_thread_is_idle()
105 CPUState *cpu; in all_cpu_threads_idle() local
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/openbmc/linux/drivers/cpufreq/
H A Dintel_pstate.c229 int cpu; member
284 int (*get_max)(int cpu);
285 int (*get_max_physical)(int cpu);
286 int (*get_min)(int cpu);
287 int (*get_turbo)(int cpu);
289 int (*get_cpu_scaling)(int cpu);
352 static void intel_pstate_set_itmt_prio(int cpu) in intel_pstate_set_itmt_prio() argument
358 ret = cppc_get_perf_caps(cpu, &cppc_perf); in intel_pstate_set_itmt_prio()
367 cppc_perf.highest_perf = HWP_HIGHEST_PERF(READ_ONCE(all_cpu_data[cpu]->hwp_cap_cached)); in intel_pstate_set_itmt_prio()
374 sched_set_itmt_core_prio(cppc_perf.highest_perf, cpu); in intel_pstate_set_itmt_prio()
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/openbmc/qemu/hw/core/
H A Dcpu-common.c40 CPUState *cpu; in cpu_by_arch_id() local
42 CPU_FOREACH(cpu) { in cpu_by_arch_id()
43 CPUClass *cc = CPU_GET_CLASS(cpu); in cpu_by_arch_id()
45 if (cc->get_arch_id(cpu) == id) { in cpu_by_arch_id()
46 return cpu; in cpu_by_arch_id()
60 CPUState *cpu = CPU(object_new(typename)); in cpu_create() local
61 if (!qdev_realize(DEVICE(cpu), NULL, &err)) { in cpu_create()
63 object_unref(OBJECT(cpu)); in cpu_create()
66 return cpu; in cpu_create()
71 void cpu_reset_interrupt(CPUState *cpu, int mask) in cpu_reset_interrupt() argument
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/openbmc/linux/arch/arm/boot/dts/intel/axm/
H A Daxm5516-cpus.dtsi13 cpu-map {
16 cpu = <&CPU0>;
19 cpu = <&CPU1>;
22 cpu = <&CPU2>;
25 cpu = <&CPU3>;
30 cpu = <&CPU4>;
33 cpu = <&CPU5>;
36 cpu = <&CPU6>;
39 cpu = <&CPU7>;
44 cpu = <&CPU8>;
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/openbmc/linux/arch/powerpc/kernel/
H A Dsmp.c286 void smp_muxed_ipi_set_message(int cpu, int msg) in smp_muxed_ipi_set_message() argument
288 struct cpu_messages *info = &per_cpu(ipi_message, cpu); in smp_muxed_ipi_set_message()
298 void smp_muxed_ipi_message_pass(int cpu, int msg) in smp_muxed_ipi_message_pass() argument
300 smp_muxed_ipi_set_message(cpu, msg); in smp_muxed_ipi_message_pass()
306 smp_ops->cause_ipi(cpu); in smp_muxed_ipi_message_pass()
360 static inline void do_message_pass(int cpu, int msg) in do_message_pass() argument
363 smp_ops->message_pass(cpu, msg); in do_message_pass()
366 smp_muxed_ipi_message_pass(cpu, msg); in do_message_pass()
370 void arch_smp_send_reschedule(int cpu) in arch_smp_send_reschedule() argument
373 do_message_pass(cpu, PPC_MSG_RESCHEDULE); in arch_smp_send_reschedule()
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/openbmc/linux/drivers/base/
H A Darch_topology.c63 int cpu; in topology_set_scale_freq_source() local
74 for_each_cpu(cpu, cpus) { in topology_set_scale_freq_source()
75 sfd = rcu_dereference(*per_cpu_ptr(&sft_data, cpu)); in topology_set_scale_freq_source()
79 rcu_assign_pointer(per_cpu(sft_data, cpu), data); in topology_set_scale_freq_source()
80 cpumask_set_cpu(cpu, &scale_freq_counters_mask); in topology_set_scale_freq_source()
94 int cpu; in topology_clear_scale_freq_source() local
98 for_each_cpu(cpu, cpus) { in topology_clear_scale_freq_source()
99 sfd = rcu_dereference(*per_cpu_ptr(&sft_data, cpu)); in topology_clear_scale_freq_source()
102 rcu_assign_pointer(per_cpu(sft_data, cpu), NULL); in topology_clear_scale_freq_source()
103 cpumask_clear_cpu(cpu, &scale_freq_counters_mask); in topology_clear_scale_freq_source()
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/openbmc/linux/tools/testing/selftests/cpu-hotplug/
H A Dcpu-on-off-test.sh27 if ! ls $SYSFS/devices/system/cpu/cpu* > /dev/null 2>&1; then
28 echo $msg cpu hotplug is not supported >&2
33 online_cpus=`cat $SYSFS/devices/system/cpu/online`
41 present_cpus=`cat $SYSFS/devices/system/cpu/present`
47 offline_cpus=`cat $SYSFS/devices/system/cpu/offline`
63 for cpu in $SYSFS/devices/system/cpu/cpu*; do
64 if [ -f $cpu/online ] && grep -q $state $cpu/online; then
65 echo ${cpu##/*/cpu}
82 grep -q 1 $SYSFS/devices/system/cpu/cpu$1/online
87 grep -q 0 $SYSFS/devices/system/cpu/cpu$1/online
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/openbmc/linux/include/linux/
H A Dtopology.h94 static inline int cpu_to_node(int cpu) in cpu_to_node() argument
96 return per_cpu(numa_node, cpu); in cpu_to_node()
108 static inline void set_cpu_numa_node(int cpu, int node) in set_cpu_numa_node() argument
110 per_cpu(numa_node, cpu) = node; in set_cpu_numa_node()
151 static inline int cpu_to_mem(int cpu) in cpu_to_mem() argument
153 return per_cpu(_numa_mem_, cpu); in cpu_to_mem()
158 static inline void set_cpu_numa_mem(int cpu, int node) in set_cpu_numa_mem() argument
160 per_cpu(_numa_mem_, cpu) = node; in set_cpu_numa_mem()
175 static inline int cpu_to_mem(int cpu) in cpu_to_mem() argument
177 return cpu_to_node(cpu); in cpu_to_mem()
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/openbmc/openbmc/poky/meta/recipes-support/boost/boost/
H A D0001-Don-t-set-up-arch-instruction-set-flags-we-do-that-o.patch19 @@ -1144,156 +1144,3 @@ local rule cpu-flags ( toolset variable : architecture : instruction-set + :
31 -cpu-flags gcc OPTIONS : x86 : native : -march=native ;
32 -cpu-flags gcc OPTIONS : x86 : i486 : -march=i486 ;
33 -cpu-flags gcc OPTIONS : x86 : i586 : -march=i586 ;
34 -cpu-flags gcc OPTIONS : x86 : i686 : -march=i686 ;
35 -cpu-flags gcc OPTIONS : x86 : pentium : -march=pentium ;
36 -cpu-flags gcc OPTIONS : x86 : pentium-mmx : -march=pentium-mmx ;
37 -cpu-flags gcc OPTIONS : x86 : pentiumpro : -march=pentiumpro ;
38 -cpu-flags gcc OPTIONS : x86 : pentium2 : -march=pentium2 ;
39 -cpu-flags gcc OPTIONS : x86 : pentium3 : -march=pentium3 ;
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/openbmc/u-boot/arch/arm/dts/
H A Dthunderx-88xx.dtsi24 cpu@000 {
25 device_type = "cpu";
30 cpu@001 {
31 device_type = "cpu";
36 cpu@002 {
37 device_type = "cpu";
42 cpu@003 {
43 device_type = "cpu";
48 cpu@004 {
49 device_type = "cpu";
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/openbmc/linux/Documentation/translations/zh_CN/scheduler/
H A Dsched-bwc.rst24 达“配额”微秒的CPU时间。当cgroup中的线程可运行时，该配额以时间片段的方式被分配到每个cpu
29 它以需求为基础被转移到cpu-local“筒仓”，在每次更新中转移的数量是可调整的，被描述为“片“（时
65 配额、周期和突发是在cpu子系统内通过cgroupfs管理的。
69 :ref:`Documentation/admin-guide/cgroup-v2.rst <cgroup-v2-cpu>`.
71 - cpu.cfs_quota_us：在一个时期内补充的运行时间（微秒）。
72 - cpu.cfs_period_us：一个周期的长度（微秒）。
73 - cpu.stat: 输出节流统计数据[下面进一步解释]
74 - cpu.cfs_burst_us：最大累积运行时间（微秒）。
78 cpu.cfs_period_us=100ms
79 cpu.cfs_quota_us=-1
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/openbmc/qemu/
H A Dcpu-common.c82 void cpu_list_add(CPUState *cpu) in cpu_list_add() argument
87 if (cpu->cpu_index == UNASSIGNED_CPU_INDEX) { in cpu_list_add()
89 cpu->cpu_index = cpu_get_free_index(); in cpu_list_add()
90 assert(cpu->cpu_index != UNASSIGNED_CPU_INDEX); in cpu_list_add()
94 QTAILQ_INSERT_TAIL_RCU(&cpus_queue, cpu, node); in cpu_list_add()
98 void cpu_list_remove(CPUState *cpu) in cpu_list_remove() argument
101 if (!QTAILQ_IN_USE(cpu, node)) { in cpu_list_remove()
106 QTAILQ_REMOVE_RCU(&cpus_queue, cpu, node); in cpu_list_remove()
107 cpu->cpu_index = UNASSIGNED_CPU_INDEX; in cpu_list_remove()
113 CPUState *cpu; in qemu_get_cpu() local
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/openbmc/linux/arch/microblaze/kernel/cpu/
H A Dcpuinfo-static.c23 void __init set_cpuinfo_static(struct cpuinfo *ci, struct device_node *cpu) in set_cpuinfo_static() argument
28 (fcpu(cpu, "xlnx,use-barrel") ? PVR0_USE_BARREL_MASK : 0) | in set_cpuinfo_static()
29 (fcpu(cpu, "xlnx,use-msr-instr") ? PVR2_USE_MSR_INSTR : 0) | in set_cpuinfo_static()
30 (fcpu(cpu, "xlnx,use-pcmp-instr") ? PVR2_USE_PCMP_INSTR : 0) | in set_cpuinfo_static()
31 (fcpu(cpu, "xlnx,use-div") ? PVR0_USE_DIV_MASK : 0); in set_cpuinfo_static()
43 ci->use_mult = fcpu(cpu, "xlnx,use-hw-mul"); in set_cpuinfo_static()
51 ci->use_fpu = fcpu(cpu, "xlnx,use-fpu"); in set_cpuinfo_static()
59 (fcpu(cpu, "xlnx,unaligned-exceptions") ? in set_cpuinfo_static()
61 (fcpu(cpu, "xlnx,ill-opcode-exception") ? in set_cpuinfo_static()
63 (fcpu(cpu, "xlnx,iopb-bus-exception") ? in set_cpuinfo_static()
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/openbmc/linux/arch/arm/mach-meson/
H A Dplatsmp.c38 static struct reset_control *meson_smp_get_core_reset(int cpu) in meson_smp_get_core_reset() argument
40 struct device_node *np = of_get_cpu_node(cpu, 0); in meson_smp_get_core_reset()
45 static void meson_smp_set_cpu_ctrl(int cpu, bool on_off) in meson_smp_set_cpu_ctrl() argument
50 val |= BIT(cpu); in meson_smp_set_cpu_ctrl()
52 val &= ~BIT(cpu); in meson_smp_set_cpu_ctrl()
116 static void meson_smp_begin_secondary_boot(unsigned int cpu) in meson_smp_begin_secondary_boot() argument
125 sram_base + MESON_SMP_SRAM_CPU_CTRL_ADDR_REG(cpu)); in meson_smp_begin_secondary_boot()
131 scu_cpu_power_enable(scu_base, cpu); in meson_smp_begin_secondary_boot()
134 static int meson_smp_finalize_secondary_boot(unsigned int cpu) in meson_smp_finalize_secondary_boot() argument
139 while (readl(sram_base + MESON_SMP_SRAM_CPU_CTRL_ADDR_REG(cpu))) { in meson_smp_finalize_secondary_boot()
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