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Searched refs:CL (Results 1 – 25 of 75) sorted by relevance

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/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/subdev/fb/
H A Dsddr3.c72 int CWL, CL, WR, DLL = 0, ODT = 0; in nvkm_sddr3_calc() local
83 CL = ram->next->bios.timing_10_CL; in nvkm_sddr3_calc()
89 CL = (ram->next->bios.timing[1] & 0x0000001f) >> 0; in nvkm_sddr3_calc()
101 CL = ramxlat(ramddr3_cl, CL); in nvkm_sddr3_calc()
103 if (CL < 0 || CWL < 0 || WR < 0) in nvkm_sddr3_calc()
108 ram->mr[0] |= (CL & 0x0e) << 3; in nvkm_sddr3_calc()
109 ram->mr[0] |= (CL & 0x01) << 2; in nvkm_sddr3_calc()
H A Dgddr3.c73 int CL, WR, CWL, DLL = 0, ODT = 0, RON, hi; in nvkm_gddr3_calc() local
78 CL = ram->next->bios.timing_10_CL; in nvkm_gddr3_calc()
86 CL = (ram->next->bios.timing[1] & 0x0000001f) >> 0; in nvkm_gddr3_calc()
102 CL = ramxlat(hi ? ramgddr3_cl_hi : ramgddr3_cl_lo, CL); in nvkm_gddr3_calc()
104 if (CL < 0 || CWL < 1 || CWL > 7 || WR < 0) in nvkm_gddr3_calc()
109 ram->mr[0] |= (CL & 0x07) << 4; in nvkm_gddr3_calc()
110 ram->mr[0] |= (CL & 0x08) >> 1; in nvkm_gddr3_calc()
H A Dsddr2.c63 int CL, WR, DLL = 0, ODT = 0; in nvkm_sddr2_calc() local
67 CL = ram->next->bios.timing_10_CL; in nvkm_sddr2_calc()
73 CL = (ram->next->bios.timing[1] & 0x0000001f); in nvkm_sddr2_calc()
86 CL = ramxlat(ramddr2_cl, CL); in nvkm_sddr2_calc()
88 if (CL < 0 || WR < 0) in nvkm_sddr2_calc()
93 ram->mr[0] |= (CL & 0x07) << 4; in nvkm_sddr2_calc()
H A Dgddr5.c38 int WL, CL, WR, at[2], dt, ds; in nvkm_gddr5_calc() local
59 CL = (ram->next->bios.timing[1] & 0x0000001f); in nvkm_gddr5_calc()
70 if (WL < 1 || WL > 7 || CL < 5 || CL > 36 || WR < 4 || WR > 35) in nvkm_gddr5_calc()
72 CL -= 5; in nvkm_gddr5_calc()
77 ram->mr[0] |= (CL & 0x0f) << 3; in nvkm_gddr5_calc()
119 ram->mr[8] |= (CL & 0x10) >> 4; in nvkm_gddr5_calc()
H A Dramnv50.c88 T(CWL) = T(CL) - 1; in nv50_ram_timing_calc()
101 (0x2f + T(CL) - T(CWL)); in nv50_ram_timing_calc()
106 (0x2e + T(CL) - T(CWL)); in nv50_ram_timing_calc()
113 (3 + T(CL) - T(CWL)); in nv50_ram_timing_calc()
120 (T(CL) - 1) << 8 | in nv50_ram_timing_calc()
121 (T(CL) - 1); in nv50_ram_timing_calc()
134 timing[5] |= (T(CL) + 3) << 8; in nv50_ram_timing_calc()
135 timing[8] |= (T(CL) - 4); in nv50_ram_timing_calc()
138 timing[5] |= (T(CL) + 2) << 8; in nv50_ram_timing_calc()
139 timing[8] |= (T(CL) - 2); in nv50_ram_timing_calc()
[all …]
H A Dramgt215.c364 T(CWL) = T(CL) - 1; in gt215_ram_timing_calc()
378 (5 + T(CL) - T(CWL)); in gt215_ram_timing_calc()
384 (0x30 + T(CL)) << 24 | in gt215_ram_timing_calc()
385 (0xb + T(CL)) << 8 | in gt215_ram_timing_calc()
386 (T(CL) - 1); in gt215_ram_timing_calc()
393 max_t(u8, (T(CWL) + 6), (T(CL) + 2)) << 8 | in gt215_ram_timing_calc()
395 timing[6] = (0x5a + T(CL)) << 16 | in gt215_ram_timing_calc()
396 max_t(u8, 1, (6 - T(CL) + T(CWL))) << 8 | in gt215_ram_timing_calc()
397 (0x50 + T(CL) - T(CWL)); in gt215_ram_timing_calc()
399 ((tUNK_base + T(CL)) << 16) | in gt215_ram_timing_calc()
[all …]
/openbmc/openbmc/poky/scripts/
H A Dsend-pull-request105 CL="$PDIR/0000-cover-letter.patch"
107 grep -q "*** $TOKEN HERE ***" "$CL"
109 echo "ERROR: Please edit $CL and try again (Look for '*** $TOKEN HERE ***')."
157 …l "git send-email $GIT_TO $GIT_CC $GIT_EXTRA_CC --confirm=always --no-thread --suppress-cc=all $CL"
162 PATCHES=${PATCHES/"$CL"/}
H A Dcreate-pull-request205 CL="$(echo $ODIR/*0000-cover-letter.patch)"
222 sed -n "0,\#$REMOTE_URL# p" "$PM" | sed -i "/BLURB HERE/ r /dev/stdin" "$CL"
233 ) | sed -i "/BLURB HERE/ r /dev/stdin" "$CL"
238 echo " $WEB_URL" | sed -i "\#$REMOTE_URL# r /dev/stdin" "$CL"
245 sed -i "/BLURB HERE/ r $BODY" "$CL"
246 sed -i "/BLURB HERE/ d" "$CL"
257 sed -i -e "s\`\*\*\* SUBJECT HERE \*\*\*\`$SUBJECT\`" "$CL"
267 $CL
/openbmc/u-boot/arch/arm/mach-sunxi/
H A Ddram_sun9i.c89 u32 CL; member
360 u32 CL = 0; in mctl_channel_init() local
437 CL = para->cl_cwl_table[i].CL; in mctl_channel_init()
440 debug("found CL/CWL: CL = %d, CWL = %d\n", CL, CWL); in mctl_channel_init()
445 if ((CL == 0) && (CWL == 0)) { in mctl_channel_init()
461 DDR3_MR0_CL(CL); in mctl_channel_init()
525 #define RD2WR (CL + MCTL_BL/2 + 2 - CWL) in mctl_channel_init()
539 writel((MCTL_DIV2(CWL) << 24) | (MCTL_DIV2(CL) << 16) | in mctl_channel_init()
573 writel((2 << 24) | ((MCTL_DIV2(CL) - 2) << 16) | in mctl_channel_init()
860 { .CL = 5, .CWL = 5, .tCKmin = 3000, .tCKmax = 3300 }, in sunxi_dram_init()
[all …]
/openbmc/openbmc/meta-openembedded/meta-oe/recipes-core/opencl/
H A Dopencl-headers_2023.12.14.bb16 install -d ${D}${includedir}/CL/
17 install -m 0644 ${S}/CL/*.h ${D}${includedir}/CL
/openbmc/openbmc/poky/meta/recipes-multimedia/x264/x264/
H A Ddon-t-default-to-cortex-a9-with-neon.patch26 - [ $compiler == CL ] || echo $CFLAGS | grep -Eq '(-mcpu|-march|-mfpu)' || CFLAGS="$CFLAGS -mcpu…
29 if [ $compiler = CL ] && cpp_check '' '' 'defined(_M_ARM) && _M_ARM >= 7' ; then
/openbmc/u-boot/board/Seagate/nas220/
H A Dkwbimage.cfg26 #Dram initalization for SINGLE x16 CL=5 @ 400MHz
41 # bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
42 # bit27-24: 8= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
90 # bit6-4: 4, CL=5
/openbmc/u-boot/board/Marvell/dreamplug/
H A Dkwbimage.cfg22 #Dram initalization for SINGLE x16 CL=5 @ 400MHz
37 # bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
38 # bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
86 # bit6-4: 4, CL=5
/openbmc/u-boot/board/Marvell/sheevaplug/
H A Dkwbimage.cfg21 #Dram initalization for SINGLE x16 CL=5 @ 400MHz
36 # bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
37 # bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
85 # bit6-4: 4, CL=5
/openbmc/u-boot/board/Seagate/dockstar/
H A Dkwbimage.cfg24 #Dram initalization for SINGLE x16 CL=5 @ 400MHz
39 # bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
40 # bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
88 # bit6-4: 4, CL=5
/openbmc/u-boot/board/Marvell/guruplug/
H A Dkwbimage.cfg21 #Dram initalization for SINGLE x16 CL=5 @ 400MHz
36 # bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
37 # bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
85 # bit6-4: 4, CL=5
/openbmc/u-boot/board/Seagate/goflexhome/
H A Dkwbimage.cfg27 #Dram initalization for SINGLE x16 CL=5 @ 400MHz
42 # bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
43 # bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
91 # bit6-4: 4, CL=5
/openbmc/u-boot/board/Synology/ds109/
H A Dkwbimage.cfg25 #Dram initalization for SINGLE x16 CL=5 @ 400MHz
40 # bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
41 # bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
89 # bit6-4: 4, CL=5
/openbmc/u-boot/board/LaCie/netspace_v2/
H A Dkwbimage-ns2l.cfg22 #Dram initalization for SINGLE x16 CL=5 @ 400MHz
37 # bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
38 # bit27-24: 8= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
85 # bit6-4: 4, CL=5
H A Dkwbimage.cfg22 #Dram initalization for SINGLE x16 CL=5 @ 400MHz
37 # bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
38 # bit27-24: 8= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
85 # bit6-4: 4, CL=5
H A Dkwbimage-is2.cfg22 #Dram initalization for SINGLE x16 CL=5 @ 400MHz
37 # bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
38 # bit27-24: 8= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
85 # bit6-4: 4, CL=5
/openbmc/u-boot/board/LaCie/net2big_v2/
H A Dkwbimage.cfg22 #Dram initalization for SINGLE x16 CL=5 @ 400MHz
37 # bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
38 # bit27-24: 8= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
85 # bit6-4: 4, CL=5
/openbmc/u-boot/board/cloudengines/pogo_e02/
H A Dkwbimage.cfg25 #Dram initalization for SINGLE x16 CL=5 @ 400MHz
40 # bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
41 # bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
89 # bit6-4: 4, CL=5
/openbmc/u-boot/board/Marvell/openrd/
H A Dkwbimage.cfg21 #Dram initalization for SINGLE x16 CL=5 @ 400MHz
36 # bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
37 # bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
85 # bit6-4: 4, CL=5
/openbmc/u-boot/board/raidsonic/ib62x0/
H A Dkwbimage.cfg22 # Dram initalization for SINGLE x16 CL=5 @ 400MHz
37 # bit23-20: 0x5, recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
38 # bit27-24: 0x7, CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
86 # bit6-4: 0x4, CL=5

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