1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2013 Freescale Semiconductor, Inc.
4 */
5
6 #include <common.h>
7 #include <asm/io.h>
8 #include <asm/arch/imx-regs.h>
9 #include <asm/arch/iomux-vf610.h>
10 #include <asm/arch/ddrmc-vf610.h>
11 #include <asm/arch/crm_regs.h>
12 #include <asm/arch/clock.h>
13 #include <mmc.h>
14 #include <fsl_esdhc.h>
15 #include <miiphy.h>
16 #include <netdev.h>
17 #include <i2c.h>
18
19 DECLARE_GLOBAL_DATA_PTR;
20
21 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
22 PAD_CTL_DSE_25ohm | PAD_CTL_OBE_IBE_ENABLE)
23
24 #define ESDHC_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH | \
25 PAD_CTL_DSE_20ohm | PAD_CTL_OBE_IBE_ENABLE)
26
27 #define ENET_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \
28 PAD_CTL_DSE_50ohm | PAD_CTL_OBE_IBE_ENABLE)
29
30 static struct ddrmc_cr_setting vf610twr_cr_settings[] = {
31 /* levelling */
32 { DDRMC_CR97_WRLVL_EN, 97 },
33 { DDRMC_CR98_WRLVL_DL_0(0), 98 },
34 { DDRMC_CR99_WRLVL_DL_1(0), 99 },
35 { DDRMC_CR102_RDLVL_REG_EN | DDRMC_CR102_RDLVL_GT_REGEN, 102 },
36 { DDRMC_CR105_RDLVL_DL_0(0), 105 },
37 { DDRMC_CR106_RDLVL_GTDL_0(4), 106 },
38 { DDRMC_CR110_RDLVL_DL_1(0) | DDRMC_CR110_RDLVL_GTDL_1(4), 110 },
39 /* AXI */
40 { DDRMC_CR117_AXI0_W_PRI(0) | DDRMC_CR117_AXI0_R_PRI(0), 117 },
41 { DDRMC_CR118_AXI1_W_PRI(1) | DDRMC_CR118_AXI1_R_PRI(1), 118 },
42 { DDRMC_CR120_AXI0_PRI1_RPRI(2) |
43 DDRMC_CR120_AXI0_PRI0_RPRI(2), 120 },
44 { DDRMC_CR121_AXI0_PRI3_RPRI(2) |
45 DDRMC_CR121_AXI0_PRI2_RPRI(2), 121 },
46 { DDRMC_CR122_AXI1_PRI1_RPRI(1) | DDRMC_CR122_AXI1_PRI0_RPRI(1) |
47 DDRMC_CR122_AXI0_PRIRLX(100), 122 },
48 { DDRMC_CR123_AXI1_P_ODR_EN | DDRMC_CR123_AXI1_PRI3_RPRI(1) |
49 DDRMC_CR123_AXI1_PRI2_RPRI(1), 123 },
50 { DDRMC_CR124_AXI1_PRIRLX(100), 124 },
51 { DDRMC_CR126_PHY_RDLAT(8), 126 },
52 { DDRMC_CR132_WRLAT_ADJ(5) |
53 DDRMC_CR132_RDLAT_ADJ(6), 132 },
54 { DDRMC_CR137_PHYCTL_DL(2), 137 },
55 { DDRMC_CR138_PHY_WRLV_MXDL(256) |
56 DDRMC_CR138_PHYDRAM_CK_EN(1), 138 },
57 { DDRMC_CR139_PHY_WRLV_RESPLAT(4) | DDRMC_CR139_PHY_WRLV_LOAD(7) |
58 DDRMC_CR139_PHY_WRLV_DLL(3) |
59 DDRMC_CR139_PHY_WRLV_EN(3), 139 },
60 { DDRMC_CR140_PHY_WRLV_WW(64), 140 },
61 { DDRMC_CR143_RDLV_GAT_MXDL(1536) |
62 DDRMC_CR143_RDLV_MXDL(128), 143 },
63 { DDRMC_CR144_PHY_RDLVL_RES(4) | DDRMC_CR144_PHY_RDLV_LOAD(7) |
64 DDRMC_CR144_PHY_RDLV_DLL(3) |
65 DDRMC_CR144_PHY_RDLV_EN(3), 144 },
66 { DDRMC_CR145_PHY_RDLV_RR(64), 145 },
67 { DDRMC_CR146_PHY_RDLVL_RESP(64), 146 },
68 { DDRMC_CR147_RDLV_RESP_MASK(983040), 147 },
69 { DDRMC_CR148_RDLV_GATE_RESP_MASK(983040), 148 },
70 { DDRMC_CR151_RDLV_GAT_DQ_ZERO_CNT(1) |
71 DDRMC_CR151_RDLVL_DQ_ZERO_CNT(1), 151 },
72
73 { DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(13) |
74 DDRMC_CR154_PAD_ZQ_MODE(1) |
75 DDRMC_CR154_DDR_SEL_PAD_CONTR(3) |
76 DDRMC_CR154_PAD_ZQ_HW_FOR(1), 154 },
77 { DDRMC_CR155_PAD_ODT_BYTE1(1) | DDRMC_CR155_PAD_ODT_BYTE0(1), 155 },
78 { DDRMC_CR158_TWR(6), 158 },
79 { DDRMC_CR161_ODT_EN(1) | DDRMC_CR161_TODTH_RD(2) |
80 DDRMC_CR161_TODTH_WR(2), 161 },
81 /* end marker */
82 { 0, -1 }
83 };
84
dram_init(void)85 int dram_init(void)
86 {
87 static const struct ddr3_jedec_timings timings = {
88 .tinit = 5,
89 .trst_pwron = 80000,
90 .cke_inactive = 200000,
91 .wrlat = 5,
92 .caslat_lin = 12,
93 .trc = 21,
94 .trrd = 4,
95 .tccd = 4,
96 .tbst_int_interval = 0,
97 .tfaw = 20,
98 .trp = 6,
99 .twtr = 4,
100 .tras_min = 15,
101 .tmrd = 4,
102 .trtp = 4,
103 .tras_max = 28080,
104 .tmod = 12,
105 .tckesr = 4,
106 .tcke = 3,
107 .trcd_int = 6,
108 .tras_lockout = 0,
109 .tdal = 12,
110 .bstlen = 3,
111 .tdll = 512,
112 .trp_ab = 6,
113 .tref = 3120,
114 .trfc = 44,
115 .tref_int = 0,
116 .tpdex = 3,
117 .txpdll = 10,
118 .txsnr = 48,
119 .txsr = 468,
120 .cksrx = 5,
121 .cksre = 5,
122 .freq_chg_en = 0,
123 .zqcl = 256,
124 .zqinit = 512,
125 .zqcs = 64,
126 .ref_per_zq = 64,
127 .zqcs_rotate = 0,
128 .aprebit = 10,
129 .cmd_age_cnt = 64,
130 .age_cnt = 64,
131 .q_fullness = 7,
132 .odt_rd_mapcs0 = 0,
133 .odt_wr_mapcs0 = 1,
134 .wlmrd = 40,
135 .wldqsen = 25,
136 };
137
138 ddrmc_setup_iomux(NULL, 0);
139
140 ddrmc_ctrl_init_ddr3(&timings, vf610twr_cr_settings, NULL, 1, 3);
141 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
142
143 return 0;
144 }
145
setup_iomux_uart(void)146 static void setup_iomux_uart(void)
147 {
148 static const iomux_v3_cfg_t uart1_pads[] = {
149 NEW_PAD_CTRL(VF610_PAD_PTB4__UART1_TX, UART_PAD_CTRL),
150 NEW_PAD_CTRL(VF610_PAD_PTB5__UART1_RX, UART_PAD_CTRL),
151 };
152
153 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
154 }
155
setup_iomux_enet(void)156 static void setup_iomux_enet(void)
157 {
158 static const iomux_v3_cfg_t enet0_pads[] = {
159 NEW_PAD_CTRL(VF610_PAD_PTA6__RMII0_CLKIN, ENET_PAD_CTRL),
160 NEW_PAD_CTRL(VF610_PAD_PTC1__RMII0_MDIO, ENET_PAD_CTRL),
161 NEW_PAD_CTRL(VF610_PAD_PTC0__RMII0_MDC, ENET_PAD_CTRL),
162 NEW_PAD_CTRL(VF610_PAD_PTC2__RMII0_CRS_DV, ENET_PAD_CTRL),
163 NEW_PAD_CTRL(VF610_PAD_PTC3__RMII0_RD1, ENET_PAD_CTRL),
164 NEW_PAD_CTRL(VF610_PAD_PTC4__RMII0_RD0, ENET_PAD_CTRL),
165 NEW_PAD_CTRL(VF610_PAD_PTC5__RMII0_RXER, ENET_PAD_CTRL),
166 NEW_PAD_CTRL(VF610_PAD_PTC6__RMII0_TD1, ENET_PAD_CTRL),
167 NEW_PAD_CTRL(VF610_PAD_PTC7__RMII0_TD0, ENET_PAD_CTRL),
168 NEW_PAD_CTRL(VF610_PAD_PTC8__RMII0_TXEN, ENET_PAD_CTRL),
169 };
170
171 imx_iomux_v3_setup_multiple_pads(enet0_pads, ARRAY_SIZE(enet0_pads));
172 }
173
setup_iomux_i2c(void)174 static void setup_iomux_i2c(void)
175 {
176 static const iomux_v3_cfg_t i2c0_pads[] = {
177 VF610_PAD_PTB14__I2C0_SCL,
178 VF610_PAD_PTB15__I2C0_SDA,
179 };
180
181 imx_iomux_v3_setup_multiple_pads(i2c0_pads, ARRAY_SIZE(i2c0_pads));
182 }
183
184 #ifdef CONFIG_NAND_VF610_NFC
setup_iomux_nfc(void)185 static void setup_iomux_nfc(void)
186 {
187 static const iomux_v3_cfg_t nfc_pads[] = {
188 VF610_PAD_PTD31__NF_IO15,
189 VF610_PAD_PTD30__NF_IO14,
190 VF610_PAD_PTD29__NF_IO13,
191 VF610_PAD_PTD28__NF_IO12,
192 VF610_PAD_PTD27__NF_IO11,
193 VF610_PAD_PTD26__NF_IO10,
194 VF610_PAD_PTD25__NF_IO9,
195 VF610_PAD_PTD24__NF_IO8,
196 VF610_PAD_PTD23__NF_IO7,
197 VF610_PAD_PTD22__NF_IO6,
198 VF610_PAD_PTD21__NF_IO5,
199 VF610_PAD_PTD20__NF_IO4,
200 VF610_PAD_PTD19__NF_IO3,
201 VF610_PAD_PTD18__NF_IO2,
202 VF610_PAD_PTD17__NF_IO1,
203 VF610_PAD_PTD16__NF_IO0,
204 VF610_PAD_PTB24__NF_WE_B,
205 VF610_PAD_PTB25__NF_CE0_B,
206 VF610_PAD_PTB27__NF_RE_B,
207 VF610_PAD_PTC26__NF_RB_B,
208 VF610_PAD_PTC27__NF_ALE,
209 VF610_PAD_PTC28__NF_CLE
210 };
211
212 imx_iomux_v3_setup_multiple_pads(nfc_pads, ARRAY_SIZE(nfc_pads));
213 }
214 #endif
215
216
setup_iomux_qspi(void)217 static void setup_iomux_qspi(void)
218 {
219 static const iomux_v3_cfg_t qspi0_pads[] = {
220 VF610_PAD_PTD0__QSPI0_A_QSCK,
221 VF610_PAD_PTD1__QSPI0_A_CS0,
222 VF610_PAD_PTD2__QSPI0_A_DATA3,
223 VF610_PAD_PTD3__QSPI0_A_DATA2,
224 VF610_PAD_PTD4__QSPI0_A_DATA1,
225 VF610_PAD_PTD5__QSPI0_A_DATA0,
226 VF610_PAD_PTD7__QSPI0_B_QSCK,
227 VF610_PAD_PTD8__QSPI0_B_CS0,
228 VF610_PAD_PTD9__QSPI0_B_DATA3,
229 VF610_PAD_PTD10__QSPI0_B_DATA2,
230 VF610_PAD_PTD11__QSPI0_B_DATA1,
231 VF610_PAD_PTD12__QSPI0_B_DATA0,
232 };
233
234 imx_iomux_v3_setup_multiple_pads(qspi0_pads, ARRAY_SIZE(qspi0_pads));
235 }
236
237 #ifdef CONFIG_FSL_ESDHC
238 struct fsl_esdhc_cfg esdhc_cfg[1] = {
239 {ESDHC1_BASE_ADDR},
240 };
241
board_mmc_getcd(struct mmc * mmc)242 int board_mmc_getcd(struct mmc *mmc)
243 {
244 /* eSDHC1 is always present */
245 return 1;
246 }
247
board_mmc_init(bd_t * bis)248 int board_mmc_init(bd_t *bis)
249 {
250 static const iomux_v3_cfg_t esdhc1_pads[] = {
251 NEW_PAD_CTRL(VF610_PAD_PTA24__ESDHC1_CLK, ESDHC_PAD_CTRL),
252 NEW_PAD_CTRL(VF610_PAD_PTA25__ESDHC1_CMD, ESDHC_PAD_CTRL),
253 NEW_PAD_CTRL(VF610_PAD_PTA26__ESDHC1_DAT0, ESDHC_PAD_CTRL),
254 NEW_PAD_CTRL(VF610_PAD_PTA27__ESDHC1_DAT1, ESDHC_PAD_CTRL),
255 NEW_PAD_CTRL(VF610_PAD_PTA28__ESDHC1_DAT2, ESDHC_PAD_CTRL),
256 NEW_PAD_CTRL(VF610_PAD_PTA29__ESDHC1_DAT3, ESDHC_PAD_CTRL),
257 };
258
259 esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
260
261 imx_iomux_v3_setup_multiple_pads(
262 esdhc1_pads, ARRAY_SIZE(esdhc1_pads));
263
264 return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
265 }
266 #endif
267
clock_init(void)268 static void clock_init(void)
269 {
270 struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
271 struct anadig_reg *anadig = (struct anadig_reg *)ANADIG_BASE_ADDR;
272
273 clrsetbits_le32(&ccm->ccgr0, CCM_REG_CTRL_MASK,
274 CCM_CCGR0_UART1_CTRL_MASK);
275 clrsetbits_le32(&ccm->ccgr1, CCM_REG_CTRL_MASK,
276 CCM_CCGR1_PIT_CTRL_MASK | CCM_CCGR1_WDOGA5_CTRL_MASK);
277 clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK,
278 CCM_CCGR2_IOMUXC_CTRL_MASK | CCM_CCGR2_PORTA_CTRL_MASK |
279 CCM_CCGR2_PORTB_CTRL_MASK | CCM_CCGR2_PORTC_CTRL_MASK |
280 CCM_CCGR2_PORTD_CTRL_MASK | CCM_CCGR2_PORTE_CTRL_MASK |
281 CCM_CCGR2_QSPI0_CTRL_MASK);
282 clrsetbits_le32(&ccm->ccgr3, CCM_REG_CTRL_MASK,
283 CCM_CCGR3_ANADIG_CTRL_MASK | CCM_CCGR3_SCSC_CTRL_MASK);
284 clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK,
285 CCM_CCGR4_WKUP_CTRL_MASK | CCM_CCGR4_CCM_CTRL_MASK |
286 CCM_CCGR4_GPC_CTRL_MASK | CCM_CCGR4_I2C0_CTRL_MASK);
287 clrsetbits_le32(&ccm->ccgr6, CCM_REG_CTRL_MASK,
288 CCM_CCGR6_OCOTP_CTRL_MASK | CCM_CCGR6_DDRMC_CTRL_MASK);
289 clrsetbits_le32(&ccm->ccgr7, CCM_REG_CTRL_MASK,
290 CCM_CCGR7_SDHC1_CTRL_MASK);
291 clrsetbits_le32(&ccm->ccgr9, CCM_REG_CTRL_MASK,
292 CCM_CCGR9_FEC0_CTRL_MASK | CCM_CCGR9_FEC1_CTRL_MASK);
293 clrsetbits_le32(&ccm->ccgr10, CCM_REG_CTRL_MASK,
294 CCM_CCGR10_NFC_CTRL_MASK);
295
296 clrsetbits_le32(&anadig->pll2_ctrl, ANADIG_PLL2_CTRL_POWERDOWN,
297 ANADIG_PLL2_CTRL_ENABLE | ANADIG_PLL2_CTRL_DIV_SELECT);
298 clrsetbits_le32(&anadig->pll1_ctrl, ANADIG_PLL1_CTRL_POWERDOWN,
299 ANADIG_PLL1_CTRL_ENABLE | ANADIG_PLL1_CTRL_DIV_SELECT);
300
301 clrsetbits_le32(&ccm->ccr, CCM_CCR_OSCNT_MASK,
302 CCM_CCR_FIRC_EN | CCM_CCR_OSCNT(5));
303 clrsetbits_le32(&ccm->ccsr, CCM_REG_CTRL_MASK,
304 CCM_CCSR_PLL1_PFD_CLK_SEL(3) | CCM_CCSR_PLL2_PFD4_EN |
305 CCM_CCSR_PLL2_PFD3_EN | CCM_CCSR_PLL2_PFD2_EN |
306 CCM_CCSR_PLL2_PFD1_EN | CCM_CCSR_PLL1_PFD4_EN |
307 CCM_CCSR_PLL1_PFD3_EN | CCM_CCSR_PLL1_PFD2_EN |
308 CCM_CCSR_PLL1_PFD1_EN | CCM_CCSR_DDRC_CLK_SEL(1) |
309 CCM_CCSR_FAST_CLK_SEL(1) | CCM_CCSR_SYS_CLK_SEL(4));
310 clrsetbits_le32(&ccm->cacrr, CCM_REG_CTRL_MASK,
311 CCM_CACRR_IPG_CLK_DIV(1) | CCM_CACRR_BUS_CLK_DIV(2) |
312 CCM_CACRR_ARM_CLK_DIV(0));
313 clrsetbits_le32(&ccm->cscmr1, CCM_REG_CTRL_MASK,
314 CCM_CSCMR1_ESDHC1_CLK_SEL(3) | CCM_CSCMR1_QSPI0_CLK_SEL(3) |
315 CCM_CSCMR1_NFC_CLK_SEL(0));
316 clrsetbits_le32(&ccm->cscdr1, CCM_REG_CTRL_MASK,
317 CCM_CSCDR1_RMII_CLK_EN);
318 clrsetbits_le32(&ccm->cscdr2, CCM_REG_CTRL_MASK,
319 CCM_CSCDR2_ESDHC1_EN | CCM_CSCDR2_ESDHC1_CLK_DIV(0) |
320 CCM_CSCDR2_NFC_EN);
321 clrsetbits_le32(&ccm->cscdr3, CCM_REG_CTRL_MASK,
322 CCM_CSCDR3_QSPI0_EN | CCM_CSCDR3_QSPI0_DIV(1) |
323 CCM_CSCDR3_QSPI0_X2_DIV(1) | CCM_CSCDR3_QSPI0_X4_DIV(3) |
324 CCM_CSCDR3_NFC_PRE_DIV(5));
325 clrsetbits_le32(&ccm->cscmr2, CCM_REG_CTRL_MASK,
326 CCM_CSCMR2_RMII_CLK_SEL(0));
327 }
328
mscm_init(void)329 static void mscm_init(void)
330 {
331 struct mscm_ir *mscmir = (struct mscm_ir *)MSCM_IR_BASE_ADDR;
332 int i;
333
334 for (i = 0; i < MSCM_IRSPRC_NUM; i++)
335 writew(MSCM_IRSPRC_CP0_EN, &mscmir->irsprc[i]);
336 }
337
board_phy_config(struct phy_device * phydev)338 int board_phy_config(struct phy_device *phydev)
339 {
340 if (phydev->drv->config)
341 phydev->drv->config(phydev);
342
343 return 0;
344 }
345
board_early_init_f(void)346 int board_early_init_f(void)
347 {
348 clock_init();
349 mscm_init();
350
351 setup_iomux_uart();
352 setup_iomux_enet();
353 setup_iomux_i2c();
354 setup_iomux_qspi();
355 #ifdef CONFIG_NAND_VF610_NFC
356 setup_iomux_nfc();
357 #endif
358
359 return 0;
360 }
361
board_init(void)362 int board_init(void)
363 {
364 struct scsc_reg *scsc = (struct scsc_reg *)SCSC_BASE_ADDR;
365
366 /* address of boot parameters */
367 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
368
369 /*
370 * Enable external 32K Oscillator
371 *
372 * The internal clock experiences significant drift
373 * so we must use the external oscillator in order
374 * to maintain correct time in the hwclock
375 */
376 setbits_le32(&scsc->sosc_ctr, SCSC_SOSC_CTR_SOSC_EN);
377
378 return 0;
379 }
380
checkboard(void)381 int checkboard(void)
382 {
383 puts("Board: vf610twr\n");
384
385 return 0;
386 }
387