1 /* 2 * Copyright (C) 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20 */ 21 #ifndef _vcn_2_0_0_SH_MASK_HEADER 22 #define _vcn_2_0_0_SH_MASK_HEADER 23 24 25 // addressBlock: uvd0_mmsch_dec 26 //MMSCH_UCODE_ADDR 27 #define MMSCH_UCODE_ADDR__UCODE_ADDR__SHIFT 0x2 28 #define MMSCH_UCODE_ADDR__UCODE_LOCK__SHIFT 0x1f 29 #define MMSCH_UCODE_ADDR__UCODE_ADDR_MASK 0x00003FFCL 30 #define MMSCH_UCODE_ADDR__UCODE_LOCK_MASK 0x80000000L 31 //MMSCH_UCODE_DATA 32 #define MMSCH_UCODE_DATA__UCODE_DATA__SHIFT 0x0 33 #define MMSCH_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL 34 //MMSCH_SRAM_ADDR 35 #define MMSCH_SRAM_ADDR__SRAM_ADDR__SHIFT 0x2 36 #define MMSCH_SRAM_ADDR__SRAM_LOCK__SHIFT 0x1f 37 #define MMSCH_SRAM_ADDR__SRAM_ADDR_MASK 0x00001FFCL 38 #define MMSCH_SRAM_ADDR__SRAM_LOCK_MASK 0x80000000L 39 //MMSCH_SRAM_DATA 40 #define MMSCH_SRAM_DATA__SRAM_DATA__SHIFT 0x0 41 #define MMSCH_SRAM_DATA__SRAM_DATA_MASK 0xFFFFFFFFL 42 //MMSCH_VF_SRAM_OFFSET 43 #define MMSCH_VF_SRAM_OFFSET__VF_SRAM_OFFSET__SHIFT 0x2 44 #define MMSCH_VF_SRAM_OFFSET__VF_SRAM_NUM_DW_PER_VF__SHIFT 0x10 45 #define MMSCH_VF_SRAM_OFFSET__VF_SRAM_OFFSET_MASK 0x00001FFCL 46 #define MMSCH_VF_SRAM_OFFSET__VF_SRAM_NUM_DW_PER_VF_MASK 0x00FF0000L 47 //MMSCH_DB_SRAM_OFFSET 48 #define MMSCH_DB_SRAM_OFFSET__DB_SRAM_OFFSET__SHIFT 0x2 49 #define MMSCH_DB_SRAM_OFFSET__DB_SRAM_NUM_ENG__SHIFT 0x10 50 #define MMSCH_DB_SRAM_OFFSET__DB_SRAM_NUM_RING_PER_ENG__SHIFT 0x18 51 #define MMSCH_DB_SRAM_OFFSET__DB_SRAM_OFFSET_MASK 0x00001FFCL 52 #define MMSCH_DB_SRAM_OFFSET__DB_SRAM_NUM_ENG_MASK 0x00FF0000L 53 #define MMSCH_DB_SRAM_OFFSET__DB_SRAM_NUM_RING_PER_ENG_MASK 0xFF000000L 54 //MMSCH_CTX_SRAM_OFFSET 55 #define MMSCH_CTX_SRAM_OFFSET__CTX_SRAM_OFFSET__SHIFT 0x2 56 #define MMSCH_CTX_SRAM_OFFSET__CTX_SRAM_SIZE__SHIFT 0x10 57 #define MMSCH_CTX_SRAM_OFFSET__CTX_SRAM_OFFSET_MASK 0x00001FFCL 58 #define MMSCH_CTX_SRAM_OFFSET__CTX_SRAM_SIZE_MASK 0xFFFF0000L 59 //MMSCH_CTL 60 #define MMSCH_CTL__P_RUNSTALL__SHIFT 0x0 61 #define MMSCH_CTL__P_RESET__SHIFT 0x1 62 #define MMSCH_CTL__VFID_FIFO_EN__SHIFT 0x4 63 #define MMSCH_CTL__P_LOCK__SHIFT 0x1f 64 #define MMSCH_CTL__P_RUNSTALL_MASK 0x00000001L 65 #define MMSCH_CTL__P_RESET_MASK 0x00000002L 66 #define MMSCH_CTL__VFID_FIFO_EN_MASK 0x00000010L 67 #define MMSCH_CTL__P_LOCK_MASK 0x80000000L 68 //MMSCH_INTR 69 #define MMSCH_INTR__INTR__SHIFT 0x0 70 #define MMSCH_INTR__INTR_MASK 0x00001FFFL 71 //MMSCH_INTR_ACK 72 #define MMSCH_INTR_ACK__INTR__SHIFT 0x0 73 #define MMSCH_INTR_ACK__INTR_MASK 0x00001FFFL 74 //MMSCH_INTR_STATUS 75 #define MMSCH_INTR_STATUS__INTR__SHIFT 0x0 76 #define MMSCH_INTR_STATUS__INTR_MASK 0x00001FFFL 77 //MMSCH_VF_VMID 78 #define MMSCH_VF_VMID__VF_CTX_VMID__SHIFT 0x0 79 #define MMSCH_VF_VMID__VF_GPCOM_VMID__SHIFT 0x5 80 #define MMSCH_VF_VMID__VF_CTX_VMID_MASK 0x0000001FL 81 #define MMSCH_VF_VMID__VF_GPCOM_VMID_MASK 0x000003E0L 82 //MMSCH_VF_CTX_ADDR_LO 83 #define MMSCH_VF_CTX_ADDR_LO__VF_CTX_ADDR_LO__SHIFT 0x6 84 #define MMSCH_VF_CTX_ADDR_LO__VF_CTX_ADDR_LO_MASK 0xFFFFFFC0L 85 //MMSCH_VF_CTX_ADDR_HI 86 #define MMSCH_VF_CTX_ADDR_HI__VF_CTX_ADDR_HI__SHIFT 0x0 87 #define MMSCH_VF_CTX_ADDR_HI__VF_CTX_ADDR_HI_MASK 0xFFFFFFFFL 88 //MMSCH_VF_CTX_SIZE 89 #define MMSCH_VF_CTX_SIZE__VF_CTX_SIZE__SHIFT 0x0 90 #define MMSCH_VF_CTX_SIZE__VF_CTX_SIZE_MASK 0xFFFFFFFFL 91 //MMSCH_VF_GPCOM_ADDR_LO 92 #define MMSCH_VF_GPCOM_ADDR_LO__VF_GPCOM_ADDR_LO__SHIFT 0x6 93 #define MMSCH_VF_GPCOM_ADDR_LO__VF_GPCOM_ADDR_LO_MASK 0xFFFFFFC0L 94 //MMSCH_VF_GPCOM_ADDR_HI 95 #define MMSCH_VF_GPCOM_ADDR_HI__VF_GPCOM_ADDR_HI__SHIFT 0x0 96 #define MMSCH_VF_GPCOM_ADDR_HI__VF_GPCOM_ADDR_HI_MASK 0xFFFFFFFFL 97 //MMSCH_VF_GPCOM_SIZE 98 #define MMSCH_VF_GPCOM_SIZE__VF_GPCOM_SIZE__SHIFT 0x0 99 #define MMSCH_VF_GPCOM_SIZE__VF_GPCOM_SIZE_MASK 0xFFFFFFFFL 100 //MMSCH_VF_MAILBOX_HOST 101 #define MMSCH_VF_MAILBOX_HOST__DATA__SHIFT 0x0 102 #define MMSCH_VF_MAILBOX_HOST__DATA_MASK 0xFFFFFFFFL 103 //MMSCH_VF_MAILBOX_RESP 104 #define MMSCH_VF_MAILBOX_RESP__RESP__SHIFT 0x0 105 #define MMSCH_VF_MAILBOX_RESP__RESP_MASK 0xFFFFFFFFL 106 //MMSCH_VF_MAILBOX_0 107 #define MMSCH_VF_MAILBOX_0__DATA__SHIFT 0x0 108 #define MMSCH_VF_MAILBOX_0__DATA_MASK 0xFFFFFFFFL 109 //MMSCH_VF_MAILBOX_0_RESP 110 #define MMSCH_VF_MAILBOX_0_RESP__RESP__SHIFT 0x0 111 #define MMSCH_VF_MAILBOX_0_RESP__RESP_MASK 0xFFFFFFFFL 112 //MMSCH_VF_MAILBOX_1 113 #define MMSCH_VF_MAILBOX_1__DATA__SHIFT 0x0 114 #define MMSCH_VF_MAILBOX_1__DATA_MASK 0xFFFFFFFFL 115 //MMSCH_VF_MAILBOX_1_RESP 116 #define MMSCH_VF_MAILBOX_1_RESP__RESP__SHIFT 0x0 117 #define MMSCH_VF_MAILBOX_1_RESP__RESP_MASK 0xFFFFFFFFL 118 //MMSCH_CNTL 119 #define MMSCH_CNTL__CLK_EN__SHIFT 0x0 120 #define MMSCH_CNTL__ED_ENABLE__SHIFT 0x1 121 #define MMSCH_CNTL__MMSCH_IRQ_ERR__SHIFT 0x5 122 #define MMSCH_CNTL__MMSCH_NACK_INTR_EN__SHIFT 0x9 123 #define MMSCH_CNTL__MMSCH_DB_BUSY_INTR_EN__SHIFT 0xa 124 #define MMSCH_CNTL__PRB_TIMEOUT_VAL__SHIFT 0x14 125 #define MMSCH_CNTL__TIMEOUT_DIS__SHIFT 0x1c 126 #define MMSCH_CNTL__CLK_EN_MASK 0x00000001L 127 #define MMSCH_CNTL__ED_ENABLE_MASK 0x00000002L 128 #define MMSCH_CNTL__MMSCH_IRQ_ERR_MASK 0x000001E0L 129 #define MMSCH_CNTL__MMSCH_NACK_INTR_EN_MASK 0x00000200L 130 #define MMSCH_CNTL__MMSCH_DB_BUSY_INTR_EN_MASK 0x00000400L 131 #define MMSCH_CNTL__PRB_TIMEOUT_VAL_MASK 0x0FF00000L 132 #define MMSCH_CNTL__TIMEOUT_DIS_MASK 0x10000000L 133 //MMSCH_NONCACHE_OFFSET0 134 #define MMSCH_NONCACHE_OFFSET0__OFFSET__SHIFT 0x0 135 #define MMSCH_NONCACHE_OFFSET0__OFFSET_MASK 0x0FFFFFFFL 136 //MMSCH_NONCACHE_SIZE0 137 #define MMSCH_NONCACHE_SIZE0__SIZE__SHIFT 0x0 138 #define MMSCH_NONCACHE_SIZE0__SIZE_MASK 0x00FFFFFFL 139 //MMSCH_NONCACHE_OFFSET1 140 #define MMSCH_NONCACHE_OFFSET1__OFFSET__SHIFT 0x0 141 #define MMSCH_NONCACHE_OFFSET1__OFFSET_MASK 0x0FFFFFFFL 142 //MMSCH_NONCACHE_SIZE1 143 #define MMSCH_NONCACHE_SIZE1__SIZE__SHIFT 0x0 144 #define MMSCH_NONCACHE_SIZE1__SIZE_MASK 0x00FFFFFFL 145 //MMSCH_PROC_STATE1 146 #define MMSCH_PROC_STATE1__PC__SHIFT 0x0 147 #define MMSCH_PROC_STATE1__PC_MASK 0xFFFFFFFFL 148 //MMSCH_LAST_MC_ADDR 149 #define MMSCH_LAST_MC_ADDR__MC_ADDR__SHIFT 0x0 150 #define MMSCH_LAST_MC_ADDR__RW__SHIFT 0x1f 151 #define MMSCH_LAST_MC_ADDR__MC_ADDR_MASK 0x0FFFFFFFL 152 #define MMSCH_LAST_MC_ADDR__RW_MASK 0x80000000L 153 //MMSCH_LAST_MEM_ACCESS_HI 154 #define MMSCH_LAST_MEM_ACCESS_HI__PROC_CMD__SHIFT 0x0 155 #define MMSCH_LAST_MEM_ACCESS_HI__FIFO_RPTR__SHIFT 0x8 156 #define MMSCH_LAST_MEM_ACCESS_HI__FIFO_WPTR__SHIFT 0xc 157 #define MMSCH_LAST_MEM_ACCESS_HI__PROC_CMD_MASK 0x00000007L 158 #define MMSCH_LAST_MEM_ACCESS_HI__FIFO_RPTR_MASK 0x00000700L 159 #define MMSCH_LAST_MEM_ACCESS_HI__FIFO_WPTR_MASK 0x00007000L 160 //MMSCH_LAST_MEM_ACCESS_LO 161 #define MMSCH_LAST_MEM_ACCESS_LO__PROC_ADDR__SHIFT 0x0 162 #define MMSCH_LAST_MEM_ACCESS_LO__PROC_ADDR_MASK 0xFFFFFFFFL 163 //MMSCH_IOV_ACTIVE_FCN_ID 164 #define MMSCH_IOV_ACTIVE_FCN_ID__ACTIVE_VF_ID__SHIFT 0x0 165 #define MMSCH_IOV_ACTIVE_FCN_ID__ACTIVE_PF_VF__SHIFT 0x1f 166 #define MMSCH_IOV_ACTIVE_FCN_ID__ACTIVE_VF_ID_MASK 0x0000001FL 167 #define MMSCH_IOV_ACTIVE_FCN_ID__ACTIVE_PF_VF_MASK 0x80000000L 168 //MMSCH_SCRATCH_0 169 #define MMSCH_SCRATCH_0__SCRATCH_0__SHIFT 0x0 170 #define MMSCH_SCRATCH_0__SCRATCH_0_MASK 0xFFFFFFFFL 171 //MMSCH_SCRATCH_1 172 #define MMSCH_SCRATCH_1__SCRATCH_1__SHIFT 0x0 173 #define MMSCH_SCRATCH_1__SCRATCH_1_MASK 0xFFFFFFFFL 174 //MMSCH_GPUIOV_SCH_BLOCK_0 175 #define MMSCH_GPUIOV_SCH_BLOCK_0__ID__SHIFT 0x0 176 #define MMSCH_GPUIOV_SCH_BLOCK_0__VERSION__SHIFT 0x4 177 #define MMSCH_GPUIOV_SCH_BLOCK_0__SIZE__SHIFT 0x8 178 #define MMSCH_GPUIOV_SCH_BLOCK_0__ID_MASK 0x0000000FL 179 #define MMSCH_GPUIOV_SCH_BLOCK_0__VERSION_MASK 0x000000F0L 180 #define MMSCH_GPUIOV_SCH_BLOCK_0__SIZE_MASK 0x0000FF00L 181 //MMSCH_GPUIOV_CMD_CONTROL_0 182 #define MMSCH_GPUIOV_CMD_CONTROL_0__CMD_TYPE__SHIFT 0x0 183 #define MMSCH_GPUIOV_CMD_CONTROL_0__CMD_EXECUTE__SHIFT 0x4 184 #define MMSCH_GPUIOV_CMD_CONTROL_0__CMD_EXECUTE_INTR_EN__SHIFT 0x5 185 #define MMSCH_GPUIOV_CMD_CONTROL_0__VM_BUSY_INTR_EN__SHIFT 0x6 186 #define MMSCH_GPUIOV_CMD_CONTROL_0__FUNCTINO_ID__SHIFT 0x8 187 #define MMSCH_GPUIOV_CMD_CONTROL_0__NEXT_FUNCTINO_ID__SHIFT 0x10 188 #define MMSCH_GPUIOV_CMD_CONTROL_0__CMD_TYPE_MASK 0x0000000FL 189 #define MMSCH_GPUIOV_CMD_CONTROL_0__CMD_EXECUTE_MASK 0x00000010L 190 #define MMSCH_GPUIOV_CMD_CONTROL_0__CMD_EXECUTE_INTR_EN_MASK 0x00000020L 191 #define MMSCH_GPUIOV_CMD_CONTROL_0__VM_BUSY_INTR_EN_MASK 0x00000040L 192 #define MMSCH_GPUIOV_CMD_CONTROL_0__FUNCTINO_ID_MASK 0x0000FF00L 193 #define MMSCH_GPUIOV_CMD_CONTROL_0__NEXT_FUNCTINO_ID_MASK 0x00FF0000L 194 //MMSCH_GPUIOV_CMD_STATUS_0 195 #define MMSCH_GPUIOV_CMD_STATUS_0__CMD_STATUS__SHIFT 0x0 196 #define MMSCH_GPUIOV_CMD_STATUS_0__CMD_STATUS_MASK 0x0000000FL 197 //MMSCH_GPUIOV_VM_BUSY_STATUS_0 198 #define MMSCH_GPUIOV_VM_BUSY_STATUS_0__BUSY__SHIFT 0x0 199 #define MMSCH_GPUIOV_VM_BUSY_STATUS_0__BUSY_MASK 0xFFFFFFFFL 200 //MMSCH_GPUIOV_ACTIVE_FCNS_0 201 #define MMSCH_GPUIOV_ACTIVE_FCNS_0__ACTIVE_FCNS__SHIFT 0x0 202 #define MMSCH_GPUIOV_ACTIVE_FCNS_0__ACTIVE_FCNS_MASK 0xFFFFFFFFL 203 //MMSCH_GPUIOV_ACTIVE_FCN_ID_0 204 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_0__ID__SHIFT 0x0 205 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_0__ID_STATUS__SHIFT 0x8 206 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_0__ID_MASK 0x000000FFL 207 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_0__ID_STATUS_MASK 0x00000F00L 208 //MMSCH_GPUIOV_DW6_0 209 #define MMSCH_GPUIOV_DW6_0__DATA__SHIFT 0x0 210 #define MMSCH_GPUIOV_DW6_0__DATA_MASK 0xFFFFFFFFL 211 //MMSCH_GPUIOV_DW7_0 212 #define MMSCH_GPUIOV_DW7_0__DATA__SHIFT 0x0 213 #define MMSCH_GPUIOV_DW7_0__DATA_MASK 0xFFFFFFFFL 214 //MMSCH_GPUIOV_DW8_0 215 #define MMSCH_GPUIOV_DW8_0__DATA__SHIFT 0x0 216 #define MMSCH_GPUIOV_DW8_0__DATA_MASK 0xFFFFFFFFL 217 //MMSCH_GPUIOV_SCH_BLOCK_1 218 #define MMSCH_GPUIOV_SCH_BLOCK_1__ID__SHIFT 0x0 219 #define MMSCH_GPUIOV_SCH_BLOCK_1__VERSION__SHIFT 0x4 220 #define MMSCH_GPUIOV_SCH_BLOCK_1__SIZE__SHIFT 0x8 221 #define MMSCH_GPUIOV_SCH_BLOCK_1__ID_MASK 0x0000000FL 222 #define MMSCH_GPUIOV_SCH_BLOCK_1__VERSION_MASK 0x000000F0L 223 #define MMSCH_GPUIOV_SCH_BLOCK_1__SIZE_MASK 0x0000FF00L 224 //MMSCH_GPUIOV_CMD_CONTROL_1 225 #define MMSCH_GPUIOV_CMD_CONTROL_1__CMD_TYPE__SHIFT 0x0 226 #define MMSCH_GPUIOV_CMD_CONTROL_1__CMD_EXECUTE__SHIFT 0x4 227 #define MMSCH_GPUIOV_CMD_CONTROL_1__CMD_EXECUTE_INTR_EN__SHIFT 0x5 228 #define MMSCH_GPUIOV_CMD_CONTROL_1__VM_BUSY_INTR_EN__SHIFT 0x6 229 #define MMSCH_GPUIOV_CMD_CONTROL_1__FUNCTINO_ID__SHIFT 0x8 230 #define MMSCH_GPUIOV_CMD_CONTROL_1__NEXT_FUNCTINO_ID__SHIFT 0x10 231 #define MMSCH_GPUIOV_CMD_CONTROL_1__CMD_TYPE_MASK 0x0000000FL 232 #define MMSCH_GPUIOV_CMD_CONTROL_1__CMD_EXECUTE_MASK 0x00000010L 233 #define MMSCH_GPUIOV_CMD_CONTROL_1__CMD_EXECUTE_INTR_EN_MASK 0x00000020L 234 #define MMSCH_GPUIOV_CMD_CONTROL_1__VM_BUSY_INTR_EN_MASK 0x00000040L 235 #define MMSCH_GPUIOV_CMD_CONTROL_1__FUNCTINO_ID_MASK 0x0000FF00L 236 #define MMSCH_GPUIOV_CMD_CONTROL_1__NEXT_FUNCTINO_ID_MASK 0x00FF0000L 237 //MMSCH_GPUIOV_CMD_STATUS_1 238 #define MMSCH_GPUIOV_CMD_STATUS_1__CMD_STATUS__SHIFT 0x0 239 #define MMSCH_GPUIOV_CMD_STATUS_1__CMD_STATUS_MASK 0x0000000FL 240 //MMSCH_GPUIOV_VM_BUSY_STATUS_1 241 #define MMSCH_GPUIOV_VM_BUSY_STATUS_1__BUSY__SHIFT 0x0 242 #define MMSCH_GPUIOV_VM_BUSY_STATUS_1__BUSY_MASK 0xFFFFFFFFL 243 //MMSCH_GPUIOV_ACTIVE_FCNS_1 244 #define MMSCH_GPUIOV_ACTIVE_FCNS_1__ACTIVE_FCNS__SHIFT 0x0 245 #define MMSCH_GPUIOV_ACTIVE_FCNS_1__ACTIVE_FCNS_MASK 0xFFFFFFFFL 246 //MMSCH_GPUIOV_ACTIVE_FCN_ID_1 247 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_1__ID__SHIFT 0x0 248 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_1__ID_STATUS__SHIFT 0x8 249 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_1__ID_MASK 0x000000FFL 250 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_1__ID_STATUS_MASK 0x00000F00L 251 //MMSCH_GPUIOV_DW6_1 252 #define MMSCH_GPUIOV_DW6_1__DATA__SHIFT 0x0 253 #define MMSCH_GPUIOV_DW6_1__DATA_MASK 0xFFFFFFFFL 254 //MMSCH_GPUIOV_DW7_1 255 #define MMSCH_GPUIOV_DW7_1__DATA__SHIFT 0x0 256 #define MMSCH_GPUIOV_DW7_1__DATA_MASK 0xFFFFFFFFL 257 //MMSCH_GPUIOV_DW8_1 258 #define MMSCH_GPUIOV_DW8_1__DATA__SHIFT 0x0 259 #define MMSCH_GPUIOV_DW8_1__DATA_MASK 0xFFFFFFFFL 260 //MMSCH_GPUIOV_CNTXT 261 #define MMSCH_GPUIOV_CNTXT__CNTXT_SIZE__SHIFT 0x0 262 #define MMSCH_GPUIOV_CNTXT__CNTXT_LOCATION__SHIFT 0x7 263 #define MMSCH_GPUIOV_CNTXT__CNTXT_OFFSET__SHIFT 0xa 264 #define MMSCH_GPUIOV_CNTXT__CNTXT_SIZE_MASK 0x0000007FL 265 #define MMSCH_GPUIOV_CNTXT__CNTXT_LOCATION_MASK 0x00000080L 266 #define MMSCH_GPUIOV_CNTXT__CNTXT_OFFSET_MASK 0xFFFFFC00L 267 //MMSCH_SCRATCH_2 268 #define MMSCH_SCRATCH_2__SCRATCH_2__SHIFT 0x0 269 #define MMSCH_SCRATCH_2__SCRATCH_2_MASK 0xFFFFFFFFL 270 //MMSCH_SCRATCH_3 271 #define MMSCH_SCRATCH_3__SCRATCH_3__SHIFT 0x0 272 #define MMSCH_SCRATCH_3__SCRATCH_3_MASK 0xFFFFFFFFL 273 //MMSCH_SCRATCH_4 274 #define MMSCH_SCRATCH_4__SCRATCH_4__SHIFT 0x0 275 #define MMSCH_SCRATCH_4__SCRATCH_4_MASK 0xFFFFFFFFL 276 //MMSCH_SCRATCH_5 277 #define MMSCH_SCRATCH_5__SCRATCH_5__SHIFT 0x0 278 #define MMSCH_SCRATCH_5__SCRATCH_5_MASK 0xFFFFFFFFL 279 //MMSCH_SCRATCH_6 280 #define MMSCH_SCRATCH_6__SCRATCH_6__SHIFT 0x0 281 #define MMSCH_SCRATCH_6__SCRATCH_6_MASK 0xFFFFFFFFL 282 //MMSCH_SCRATCH_7 283 #define MMSCH_SCRATCH_7__SCRATCH_7__SHIFT 0x0 284 #define MMSCH_SCRATCH_7__SCRATCH_7_MASK 0xFFFFFFFFL 285 //MMSCH_VFID_FIFO_HEAD_0 286 #define MMSCH_VFID_FIFO_HEAD_0__HEAD__SHIFT 0x0 287 #define MMSCH_VFID_FIFO_HEAD_0__HEAD_MASK 0x0000003FL 288 //MMSCH_VFID_FIFO_TAIL_0 289 #define MMSCH_VFID_FIFO_TAIL_0__TAIL__SHIFT 0x0 290 #define MMSCH_VFID_FIFO_TAIL_0__TAIL_MASK 0x0000003FL 291 //MMSCH_VFID_FIFO_HEAD_1 292 #define MMSCH_VFID_FIFO_HEAD_1__HEAD__SHIFT 0x0 293 #define MMSCH_VFID_FIFO_HEAD_1__HEAD_MASK 0x0000003FL 294 //MMSCH_VFID_FIFO_TAIL_1 295 #define MMSCH_VFID_FIFO_TAIL_1__TAIL__SHIFT 0x0 296 #define MMSCH_VFID_FIFO_TAIL_1__TAIL_MASK 0x0000003FL 297 //MMSCH_NACK_STATUS 298 #define MMSCH_NACK_STATUS__WR_NACK_STATUS__SHIFT 0x0 299 #define MMSCH_NACK_STATUS__RD_NACK_STATUS__SHIFT 0x2 300 #define MMSCH_NACK_STATUS__WR_NACK_STATUS_MASK 0x00000003L 301 #define MMSCH_NACK_STATUS__RD_NACK_STATUS_MASK 0x0000000CL 302 //MMSCH_VF_MAILBOX0_DATA 303 #define MMSCH_VF_MAILBOX0_DATA__DATA__SHIFT 0x0 304 #define MMSCH_VF_MAILBOX0_DATA__DATA_MASK 0xFFFFFFFFL 305 //MMSCH_VF_MAILBOX1_DATA 306 #define MMSCH_VF_MAILBOX1_DATA__DATA__SHIFT 0x0 307 #define MMSCH_VF_MAILBOX1_DATA__DATA_MASK 0xFFFFFFFFL 308 //MMSCH_GPUIOV_SCH_BLOCK_IP_0 309 #define MMSCH_GPUIOV_SCH_BLOCK_IP_0__ID__SHIFT 0x0 310 #define MMSCH_GPUIOV_SCH_BLOCK_IP_0__VERSION__SHIFT 0x4 311 #define MMSCH_GPUIOV_SCH_BLOCK_IP_0__SIZE__SHIFT 0x8 312 #define MMSCH_GPUIOV_SCH_BLOCK_IP_0__ID_MASK 0x0000000FL 313 #define MMSCH_GPUIOV_SCH_BLOCK_IP_0__VERSION_MASK 0x000000F0L 314 #define MMSCH_GPUIOV_SCH_BLOCK_IP_0__SIZE_MASK 0x0000FF00L 315 //MMSCH_GPUIOV_CMD_STATUS_IP_0 316 #define MMSCH_GPUIOV_CMD_STATUS_IP_0__CMD_STATUS__SHIFT 0x0 317 #define MMSCH_GPUIOV_CMD_STATUS_IP_0__CMD_STATUS_MASK 0x0000000FL 318 //MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_0 319 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_0__ID__SHIFT 0x0 320 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_0__ID_STATUS__SHIFT 0x8 321 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_0__ID_MASK 0x000000FFL 322 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_0__ID_STATUS_MASK 0x00000F00L 323 //MMSCH_GPUIOV_SCH_BLOCK_IP_1 324 #define MMSCH_GPUIOV_SCH_BLOCK_IP_1__ID__SHIFT 0x0 325 #define MMSCH_GPUIOV_SCH_BLOCK_IP_1__VERSION__SHIFT 0x4 326 #define MMSCH_GPUIOV_SCH_BLOCK_IP_1__SIZE__SHIFT 0x8 327 #define MMSCH_GPUIOV_SCH_BLOCK_IP_1__ID_MASK 0x0000000FL 328 #define MMSCH_GPUIOV_SCH_BLOCK_IP_1__VERSION_MASK 0x000000F0L 329 #define MMSCH_GPUIOV_SCH_BLOCK_IP_1__SIZE_MASK 0x0000FF00L 330 //MMSCH_GPUIOV_CMD_STATUS_IP_1 331 #define MMSCH_GPUIOV_CMD_STATUS_IP_1__CMD_STATUS__SHIFT 0x0 332 #define MMSCH_GPUIOV_CMD_STATUS_IP_1__CMD_STATUS_MASK 0x0000000FL 333 //MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_1 334 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_1__ID__SHIFT 0x0 335 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_1__ID_STATUS__SHIFT 0x8 336 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_1__ID_MASK 0x000000FFL 337 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_1__ID_STATUS_MASK 0x00000F00L 338 //MMSCH_GPUIOV_CNTXT_IP 339 #define MMSCH_GPUIOV_CNTXT_IP__CNTXT_SIZE__SHIFT 0x0 340 #define MMSCH_GPUIOV_CNTXT_IP__CNTXT_LOCATION__SHIFT 0x7 341 #define MMSCH_GPUIOV_CNTXT_IP__CNTXT_SIZE_MASK 0x0000007FL 342 #define MMSCH_GPUIOV_CNTXT_IP__CNTXT_LOCATION_MASK 0x00000080L 343 //MMSCH_GPUIOV_SCH_BLOCK_2 344 #define MMSCH_GPUIOV_SCH_BLOCK_2__ID__SHIFT 0x0 345 #define MMSCH_GPUIOV_SCH_BLOCK_2__VERSION__SHIFT 0x4 346 #define MMSCH_GPUIOV_SCH_BLOCK_2__SIZE__SHIFT 0x8 347 #define MMSCH_GPUIOV_SCH_BLOCK_2__ID_MASK 0x0000000FL 348 #define MMSCH_GPUIOV_SCH_BLOCK_2__VERSION_MASK 0x000000F0L 349 #define MMSCH_GPUIOV_SCH_BLOCK_2__SIZE_MASK 0x0000FF00L 350 //MMSCH_GPUIOV_CMD_CONTROL_2 351 #define MMSCH_GPUIOV_CMD_CONTROL_2__CMD_TYPE__SHIFT 0x0 352 #define MMSCH_GPUIOV_CMD_CONTROL_2__CMD_EXECUTE__SHIFT 0x4 353 #define MMSCH_GPUIOV_CMD_CONTROL_2__CMD_EXECUTE_INTR_EN__SHIFT 0x5 354 #define MMSCH_GPUIOV_CMD_CONTROL_2__VM_BUSY_INTR_EN__SHIFT 0x6 355 #define MMSCH_GPUIOV_CMD_CONTROL_2__FUNCTINO_ID__SHIFT 0x8 356 #define MMSCH_GPUIOV_CMD_CONTROL_2__NEXT_FUNCTINO_ID__SHIFT 0x10 357 #define MMSCH_GPUIOV_CMD_CONTROL_2__CMD_TYPE_MASK 0x0000000FL 358 #define MMSCH_GPUIOV_CMD_CONTROL_2__CMD_EXECUTE_MASK 0x00000010L 359 #define MMSCH_GPUIOV_CMD_CONTROL_2__CMD_EXECUTE_INTR_EN_MASK 0x00000020L 360 #define MMSCH_GPUIOV_CMD_CONTROL_2__VM_BUSY_INTR_EN_MASK 0x00000040L 361 #define MMSCH_GPUIOV_CMD_CONTROL_2__FUNCTINO_ID_MASK 0x0000FF00L 362 #define MMSCH_GPUIOV_CMD_CONTROL_2__NEXT_FUNCTINO_ID_MASK 0x00FF0000L 363 //MMSCH_GPUIOV_CMD_STATUS_2 364 #define MMSCH_GPUIOV_CMD_STATUS_2__CMD_STATUS__SHIFT 0x0 365 #define MMSCH_GPUIOV_CMD_STATUS_2__CMD_STATUS_MASK 0x0000000FL 366 //MMSCH_GPUIOV_VM_BUSY_STATUS_2 367 #define MMSCH_GPUIOV_VM_BUSY_STATUS_2__BUSY__SHIFT 0x0 368 #define MMSCH_GPUIOV_VM_BUSY_STATUS_2__BUSY_MASK 0xFFFFFFFFL 369 //MMSCH_GPUIOV_ACTIVE_FCNS_2 370 #define MMSCH_GPUIOV_ACTIVE_FCNS_2__ACTIVE_FCNS__SHIFT 0x0 371 #define MMSCH_GPUIOV_ACTIVE_FCNS_2__ACTIVE_FCNS_MASK 0xFFFFFFFFL 372 //MMSCH_GPUIOV_ACTIVE_FCN_ID_2 373 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_2__ID__SHIFT 0x0 374 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_2__ID_STATUS__SHIFT 0x8 375 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_2__ID_MASK 0x000000FFL 376 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_2__ID_STATUS_MASK 0x00000F00L 377 //MMSCH_GPUIOV_DW6_2 378 #define MMSCH_GPUIOV_DW6_2__DATA__SHIFT 0x0 379 #define MMSCH_GPUIOV_DW6_2__DATA_MASK 0xFFFFFFFFL 380 //MMSCH_GPUIOV_DW7_2 381 #define MMSCH_GPUIOV_DW7_2__DATA__SHIFT 0x0 382 #define MMSCH_GPUIOV_DW7_2__DATA_MASK 0xFFFFFFFFL 383 //MMSCH_GPUIOV_DW8_2 384 #define MMSCH_GPUIOV_DW8_2__DATA__SHIFT 0x0 385 #define MMSCH_GPUIOV_DW8_2__DATA_MASK 0xFFFFFFFFL 386 //MMSCH_GPUIOV_SCH_BLOCK_IP_2 387 #define MMSCH_GPUIOV_SCH_BLOCK_IP_2__ID__SHIFT 0x0 388 #define MMSCH_GPUIOV_SCH_BLOCK_IP_2__VERSION__SHIFT 0x4 389 #define MMSCH_GPUIOV_SCH_BLOCK_IP_2__SIZE__SHIFT 0x8 390 #define MMSCH_GPUIOV_SCH_BLOCK_IP_2__ID_MASK 0x0000000FL 391 #define MMSCH_GPUIOV_SCH_BLOCK_IP_2__VERSION_MASK 0x000000F0L 392 #define MMSCH_GPUIOV_SCH_BLOCK_IP_2__SIZE_MASK 0x0000FF00L 393 //MMSCH_GPUIOV_CMD_STATUS_IP_2 394 #define MMSCH_GPUIOV_CMD_STATUS_IP_2__CMD_STATUS__SHIFT 0x0 395 #define MMSCH_GPUIOV_CMD_STATUS_IP_2__CMD_STATUS_MASK 0x0000000FL 396 //MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_2 397 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_2__ID__SHIFT 0x0 398 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_2__ID_STATUS__SHIFT 0x8 399 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_2__ID_MASK 0x000000FFL 400 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_2__ID_STATUS_MASK 0x00000F00L 401 //MMSCH_VFID_FIFO_HEAD_2 402 #define MMSCH_VFID_FIFO_HEAD_2__HEAD__SHIFT 0x0 403 #define MMSCH_VFID_FIFO_HEAD_2__HEAD_MASK 0x0000003FL 404 //MMSCH_VFID_FIFO_TAIL_2 405 #define MMSCH_VFID_FIFO_TAIL_2__TAIL__SHIFT 0x0 406 #define MMSCH_VFID_FIFO_TAIL_2__TAIL_MASK 0x0000003FL 407 //MMSCH_VM_BUSY_STATUS_0 408 #define MMSCH_VM_BUSY_STATUS_0__BUSY__SHIFT 0x0 409 #define MMSCH_VM_BUSY_STATUS_0__BUSY_MASK 0xFFFFFFFFL 410 //MMSCH_VM_BUSY_STATUS_1 411 #define MMSCH_VM_BUSY_STATUS_1__BUSY__SHIFT 0x0 412 #define MMSCH_VM_BUSY_STATUS_1__BUSY_MASK 0xFFFFFFFFL 413 //MMSCH_VM_BUSY_STATUS_2 414 #define MMSCH_VM_BUSY_STATUS_2__BUSY__SHIFT 0x0 415 #define MMSCH_VM_BUSY_STATUS_2__BUSY_MASK 0xFFFFFFFFL 416 417 418 // addressBlock: uvd0_jpegnpdec 419 //UVD_JPEG_CNTL 420 #define UVD_JPEG_CNTL__REQUEST_EN__SHIFT 0x1 421 #define UVD_JPEG_CNTL__ERR_RST_EN__SHIFT 0x2 422 #define UVD_JPEG_CNTL__HUFF_SPEED_EN__SHIFT 0x3 423 #define UVD_JPEG_CNTL__HUFF_SPEED_STATUS__SHIFT 0x4 424 #define UVD_JPEG_CNTL__REQUEST_EN_MASK 0x00000002L 425 #define UVD_JPEG_CNTL__ERR_RST_EN_MASK 0x00000004L 426 #define UVD_JPEG_CNTL__HUFF_SPEED_EN_MASK 0x00000008L 427 #define UVD_JPEG_CNTL__HUFF_SPEED_STATUS_MASK 0x00000010L 428 //UVD_JPEG_RB_BASE 429 #define UVD_JPEG_RB_BASE__RB_BYTE_OFF__SHIFT 0x0 430 #define UVD_JPEG_RB_BASE__RB_BASE__SHIFT 0x6 431 #define UVD_JPEG_RB_BASE__RB_BYTE_OFF_MASK 0x0000003FL 432 #define UVD_JPEG_RB_BASE__RB_BASE_MASK 0xFFFFFFC0L 433 //UVD_JPEG_RB_WPTR 434 #define UVD_JPEG_RB_WPTR__RB_WPTR__SHIFT 0x4 435 #define UVD_JPEG_RB_WPTR__RB_WPTR_MASK 0x3FFFFFF0L 436 //UVD_JPEG_RB_RPTR 437 #define UVD_JPEG_RB_RPTR__RB_RPTR__SHIFT 0x4 438 #define UVD_JPEG_RB_RPTR__RB_RPTR_MASK 0x3FFFFFF0L 439 //UVD_JPEG_RB_SIZE 440 #define UVD_JPEG_RB_SIZE__RB_SIZE__SHIFT 0x4 441 #define UVD_JPEG_RB_SIZE__RB_SIZE_MASK 0x3FFFFFF0L 442 //UVD_JPEG_DEC_SCRATCH0 443 #define UVD_JPEG_DEC_SCRATCH0__SCRATCH0__SHIFT 0x0 444 #define UVD_JPEG_DEC_SCRATCH0__SCRATCH0_MASK 0xFFFFFFFFL 445 //UVD_JPEG_INT_EN 446 #define UVD_JPEG_INT_EN__OUTBUF_WPTR_INC_EN__SHIFT 0x0 447 #define UVD_JPEG_INT_EN__JOB_AVAIL_EN__SHIFT 0x1 448 #define UVD_JPEG_INT_EN__FENCE_VAL_EN__SHIFT 0x2 449 #define UVD_JPEG_INT_EN__FIFO_OVERFLOW_ERR_EN__SHIFT 0x6 450 #define UVD_JPEG_INT_EN__BLK_CNT_OUT_OF_SYNC_ERR_EN__SHIFT 0x7 451 #define UVD_JPEG_INT_EN__EOI_ERR_EN__SHIFT 0x8 452 #define UVD_JPEG_INT_EN__HFM_ERR_EN__SHIFT 0x9 453 #define UVD_JPEG_INT_EN__RST_ERR_EN__SHIFT 0xa 454 #define UVD_JPEG_INT_EN__ECS_MK_ERR_EN__SHIFT 0xb 455 #define UVD_JPEG_INT_EN__TIMEOUT_ERR_EN__SHIFT 0xc 456 #define UVD_JPEG_INT_EN__MARKER_ERR_EN__SHIFT 0xd 457 #define UVD_JPEG_INT_EN__FMT_ERR_EN__SHIFT 0xe 458 #define UVD_JPEG_INT_EN__PROFILE_ERR_EN__SHIFT 0xf 459 #define UVD_JPEG_INT_EN__OUTBUF_WPTR_INC_EN_MASK 0x00000001L 460 #define UVD_JPEG_INT_EN__JOB_AVAIL_EN_MASK 0x00000002L 461 #define UVD_JPEG_INT_EN__FENCE_VAL_EN_MASK 0x00000004L 462 #define UVD_JPEG_INT_EN__FIFO_OVERFLOW_ERR_EN_MASK 0x00000040L 463 #define UVD_JPEG_INT_EN__BLK_CNT_OUT_OF_SYNC_ERR_EN_MASK 0x00000080L 464 #define UVD_JPEG_INT_EN__EOI_ERR_EN_MASK 0x00000100L 465 #define UVD_JPEG_INT_EN__HFM_ERR_EN_MASK 0x00000200L 466 #define UVD_JPEG_INT_EN__RST_ERR_EN_MASK 0x00000400L 467 #define UVD_JPEG_INT_EN__ECS_MK_ERR_EN_MASK 0x00000800L 468 #define UVD_JPEG_INT_EN__TIMEOUT_ERR_EN_MASK 0x00001000L 469 #define UVD_JPEG_INT_EN__MARKER_ERR_EN_MASK 0x00002000L 470 #define UVD_JPEG_INT_EN__FMT_ERR_EN_MASK 0x00004000L 471 #define UVD_JPEG_INT_EN__PROFILE_ERR_EN_MASK 0x00008000L 472 //UVD_JPEG_INT_STAT 473 #define UVD_JPEG_INT_STAT__OUTBUF_WPTR_INC_INT__SHIFT 0x0 474 #define UVD_JPEG_INT_STAT__JOB_AVAIL_INT__SHIFT 0x1 475 #define UVD_JPEG_INT_STAT__FENCE_VAL_INT__SHIFT 0x2 476 #define UVD_JPEG_INT_STAT__FIFO_OVERFLOW_ERR_INT__SHIFT 0x6 477 #define UVD_JPEG_INT_STAT__BLK_CNT_OUT_OF_SYNC_ERR_INT__SHIFT 0x7 478 #define UVD_JPEG_INT_STAT__EOI_ERR_INT__SHIFT 0x8 479 #define UVD_JPEG_INT_STAT__HFM_ERR_INT__SHIFT 0x9 480 #define UVD_JPEG_INT_STAT__RST_ERR_INT__SHIFT 0xa 481 #define UVD_JPEG_INT_STAT__ECS_MK_ERR_INT__SHIFT 0xb 482 #define UVD_JPEG_INT_STAT__TIMEOUT_ERR_INT__SHIFT 0xc 483 #define UVD_JPEG_INT_STAT__MARKER_ERR_INT__SHIFT 0xd 484 #define UVD_JPEG_INT_STAT__FMT_ERR_INT__SHIFT 0xe 485 #define UVD_JPEG_INT_STAT__PROFILE_ERR_INT__SHIFT 0xf 486 #define UVD_JPEG_INT_STAT__OUTBUF_WPTR_INC_INT_MASK 0x00000001L 487 #define UVD_JPEG_INT_STAT__JOB_AVAIL_INT_MASK 0x00000002L 488 #define UVD_JPEG_INT_STAT__FENCE_VAL_INT_MASK 0x00000004L 489 #define UVD_JPEG_INT_STAT__FIFO_OVERFLOW_ERR_INT_MASK 0x00000040L 490 #define UVD_JPEG_INT_STAT__BLK_CNT_OUT_OF_SYNC_ERR_INT_MASK 0x00000080L 491 #define UVD_JPEG_INT_STAT__EOI_ERR_INT_MASK 0x00000100L 492 #define UVD_JPEG_INT_STAT__HFM_ERR_INT_MASK 0x00000200L 493 #define UVD_JPEG_INT_STAT__RST_ERR_INT_MASK 0x00000400L 494 #define UVD_JPEG_INT_STAT__ECS_MK_ERR_INT_MASK 0x00000800L 495 #define UVD_JPEG_INT_STAT__TIMEOUT_ERR_INT_MASK 0x00001000L 496 #define UVD_JPEG_INT_STAT__MARKER_ERR_INT_MASK 0x00002000L 497 #define UVD_JPEG_INT_STAT__FMT_ERR_INT_MASK 0x00004000L 498 #define UVD_JPEG_INT_STAT__PROFILE_ERR_INT_MASK 0x00008000L 499 //UVD_JPEG_PITCH 500 #define UVD_JPEG_PITCH__PITCH__SHIFT 0x0 501 #define UVD_JPEG_PITCH__PITCH_MASK 0xFFFFFFFFL 502 //UVD_JPEG_UV_PITCH 503 #define UVD_JPEG_UV_PITCH__UV_PITCH__SHIFT 0x0 504 #define UVD_JPEG_UV_PITCH__UV_PITCH_MASK 0xFFFFFFFFL 505 //JPEG_DEC_Y_GFX8_TILING_SURFACE 506 #define JPEG_DEC_Y_GFX8_TILING_SURFACE__BANK_WIDTH__SHIFT 0x0 507 #define JPEG_DEC_Y_GFX8_TILING_SURFACE__BANK_HEIGHT__SHIFT 0x2 508 #define JPEG_DEC_Y_GFX8_TILING_SURFACE__MACRO_TILE_ASPECT__SHIFT 0x4 509 #define JPEG_DEC_Y_GFX8_TILING_SURFACE__NUM_BANKS__SHIFT 0x6 510 #define JPEG_DEC_Y_GFX8_TILING_SURFACE__PIPE_CONFIG__SHIFT 0x8 511 #define JPEG_DEC_Y_GFX8_TILING_SURFACE__TILE_SPLIT__SHIFT 0xd 512 #define JPEG_DEC_Y_GFX8_TILING_SURFACE__ARRAY_MODE__SHIFT 0x10 513 #define JPEG_DEC_Y_GFX8_TILING_SURFACE__BANK_WIDTH_MASK 0x00000003L 514 #define JPEG_DEC_Y_GFX8_TILING_SURFACE__BANK_HEIGHT_MASK 0x0000000CL 515 #define JPEG_DEC_Y_GFX8_TILING_SURFACE__MACRO_TILE_ASPECT_MASK 0x00000030L 516 #define JPEG_DEC_Y_GFX8_TILING_SURFACE__NUM_BANKS_MASK 0x000000C0L 517 #define JPEG_DEC_Y_GFX8_TILING_SURFACE__PIPE_CONFIG_MASK 0x00001F00L 518 #define JPEG_DEC_Y_GFX8_TILING_SURFACE__TILE_SPLIT_MASK 0x0000E000L 519 #define JPEG_DEC_Y_GFX8_TILING_SURFACE__ARRAY_MODE_MASK 0x000F0000L 520 //JPEG_DEC_UV_GFX8_TILING_SURFACE 521 #define JPEG_DEC_UV_GFX8_TILING_SURFACE__BANK_WIDTH__SHIFT 0x0 522 #define JPEG_DEC_UV_GFX8_TILING_SURFACE__BANK_HEIGHT__SHIFT 0x2 523 #define JPEG_DEC_UV_GFX8_TILING_SURFACE__MACRO_TILE_ASPECT__SHIFT 0x4 524 #define JPEG_DEC_UV_GFX8_TILING_SURFACE__NUM_BANKS__SHIFT 0x6 525 #define JPEG_DEC_UV_GFX8_TILING_SURFACE__PIPE_CONFIG__SHIFT 0x8 526 #define JPEG_DEC_UV_GFX8_TILING_SURFACE__TILE_SPLIT__SHIFT 0xd 527 #define JPEG_DEC_UV_GFX8_TILING_SURFACE__ARRAY_MODE__SHIFT 0x10 528 #define JPEG_DEC_UV_GFX8_TILING_SURFACE__BANK_WIDTH_MASK 0x00000003L 529 #define JPEG_DEC_UV_GFX8_TILING_SURFACE__BANK_HEIGHT_MASK 0x0000000CL 530 #define JPEG_DEC_UV_GFX8_TILING_SURFACE__MACRO_TILE_ASPECT_MASK 0x00000030L 531 #define JPEG_DEC_UV_GFX8_TILING_SURFACE__NUM_BANKS_MASK 0x000000C0L 532 #define JPEG_DEC_UV_GFX8_TILING_SURFACE__PIPE_CONFIG_MASK 0x00001F00L 533 #define JPEG_DEC_UV_GFX8_TILING_SURFACE__TILE_SPLIT_MASK 0x0000E000L 534 #define JPEG_DEC_UV_GFX8_TILING_SURFACE__ARRAY_MODE_MASK 0x000F0000L 535 //JPEG_DEC_GFX8_ADDR_CONFIG 536 #define JPEG_DEC_GFX8_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 537 #define JPEG_DEC_GFX8_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000070L 538 //JPEG_DEC_Y_GFX10_TILING_SURFACE 539 #define JPEG_DEC_Y_GFX10_TILING_SURFACE__SWIZZLE_MODE__SHIFT 0x0 540 #define JPEG_DEC_Y_GFX10_TILING_SURFACE__SWIZZLE_MODE_MASK 0x0000001FL 541 //JPEG_DEC_UV_GFX10_TILING_SURFACE 542 #define JPEG_DEC_UV_GFX10_TILING_SURFACE__SWIZZLE_MODE__SHIFT 0x0 543 #define JPEG_DEC_UV_GFX10_TILING_SURFACE__SWIZZLE_MODE_MASK 0x0000001FL 544 //JPEG_DEC_GFX10_ADDR_CONFIG 545 #define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 546 #define JPEG_DEC_GFX10_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 547 #define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc 548 #define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 549 #define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L 550 #define JPEG_DEC_GFX10_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L 551 #define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L 552 #define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L 553 //JPEG_DEC_ADDR_MODE 554 #define JPEG_DEC_ADDR_MODE__ADDR_MODE_Y__SHIFT 0x0 555 #define JPEG_DEC_ADDR_MODE__ADDR_MODE_UV__SHIFT 0x2 556 #define JPEG_DEC_ADDR_MODE__ADDR_LIB_SEL__SHIFT 0xc 557 #define JPEG_DEC_ADDR_MODE__ADDR_MODE_Y_MASK 0x00000003L 558 #define JPEG_DEC_ADDR_MODE__ADDR_MODE_UV_MASK 0x0000000CL 559 #define JPEG_DEC_ADDR_MODE__ADDR_LIB_SEL_MASK 0x00007000L 560 //UVD_JPEG_GPCOM_CMD 561 #define UVD_JPEG_GPCOM_CMD__CMD__SHIFT 0x1 562 #define UVD_JPEG_GPCOM_CMD__CMD_MASK 0x0000000EL 563 //UVD_JPEG_GPCOM_DATA0 564 #define UVD_JPEG_GPCOM_DATA0__DATA0__SHIFT 0x0 565 #define UVD_JPEG_GPCOM_DATA0__DATA0_MASK 0xFFFFFFFFL 566 //UVD_JPEG_GPCOM_DATA1 567 #define UVD_JPEG_GPCOM_DATA1__DATA1__SHIFT 0x0 568 #define UVD_JPEG_GPCOM_DATA1__DATA1_MASK 0xFFFFFFFFL 569 //UVD_JPEG_SCRATCH1 570 #define UVD_JPEG_SCRATCH1__SCRATCH1__SHIFT 0x0 571 #define UVD_JPEG_SCRATCH1__SCRATCH1_MASK 0xFFFFFFFFL 572 //UVD_JPEG_DEC_SOFT_RST 573 #define UVD_JPEG_DEC_SOFT_RST__SOFT_RESET__SHIFT 0x0 574 #define UVD_JPEG_DEC_SOFT_RST__RESET_STATUS__SHIFT 0x10 575 #define UVD_JPEG_DEC_SOFT_RST__SOFT_RESET_MASK 0x00000001L 576 #define UVD_JPEG_DEC_SOFT_RST__RESET_STATUS_MASK 0x00010000L 577 578 579 // addressBlock: uvd0_uvd_jpeg_enc_dec 580 //UVD_JPEG_ENC_INT_EN 581 #define UVD_JPEG_ENC_INT_EN__HUFF_JOB_DONE_INT_EN__SHIFT 0x0 582 #define UVD_JPEG_ENC_INT_EN__SCLR_JOB_DONE_INT_EN__SHIFT 0x1 583 #define UVD_JPEG_ENC_INT_EN__HUFF_ERROR_INT_EN__SHIFT 0x2 584 #define UVD_JPEG_ENC_INT_EN__SCLR_ERROR_INT_EN__SHIFT 0x3 585 #define UVD_JPEG_ENC_INT_EN__QTBL_ERROR_INT_EN__SHIFT 0x4 586 #define UVD_JPEG_ENC_INT_EN__PIC_SIZE_ERROR_INT_EN__SHIFT 0x5 587 #define UVD_JPEG_ENC_INT_EN__FENCE_VAL_INT_EN__SHIFT 0x6 588 #define UVD_JPEG_ENC_INT_EN__HUFF_JOB_DONE_INT_EN_MASK 0x00000001L 589 #define UVD_JPEG_ENC_INT_EN__SCLR_JOB_DONE_INT_EN_MASK 0x00000002L 590 #define UVD_JPEG_ENC_INT_EN__HUFF_ERROR_INT_EN_MASK 0x00000004L 591 #define UVD_JPEG_ENC_INT_EN__SCLR_ERROR_INT_EN_MASK 0x00000008L 592 #define UVD_JPEG_ENC_INT_EN__QTBL_ERROR_INT_EN_MASK 0x00000010L 593 #define UVD_JPEG_ENC_INT_EN__PIC_SIZE_ERROR_INT_EN_MASK 0x00000020L 594 #define UVD_JPEG_ENC_INT_EN__FENCE_VAL_INT_EN_MASK 0x00000040L 595 //UVD_JPEG_ENC_INT_STATUS 596 #define UVD_JPEG_ENC_INT_STATUS__HUFF_JOB_DONE_STATUS__SHIFT 0x0 597 #define UVD_JPEG_ENC_INT_STATUS__SCLR_JOB_DONE_STATUS__SHIFT 0x1 598 #define UVD_JPEG_ENC_INT_STATUS__HUFF_ERROR_STATUS__SHIFT 0x2 599 #define UVD_JPEG_ENC_INT_STATUS__SCLR_ERROR_STATUS__SHIFT 0x3 600 #define UVD_JPEG_ENC_INT_STATUS__QTBL_ERROR_STATUS__SHIFT 0x4 601 #define UVD_JPEG_ENC_INT_STATUS__PIC_SIZE_ERROR_STATUS__SHIFT 0x5 602 #define UVD_JPEG_ENC_INT_STATUS__FENCE_VAL_STATUS__SHIFT 0x6 603 #define UVD_JPEG_ENC_INT_STATUS__HUFF_JOB_DONE_STATUS_MASK 0x00000001L 604 #define UVD_JPEG_ENC_INT_STATUS__SCLR_JOB_DONE_STATUS_MASK 0x00000002L 605 #define UVD_JPEG_ENC_INT_STATUS__HUFF_ERROR_STATUS_MASK 0x00000004L 606 #define UVD_JPEG_ENC_INT_STATUS__SCLR_ERROR_STATUS_MASK 0x00000008L 607 #define UVD_JPEG_ENC_INT_STATUS__QTBL_ERROR_STATUS_MASK 0x00000010L 608 #define UVD_JPEG_ENC_INT_STATUS__PIC_SIZE_ERROR_STATUS_MASK 0x00000020L 609 #define UVD_JPEG_ENC_INT_STATUS__FENCE_VAL_STATUS_MASK 0x00000040L 610 //UVD_JPEG_ENC_ENGINE_CNTL 611 #define UVD_JPEG_ENC_ENGINE_CNTL__HUFF_WR_COMB_DIS__SHIFT 0x0 612 #define UVD_JPEG_ENC_ENGINE_CNTL__DISTINCT_CHROMA_QUANT_TABLES__SHIFT 0x1 613 #define UVD_JPEG_ENC_ENGINE_CNTL__SCALAR_EN__SHIFT 0x2 614 #define UVD_JPEG_ENC_ENGINE_CNTL__ENCODE_EN__SHIFT 0x3 615 #define UVD_JPEG_ENC_ENGINE_CNTL__CMP_NEEDED__SHIFT 0x4 616 #define UVD_JPEG_ENC_ENGINE_CNTL__ECS_RESTRICT_32B_EN__SHIFT 0x9 617 #define UVD_JPEG_ENC_ENGINE_CNTL__HUFF_WR_COMB_DIS_MASK 0x00000001L 618 #define UVD_JPEG_ENC_ENGINE_CNTL__DISTINCT_CHROMA_QUANT_TABLES_MASK 0x00000002L 619 #define UVD_JPEG_ENC_ENGINE_CNTL__SCALAR_EN_MASK 0x00000004L 620 #define UVD_JPEG_ENC_ENGINE_CNTL__ENCODE_EN_MASK 0x00000008L 621 #define UVD_JPEG_ENC_ENGINE_CNTL__CMP_NEEDED_MASK 0x00000010L 622 #define UVD_JPEG_ENC_ENGINE_CNTL__ECS_RESTRICT_32B_EN_MASK 0x00000200L 623 //UVD_JPEG_ENC_SCRATCH1 624 #define UVD_JPEG_ENC_SCRATCH1__SCRATCH1__SHIFT 0x0 625 #define UVD_JPEG_ENC_SCRATCH1__SCRATCH1_MASK 0xFFFFFFFFL 626 627 628 // addressBlock: uvd0_uvd_jpeg_enc_sclk_dec 629 //UVD_JPEG_ENC_STATUS 630 #define UVD_JPEG_ENC_STATUS__PEL_FETCH_IDLE__SHIFT 0x0 631 #define UVD_JPEG_ENC_STATUS__HUFF_CORE_IDLE__SHIFT 0x1 632 #define UVD_JPEG_ENC_STATUS__FDCT_IDLE__SHIFT 0x2 633 #define UVD_JPEG_ENC_STATUS__SCALAR_IDLE__SHIFT 0x3 634 #define UVD_JPEG_ENC_STATUS__PEL_FETCH_IDLE_MASK 0x00000001L 635 #define UVD_JPEG_ENC_STATUS__HUFF_CORE_IDLE_MASK 0x00000002L 636 #define UVD_JPEG_ENC_STATUS__FDCT_IDLE_MASK 0x00000004L 637 #define UVD_JPEG_ENC_STATUS__SCALAR_IDLE_MASK 0x00000008L 638 //UVD_JPEG_ENC_PITCH 639 #define UVD_JPEG_ENC_PITCH__PITCH_Y__SHIFT 0x0 640 #define UVD_JPEG_ENC_PITCH__PITCH_UV__SHIFT 0x10 641 #define UVD_JPEG_ENC_PITCH__PITCH_Y_MASK 0x00000FFFL 642 #define UVD_JPEG_ENC_PITCH__PITCH_UV_MASK 0x0FFF0000L 643 //UVD_JPEG_ENC_LUMA_BASE 644 #define UVD_JPEG_ENC_LUMA_BASE__LUMA_BASE__SHIFT 0x0 645 #define UVD_JPEG_ENC_LUMA_BASE__LUMA_BASE_MASK 0xFFFFFFFFL 646 //UVD_JPEG_ENC_CHROMAU_BASE 647 #define UVD_JPEG_ENC_CHROMAU_BASE__CHROMAU_BASE__SHIFT 0x0 648 #define UVD_JPEG_ENC_CHROMAU_BASE__CHROMAU_BASE_MASK 0xFFFFFFFFL 649 //UVD_JPEG_ENC_CHROMAV_BASE 650 #define UVD_JPEG_ENC_CHROMAV_BASE__CHROMAV_BASE__SHIFT 0x0 651 #define UVD_JPEG_ENC_CHROMAV_BASE__CHROMAV_BASE_MASK 0xFFFFFFFFL 652 //JPEG_ENC_Y_GFX10_TILING_SURFACE 653 #define JPEG_ENC_Y_GFX10_TILING_SURFACE__SWIZZLE_MODE__SHIFT 0x0 654 #define JPEG_ENC_Y_GFX10_TILING_SURFACE__SWIZZLE_MODE_MASK 0x0000001FL 655 //JPEG_ENC_UV_GFX10_TILING_SURFACE 656 #define JPEG_ENC_UV_GFX10_TILING_SURFACE__SWIZZLE_MODE__SHIFT 0x0 657 #define JPEG_ENC_UV_GFX10_TILING_SURFACE__SWIZZLE_MODE_MASK 0x0000001FL 658 //JPEG_ENC_GFX10_ADDR_CONFIG 659 #define JPEG_ENC_GFX10_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 660 #define JPEG_ENC_GFX10_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 661 #define JPEG_ENC_GFX10_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc 662 #define JPEG_ENC_GFX10_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 663 #define JPEG_ENC_GFX10_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L 664 #define JPEG_ENC_GFX10_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L 665 #define JPEG_ENC_GFX10_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L 666 #define JPEG_ENC_GFX10_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L 667 //JPEG_ENC_ADDR_MODE 668 #define JPEG_ENC_ADDR_MODE__ADDR_MODE_Y__SHIFT 0x0 669 #define JPEG_ENC_ADDR_MODE__ADDR_MODE_UV__SHIFT 0x2 670 #define JPEG_ENC_ADDR_MODE__ADDR_LIB_SEL__SHIFT 0xc 671 #define JPEG_ENC_ADDR_MODE__ADDR_MODE_Y_MASK 0x00000003L 672 #define JPEG_ENC_ADDR_MODE__ADDR_MODE_UV_MASK 0x0000000CL 673 #define JPEG_ENC_ADDR_MODE__ADDR_LIB_SEL_MASK 0x00007000L 674 //UVD_JPEG_ENC_GPCOM_CMD 675 #define UVD_JPEG_ENC_GPCOM_CMD__CMD__SHIFT 0x1 676 #define UVD_JPEG_ENC_GPCOM_CMD__CMD_MASK 0x0000000EL 677 //UVD_JPEG_ENC_GPCOM_DATA0 678 #define UVD_JPEG_ENC_GPCOM_DATA0__DATA0__SHIFT 0x0 679 #define UVD_JPEG_ENC_GPCOM_DATA0__DATA0_MASK 0xFFFFFFFFL 680 //UVD_JPEG_ENC_GPCOM_DATA1 681 #define UVD_JPEG_ENC_GPCOM_DATA1__DATA1__SHIFT 0x0 682 #define UVD_JPEG_ENC_GPCOM_DATA1__DATA1_MASK 0xFFFFFFFFL 683 //UVD_JPEG_ENC_CGC_CNTL 684 #define UVD_JPEG_ENC_CGC_CNTL__CGC_EN__SHIFT 0x0 685 #define UVD_JPEG_ENC_CGC_CNTL__CGC_EN_MASK 0x00000001L 686 //UVD_JPEG_ENC_SCRATCH0 687 #define UVD_JPEG_ENC_SCRATCH0__SCRATCH0__SHIFT 0x0 688 #define UVD_JPEG_ENC_SCRATCH0__SCRATCH0_MASK 0xFFFFFFFFL 689 //UVD_JPEG_ENC_SOFT_RST 690 #define UVD_JPEG_ENC_SOFT_RST__SOFT_RST__SHIFT 0x0 691 #define UVD_JPEG_ENC_SOFT_RST__RESET_STATUS__SHIFT 0x10 692 #define UVD_JPEG_ENC_SOFT_RST__SOFT_RST_MASK 0x00000001L 693 #define UVD_JPEG_ENC_SOFT_RST__RESET_STATUS_MASK 0x00010000L 694 695 696 // addressBlock: uvd0_uvd_jrbc_dec 697 //UVD_JRBC_RB_WPTR 698 #define UVD_JRBC_RB_WPTR__RB_WPTR__SHIFT 0x4 699 #define UVD_JRBC_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L 700 //UVD_JRBC_RB_CNTL 701 #define UVD_JRBC_RB_CNTL__RB_NO_FETCH__SHIFT 0x0 702 #define UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN__SHIFT 0x1 703 #define UVD_JRBC_RB_CNTL__RB_PRE_WRITE_TIMER__SHIFT 0x4 704 #define UVD_JRBC_RB_CNTL__RB_NO_FETCH_MASK 0x00000001L 705 #define UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x00000002L 706 #define UVD_JRBC_RB_CNTL__RB_PRE_WRITE_TIMER_MASK 0x0007FFF0L 707 //UVD_JRBC_IB_SIZE 708 #define UVD_JRBC_IB_SIZE__IB_SIZE__SHIFT 0x4 709 #define UVD_JRBC_IB_SIZE__IB_SIZE_MASK 0x007FFFF0L 710 //UVD_JRBC_URGENT_CNTL 711 #define UVD_JRBC_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK__SHIFT 0x0 712 #define UVD_JRBC_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK_MASK 0x00000003L 713 //UVD_JRBC_RB_REF_DATA 714 #define UVD_JRBC_RB_REF_DATA__REF_DATA__SHIFT 0x0 715 #define UVD_JRBC_RB_REF_DATA__REF_DATA_MASK 0xFFFFFFFFL 716 //UVD_JRBC_RB_COND_RD_TIMER 717 #define UVD_JRBC_RB_COND_RD_TIMER__RETRY_TIMER_CNT__SHIFT 0x0 718 #define UVD_JRBC_RB_COND_RD_TIMER__RETRY_INTERVAL_CNT__SHIFT 0x10 719 #define UVD_JRBC_RB_COND_RD_TIMER__CONTINUOUS_POLL_EN__SHIFT 0x18 720 #define UVD_JRBC_RB_COND_RD_TIMER__MEM_TIMEOUT_EN__SHIFT 0x19 721 #define UVD_JRBC_RB_COND_RD_TIMER__RETRY_TIMER_CNT_MASK 0x0000FFFFL 722 #define UVD_JRBC_RB_COND_RD_TIMER__RETRY_INTERVAL_CNT_MASK 0x00FF0000L 723 #define UVD_JRBC_RB_COND_RD_TIMER__CONTINUOUS_POLL_EN_MASK 0x01000000L 724 #define UVD_JRBC_RB_COND_RD_TIMER__MEM_TIMEOUT_EN_MASK 0x02000000L 725 //UVD_JRBC_SOFT_RESET 726 #define UVD_JRBC_SOFT_RESET__RESET__SHIFT 0x0 727 #define UVD_JRBC_SOFT_RESET__SCLK_RESET_STATUS__SHIFT 0x11 728 #define UVD_JRBC_SOFT_RESET__RESET_MASK 0x00000001L 729 #define UVD_JRBC_SOFT_RESET__SCLK_RESET_STATUS_MASK 0x00020000L 730 //UVD_JRBC_STATUS 731 #define UVD_JRBC_STATUS__RB_JOB_DONE__SHIFT 0x0 732 #define UVD_JRBC_STATUS__IB_JOB_DONE__SHIFT 0x1 733 #define UVD_JRBC_STATUS__RB_ILLEGAL_CMD__SHIFT 0x2 734 #define UVD_JRBC_STATUS__RB_COND_REG_RD_TIMEOUT__SHIFT 0x3 735 #define UVD_JRBC_STATUS__RB_MEM_WR_TIMEOUT__SHIFT 0x4 736 #define UVD_JRBC_STATUS__RB_MEM_RD_TIMEOUT__SHIFT 0x5 737 #define UVD_JRBC_STATUS__IB_ILLEGAL_CMD__SHIFT 0x6 738 #define UVD_JRBC_STATUS__IB_COND_REG_RD_TIMEOUT__SHIFT 0x7 739 #define UVD_JRBC_STATUS__IB_MEM_WR_TIMEOUT__SHIFT 0x8 740 #define UVD_JRBC_STATUS__IB_MEM_RD_TIMEOUT__SHIFT 0x9 741 #define UVD_JRBC_STATUS__RB_TRAP_STATUS__SHIFT 0xa 742 #define UVD_JRBC_STATUS__PREEMPT_STATUS__SHIFT 0xb 743 #define UVD_JRBC_STATUS__IB_TRAP_STATUS__SHIFT 0xc 744 #define UVD_JRBC_STATUS__INT_EN__SHIFT 0x10 745 #define UVD_JRBC_STATUS__INT_ACK__SHIFT 0x11 746 #define UVD_JRBC_STATUS__RB_JOB_DONE_MASK 0x00000001L 747 #define UVD_JRBC_STATUS__IB_JOB_DONE_MASK 0x00000002L 748 #define UVD_JRBC_STATUS__RB_ILLEGAL_CMD_MASK 0x00000004L 749 #define UVD_JRBC_STATUS__RB_COND_REG_RD_TIMEOUT_MASK 0x00000008L 750 #define UVD_JRBC_STATUS__RB_MEM_WR_TIMEOUT_MASK 0x00000010L 751 #define UVD_JRBC_STATUS__RB_MEM_RD_TIMEOUT_MASK 0x00000020L 752 #define UVD_JRBC_STATUS__IB_ILLEGAL_CMD_MASK 0x00000040L 753 #define UVD_JRBC_STATUS__IB_COND_REG_RD_TIMEOUT_MASK 0x00000080L 754 #define UVD_JRBC_STATUS__IB_MEM_WR_TIMEOUT_MASK 0x00000100L 755 #define UVD_JRBC_STATUS__IB_MEM_RD_TIMEOUT_MASK 0x00000200L 756 #define UVD_JRBC_STATUS__RB_TRAP_STATUS_MASK 0x00000400L 757 #define UVD_JRBC_STATUS__PREEMPT_STATUS_MASK 0x00000800L 758 #define UVD_JRBC_STATUS__IB_TRAP_STATUS_MASK 0x00001000L 759 #define UVD_JRBC_STATUS__INT_EN_MASK 0x00010000L 760 #define UVD_JRBC_STATUS__INT_ACK_MASK 0x00020000L 761 //UVD_JRBC_RB_RPTR 762 #define UVD_JRBC_RB_RPTR__RB_RPTR__SHIFT 0x4 763 #define UVD_JRBC_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L 764 //UVD_JRBC_RB_BUF_STATUS 765 #define UVD_JRBC_RB_BUF_STATUS__RB_BUF_VALID__SHIFT 0x0 766 #define UVD_JRBC_RB_BUF_STATUS__RB_BUF_RD_ADDR__SHIFT 0x10 767 #define UVD_JRBC_RB_BUF_STATUS__RB_BUF_WR_ADDR__SHIFT 0x18 768 #define UVD_JRBC_RB_BUF_STATUS__RB_BUF_VALID_MASK 0x0000FFFFL 769 #define UVD_JRBC_RB_BUF_STATUS__RB_BUF_RD_ADDR_MASK 0x000F0000L 770 #define UVD_JRBC_RB_BUF_STATUS__RB_BUF_WR_ADDR_MASK 0x03000000L 771 //UVD_JRBC_IB_BUF_STATUS 772 #define UVD_JRBC_IB_BUF_STATUS__IB_BUF_VALID__SHIFT 0x0 773 #define UVD_JRBC_IB_BUF_STATUS__IB_BUF_RD_ADDR__SHIFT 0x10 774 #define UVD_JRBC_IB_BUF_STATUS__IB_BUF_WR_ADDR__SHIFT 0x18 775 #define UVD_JRBC_IB_BUF_STATUS__IB_BUF_VALID_MASK 0x0000FFFFL 776 #define UVD_JRBC_IB_BUF_STATUS__IB_BUF_RD_ADDR_MASK 0x000F0000L 777 #define UVD_JRBC_IB_BUF_STATUS__IB_BUF_WR_ADDR_MASK 0x03000000L 778 //UVD_JRBC_IB_SIZE_UPDATE 779 #define UVD_JRBC_IB_SIZE_UPDATE__REMAIN_IB_SIZE__SHIFT 0x4 780 #define UVD_JRBC_IB_SIZE_UPDATE__REMAIN_IB_SIZE_MASK 0x007FFFF0L 781 //UVD_JRBC_IB_COND_RD_TIMER 782 #define UVD_JRBC_IB_COND_RD_TIMER__RETRY_TIMER_CNT__SHIFT 0x0 783 #define UVD_JRBC_IB_COND_RD_TIMER__RETRY_INTERVAL_CNT__SHIFT 0x10 784 #define UVD_JRBC_IB_COND_RD_TIMER__CONTINUOUS_POLL_EN__SHIFT 0x18 785 #define UVD_JRBC_IB_COND_RD_TIMER__MEM_TIMEOUT_EN__SHIFT 0x19 786 #define UVD_JRBC_IB_COND_RD_TIMER__RETRY_TIMER_CNT_MASK 0x0000FFFFL 787 #define UVD_JRBC_IB_COND_RD_TIMER__RETRY_INTERVAL_CNT_MASK 0x00FF0000L 788 #define UVD_JRBC_IB_COND_RD_TIMER__CONTINUOUS_POLL_EN_MASK 0x01000000L 789 #define UVD_JRBC_IB_COND_RD_TIMER__MEM_TIMEOUT_EN_MASK 0x02000000L 790 //UVD_JRBC_IB_REF_DATA 791 #define UVD_JRBC_IB_REF_DATA__REF_DATA__SHIFT 0x0 792 #define UVD_JRBC_IB_REF_DATA__REF_DATA_MASK 0xFFFFFFFFL 793 //UVD_JPEG_PREEMPT_CMD 794 #define UVD_JPEG_PREEMPT_CMD__PREEMPT_EN__SHIFT 0x0 795 #define UVD_JPEG_PREEMPT_CMD__WAIT_JPEG_JOB_DONE__SHIFT 0x1 796 #define UVD_JPEG_PREEMPT_CMD__PREEMPT_FENCE_CMD__SHIFT 0x2 797 #define UVD_JPEG_PREEMPT_CMD__PREEMPT_EN_MASK 0x00000001L 798 #define UVD_JPEG_PREEMPT_CMD__WAIT_JPEG_JOB_DONE_MASK 0x00000002L 799 #define UVD_JPEG_PREEMPT_CMD__PREEMPT_FENCE_CMD_MASK 0x00000004L 800 //UVD_JPEG_PREEMPT_FENCE_DATA0 801 #define UVD_JPEG_PREEMPT_FENCE_DATA0__PREEMPT_FENCE_DATA0__SHIFT 0x0 802 #define UVD_JPEG_PREEMPT_FENCE_DATA0__PREEMPT_FENCE_DATA0_MASK 0xFFFFFFFFL 803 //UVD_JPEG_PREEMPT_FENCE_DATA1 804 #define UVD_JPEG_PREEMPT_FENCE_DATA1__PREEMPT_FENCE_DATA1__SHIFT 0x0 805 #define UVD_JPEG_PREEMPT_FENCE_DATA1__PREEMPT_FENCE_DATA1_MASK 0xFFFFFFFFL 806 //UVD_JRBC_RB_SIZE 807 #define UVD_JRBC_RB_SIZE__RB_SIZE__SHIFT 0x4 808 #define UVD_JRBC_RB_SIZE__RB_SIZE_MASK 0x00FFFFF0L 809 //UVD_JRBC_SCRATCH0 810 #define UVD_JRBC_SCRATCH0__SCRATCH0__SHIFT 0x0 811 #define UVD_JRBC_SCRATCH0__SCRATCH0_MASK 0xFFFFFFFFL 812 813 814 // addressBlock: uvd0_uvd_jrbc_enc_dec 815 //UVD_JRBC_ENC_RB_WPTR 816 #define UVD_JRBC_ENC_RB_WPTR__RB_WPTR__SHIFT 0x4 817 #define UVD_JRBC_ENC_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L 818 //UVD_JRBC_ENC_RB_CNTL 819 #define UVD_JRBC_ENC_RB_CNTL__RB_NO_FETCH__SHIFT 0x0 820 #define UVD_JRBC_ENC_RB_CNTL__RB_RPTR_WR_EN__SHIFT 0x1 821 #define UVD_JRBC_ENC_RB_CNTL__RB_PRE_WRITE_TIMER__SHIFT 0x4 822 #define UVD_JRBC_ENC_RB_CNTL__RB_NO_FETCH_MASK 0x00000001L 823 #define UVD_JRBC_ENC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x00000002L 824 #define UVD_JRBC_ENC_RB_CNTL__RB_PRE_WRITE_TIMER_MASK 0x0007FFF0L 825 //UVD_JRBC_ENC_IB_SIZE 826 #define UVD_JRBC_ENC_IB_SIZE__IB_SIZE__SHIFT 0x4 827 #define UVD_JRBC_ENC_IB_SIZE__IB_SIZE_MASK 0x007FFFF0L 828 //UVD_JRBC_ENC_URGENT_CNTL 829 #define UVD_JRBC_ENC_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK__SHIFT 0x0 830 #define UVD_JRBC_ENC_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK_MASK 0x00000003L 831 //UVD_JRBC_ENC_RB_REF_DATA 832 #define UVD_JRBC_ENC_RB_REF_DATA__REF_DATA__SHIFT 0x0 833 #define UVD_JRBC_ENC_RB_REF_DATA__REF_DATA_MASK 0xFFFFFFFFL 834 //UVD_JRBC_ENC_RB_COND_RD_TIMER 835 #define UVD_JRBC_ENC_RB_COND_RD_TIMER__RETRY_TIMER_CNT__SHIFT 0x0 836 #define UVD_JRBC_ENC_RB_COND_RD_TIMER__RETRY_INTERVAL_CNT__SHIFT 0x10 837 #define UVD_JRBC_ENC_RB_COND_RD_TIMER__CONTINUOUS_POLL_EN__SHIFT 0x18 838 #define UVD_JRBC_ENC_RB_COND_RD_TIMER__MEM_TIMEOUT_EN__SHIFT 0x19 839 #define UVD_JRBC_ENC_RB_COND_RD_TIMER__RETRY_TIMER_CNT_MASK 0x0000FFFFL 840 #define UVD_JRBC_ENC_RB_COND_RD_TIMER__RETRY_INTERVAL_CNT_MASK 0x00FF0000L 841 #define UVD_JRBC_ENC_RB_COND_RD_TIMER__CONTINUOUS_POLL_EN_MASK 0x01000000L 842 #define UVD_JRBC_ENC_RB_COND_RD_TIMER__MEM_TIMEOUT_EN_MASK 0x02000000L 843 //UVD_JRBC_ENC_SOFT_RESET 844 #define UVD_JRBC_ENC_SOFT_RESET__RESET__SHIFT 0x0 845 #define UVD_JRBC_ENC_SOFT_RESET__SCLK_RESET_STATUS__SHIFT 0x11 846 #define UVD_JRBC_ENC_SOFT_RESET__RESET_MASK 0x00000001L 847 #define UVD_JRBC_ENC_SOFT_RESET__SCLK_RESET_STATUS_MASK 0x00020000L 848 //UVD_JRBC_ENC_STATUS 849 #define UVD_JRBC_ENC_STATUS__RB_JOB_DONE__SHIFT 0x0 850 #define UVD_JRBC_ENC_STATUS__IB_JOB_DONE__SHIFT 0x1 851 #define UVD_JRBC_ENC_STATUS__RB_ILLEGAL_CMD__SHIFT 0x2 852 #define UVD_JRBC_ENC_STATUS__RB_COND_REG_RD_TIMEOUT__SHIFT 0x3 853 #define UVD_JRBC_ENC_STATUS__RB_MEM_WR_TIMEOUT__SHIFT 0x4 854 #define UVD_JRBC_ENC_STATUS__RB_MEM_RD_TIMEOUT__SHIFT 0x5 855 #define UVD_JRBC_ENC_STATUS__IB_ILLEGAL_CMD__SHIFT 0x6 856 #define UVD_JRBC_ENC_STATUS__IB_COND_REG_RD_TIMEOUT__SHIFT 0x7 857 #define UVD_JRBC_ENC_STATUS__IB_MEM_WR_TIMEOUT__SHIFT 0x8 858 #define UVD_JRBC_ENC_STATUS__IB_MEM_RD_TIMEOUT__SHIFT 0x9 859 #define UVD_JRBC_ENC_STATUS__RB_TRAP_STATUS__SHIFT 0xa 860 #define UVD_JRBC_ENC_STATUS__PREEMPT_STATUS__SHIFT 0xb 861 #define UVD_JRBC_ENC_STATUS__IB_TRAP_STATUS__SHIFT 0xc 862 #define UVD_JRBC_ENC_STATUS__INT_EN__SHIFT 0x10 863 #define UVD_JRBC_ENC_STATUS__INT_ACK__SHIFT 0x11 864 #define UVD_JRBC_ENC_STATUS__RB_JOB_DONE_MASK 0x00000001L 865 #define UVD_JRBC_ENC_STATUS__IB_JOB_DONE_MASK 0x00000002L 866 #define UVD_JRBC_ENC_STATUS__RB_ILLEGAL_CMD_MASK 0x00000004L 867 #define UVD_JRBC_ENC_STATUS__RB_COND_REG_RD_TIMEOUT_MASK 0x00000008L 868 #define UVD_JRBC_ENC_STATUS__RB_MEM_WR_TIMEOUT_MASK 0x00000010L 869 #define UVD_JRBC_ENC_STATUS__RB_MEM_RD_TIMEOUT_MASK 0x00000020L 870 #define UVD_JRBC_ENC_STATUS__IB_ILLEGAL_CMD_MASK 0x00000040L 871 #define UVD_JRBC_ENC_STATUS__IB_COND_REG_RD_TIMEOUT_MASK 0x00000080L 872 #define UVD_JRBC_ENC_STATUS__IB_MEM_WR_TIMEOUT_MASK 0x00000100L 873 #define UVD_JRBC_ENC_STATUS__IB_MEM_RD_TIMEOUT_MASK 0x00000200L 874 #define UVD_JRBC_ENC_STATUS__RB_TRAP_STATUS_MASK 0x00000400L 875 #define UVD_JRBC_ENC_STATUS__PREEMPT_STATUS_MASK 0x00000800L 876 #define UVD_JRBC_ENC_STATUS__IB_TRAP_STATUS_MASK 0x00001000L 877 #define UVD_JRBC_ENC_STATUS__INT_EN_MASK 0x00010000L 878 #define UVD_JRBC_ENC_STATUS__INT_ACK_MASK 0x00020000L 879 //UVD_JRBC_ENC_RB_RPTR 880 #define UVD_JRBC_ENC_RB_RPTR__RB_RPTR__SHIFT 0x4 881 #define UVD_JRBC_ENC_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L 882 //UVD_JRBC_ENC_RB_BUF_STATUS 883 #define UVD_JRBC_ENC_RB_BUF_STATUS__RB_BUF_VALID__SHIFT 0x0 884 #define UVD_JRBC_ENC_RB_BUF_STATUS__RB_BUF_RD_ADDR__SHIFT 0x10 885 #define UVD_JRBC_ENC_RB_BUF_STATUS__RB_BUF_WR_ADDR__SHIFT 0x18 886 #define UVD_JRBC_ENC_RB_BUF_STATUS__RB_BUF_VALID_MASK 0x0000FFFFL 887 #define UVD_JRBC_ENC_RB_BUF_STATUS__RB_BUF_RD_ADDR_MASK 0x000F0000L 888 #define UVD_JRBC_ENC_RB_BUF_STATUS__RB_BUF_WR_ADDR_MASK 0x03000000L 889 //UVD_JRBC_ENC_IB_BUF_STATUS 890 #define UVD_JRBC_ENC_IB_BUF_STATUS__IB_BUF_VALID__SHIFT 0x0 891 #define UVD_JRBC_ENC_IB_BUF_STATUS__IB_BUF_RD_ADDR__SHIFT 0x10 892 #define UVD_JRBC_ENC_IB_BUF_STATUS__IB_BUF_WR_ADDR__SHIFT 0x18 893 #define UVD_JRBC_ENC_IB_BUF_STATUS__IB_BUF_VALID_MASK 0x0000FFFFL 894 #define UVD_JRBC_ENC_IB_BUF_STATUS__IB_BUF_RD_ADDR_MASK 0x000F0000L 895 #define UVD_JRBC_ENC_IB_BUF_STATUS__IB_BUF_WR_ADDR_MASK 0x03000000L 896 //UVD_JRBC_ENC_IB_SIZE_UPDATE 897 #define UVD_JRBC_ENC_IB_SIZE_UPDATE__REMAIN_IB_SIZE__SHIFT 0x4 898 #define UVD_JRBC_ENC_IB_SIZE_UPDATE__REMAIN_IB_SIZE_MASK 0x007FFFF0L 899 //UVD_JRBC_ENC_IB_COND_RD_TIMER 900 #define UVD_JRBC_ENC_IB_COND_RD_TIMER__RETRY_TIMER_CNT__SHIFT 0x0 901 #define UVD_JRBC_ENC_IB_COND_RD_TIMER__RETRY_INTERVAL_CNT__SHIFT 0x10 902 #define UVD_JRBC_ENC_IB_COND_RD_TIMER__CONTINUOUS_POLL_EN__SHIFT 0x18 903 #define UVD_JRBC_ENC_IB_COND_RD_TIMER__MEM_TIMEOUT_EN__SHIFT 0x19 904 #define UVD_JRBC_ENC_IB_COND_RD_TIMER__RETRY_TIMER_CNT_MASK 0x0000FFFFL 905 #define UVD_JRBC_ENC_IB_COND_RD_TIMER__RETRY_INTERVAL_CNT_MASK 0x00FF0000L 906 #define UVD_JRBC_ENC_IB_COND_RD_TIMER__CONTINUOUS_POLL_EN_MASK 0x01000000L 907 #define UVD_JRBC_ENC_IB_COND_RD_TIMER__MEM_TIMEOUT_EN_MASK 0x02000000L 908 //UVD_JRBC_ENC_IB_REF_DATA 909 #define UVD_JRBC_ENC_IB_REF_DATA__REF_DATA__SHIFT 0x0 910 #define UVD_JRBC_ENC_IB_REF_DATA__REF_DATA_MASK 0xFFFFFFFFL 911 //UVD_JPEG_ENC_PREEMPT_CMD 912 #define UVD_JPEG_ENC_PREEMPT_CMD__PREEMPT_EN__SHIFT 0x0 913 #define UVD_JPEG_ENC_PREEMPT_CMD__WAIT_JPEG_JOB_DONE__SHIFT 0x1 914 #define UVD_JPEG_ENC_PREEMPT_CMD__PREEMPT_FENCE_CMD__SHIFT 0x2 915 #define UVD_JPEG_ENC_PREEMPT_CMD__PREEMPT_EN_MASK 0x00000001L 916 #define UVD_JPEG_ENC_PREEMPT_CMD__WAIT_JPEG_JOB_DONE_MASK 0x00000002L 917 #define UVD_JPEG_ENC_PREEMPT_CMD__PREEMPT_FENCE_CMD_MASK 0x00000004L 918 //UVD_JPEG_ENC_PREEMPT_FENCE_DATA0 919 #define UVD_JPEG_ENC_PREEMPT_FENCE_DATA0__PREEMPT_FENCE_DATA0__SHIFT 0x0 920 #define UVD_JPEG_ENC_PREEMPT_FENCE_DATA0__PREEMPT_FENCE_DATA0_MASK 0xFFFFFFFFL 921 //UVD_JPEG_ENC_PREEMPT_FENCE_DATA1 922 #define UVD_JPEG_ENC_PREEMPT_FENCE_DATA1__PREEMPT_FENCE_DATA1__SHIFT 0x0 923 #define UVD_JPEG_ENC_PREEMPT_FENCE_DATA1__PREEMPT_FENCE_DATA1_MASK 0xFFFFFFFFL 924 //UVD_JRBC_ENC_RB_SIZE 925 #define UVD_JRBC_ENC_RB_SIZE__RB_SIZE__SHIFT 0x4 926 #define UVD_JRBC_ENC_RB_SIZE__RB_SIZE_MASK 0x00FFFFF0L 927 //UVD_JRBC_ENC_SCRATCH0 928 #define UVD_JRBC_ENC_SCRATCH0__SCRATCH0__SHIFT 0x0 929 #define UVD_JRBC_ENC_SCRATCH0__SCRATCH0_MASK 0xFFFFFFFFL 930 931 932 // addressBlock: uvd0_uvd_jmi_dec 933 //UVD_JMI_CTRL 934 #define UVD_JMI_CTRL__STALL_MC_ARB__SHIFT 0x0 935 #define UVD_JMI_CTRL__MASK_MC_URGENT__SHIFT 0x1 936 #define UVD_JMI_CTRL__ASSERT_MC_URGENT__SHIFT 0x2 937 #define UVD_JMI_CTRL__MC_RD_ARB_WAIT_TIMER__SHIFT 0x8 938 #define UVD_JMI_CTRL__MC_WR_ARB_WAIT_TIMER__SHIFT 0x10 939 #define UVD_JMI_CTRL__CRC_RESET__SHIFT 0x18 940 #define UVD_JMI_CTRL__CRC_SEL__SHIFT 0x19 941 #define UVD_JMI_CTRL__STALL_MC_ARB_MASK 0x00000001L 942 #define UVD_JMI_CTRL__MASK_MC_URGENT_MASK 0x00000002L 943 #define UVD_JMI_CTRL__ASSERT_MC_URGENT_MASK 0x00000004L 944 #define UVD_JMI_CTRL__MC_RD_ARB_WAIT_TIMER_MASK 0x0000FF00L 945 #define UVD_JMI_CTRL__MC_WR_ARB_WAIT_TIMER_MASK 0x00FF0000L 946 #define UVD_JMI_CTRL__CRC_RESET_MASK 0x01000000L 947 #define UVD_JMI_CTRL__CRC_SEL_MASK 0x1E000000L 948 //UVD_LMI_JRBC_CTRL 949 #define UVD_LMI_JRBC_CTRL__ARB_RD_WAIT_EN__SHIFT 0x0 950 #define UVD_LMI_JRBC_CTRL__ARB_WR_WAIT_EN__SHIFT 0x1 951 #define UVD_LMI_JRBC_CTRL__RD_MAX_BURST__SHIFT 0x4 952 #define UVD_LMI_JRBC_CTRL__WR_MAX_BURST__SHIFT 0x8 953 #define UVD_LMI_JRBC_CTRL__RD_SWAP__SHIFT 0x14 954 #define UVD_LMI_JRBC_CTRL__WR_SWAP__SHIFT 0x16 955 #define UVD_LMI_JRBC_CTRL__ARB_RD_WAIT_EN_MASK 0x00000001L 956 #define UVD_LMI_JRBC_CTRL__ARB_WR_WAIT_EN_MASK 0x00000002L 957 #define UVD_LMI_JRBC_CTRL__RD_MAX_BURST_MASK 0x000000F0L 958 #define UVD_LMI_JRBC_CTRL__WR_MAX_BURST_MASK 0x00000F00L 959 #define UVD_LMI_JRBC_CTRL__RD_SWAP_MASK 0x00300000L 960 #define UVD_LMI_JRBC_CTRL__WR_SWAP_MASK 0x00C00000L 961 //UVD_LMI_JPEG_CTRL 962 #define UVD_LMI_JPEG_CTRL__ARB_RD_WAIT_EN__SHIFT 0x0 963 #define UVD_LMI_JPEG_CTRL__ARB_WR_WAIT_EN__SHIFT 0x1 964 #define UVD_LMI_JPEG_CTRL__RD_MAX_BURST__SHIFT 0x4 965 #define UVD_LMI_JPEG_CTRL__WR_MAX_BURST__SHIFT 0x8 966 #define UVD_LMI_JPEG_CTRL__RD_SWAP__SHIFT 0x14 967 #define UVD_LMI_JPEG_CTRL__WR_SWAP__SHIFT 0x16 968 #define UVD_LMI_JPEG_CTRL__ARB_RD_WAIT_EN_MASK 0x00000001L 969 #define UVD_LMI_JPEG_CTRL__ARB_WR_WAIT_EN_MASK 0x00000002L 970 #define UVD_LMI_JPEG_CTRL__RD_MAX_BURST_MASK 0x000000F0L 971 #define UVD_LMI_JPEG_CTRL__WR_MAX_BURST_MASK 0x00000F00L 972 #define UVD_LMI_JPEG_CTRL__RD_SWAP_MASK 0x00300000L 973 #define UVD_LMI_JPEG_CTRL__WR_SWAP_MASK 0x00C00000L 974 //UVD_JMI_EJRBC_CTRL 975 #define UVD_JMI_EJRBC_CTRL__ARB_RD_WAIT_EN__SHIFT 0x0 976 #define UVD_JMI_EJRBC_CTRL__ARB_WR_WAIT_EN__SHIFT 0x1 977 #define UVD_JMI_EJRBC_CTRL__RD_MAX_BURST__SHIFT 0x4 978 #define UVD_JMI_EJRBC_CTRL__WR_MAX_BURST__SHIFT 0x8 979 #define UVD_JMI_EJRBC_CTRL__RD_SWAP__SHIFT 0x14 980 #define UVD_JMI_EJRBC_CTRL__WR_SWAP__SHIFT 0x16 981 #define UVD_JMI_EJRBC_CTRL__ARB_RD_WAIT_EN_MASK 0x00000001L 982 #define UVD_JMI_EJRBC_CTRL__ARB_WR_WAIT_EN_MASK 0x00000002L 983 #define UVD_JMI_EJRBC_CTRL__RD_MAX_BURST_MASK 0x000000F0L 984 #define UVD_JMI_EJRBC_CTRL__WR_MAX_BURST_MASK 0x00000F00L 985 #define UVD_JMI_EJRBC_CTRL__RD_SWAP_MASK 0x00300000L 986 #define UVD_JMI_EJRBC_CTRL__WR_SWAP_MASK 0x00C00000L 987 //UVD_LMI_EJPEG_CTRL 988 #define UVD_LMI_EJPEG_CTRL__ARB_RD_WAIT_EN__SHIFT 0x0 989 #define UVD_LMI_EJPEG_CTRL__ARB_WR_WAIT_EN__SHIFT 0x1 990 #define UVD_LMI_EJPEG_CTRL__RD_MAX_BURST__SHIFT 0x4 991 #define UVD_LMI_EJPEG_CTRL__WR_MAX_BURST__SHIFT 0x8 992 #define UVD_LMI_EJPEG_CTRL__RD_SWAP__SHIFT 0x14 993 #define UVD_LMI_EJPEG_CTRL__WR_SWAP__SHIFT 0x16 994 #define UVD_LMI_EJPEG_CTRL__ARB_RD_WAIT_EN_MASK 0x00000001L 995 #define UVD_LMI_EJPEG_CTRL__ARB_WR_WAIT_EN_MASK 0x00000002L 996 #define UVD_LMI_EJPEG_CTRL__RD_MAX_BURST_MASK 0x000000F0L 997 #define UVD_LMI_EJPEG_CTRL__WR_MAX_BURST_MASK 0x00000F00L 998 #define UVD_LMI_EJPEG_CTRL__RD_SWAP_MASK 0x00300000L 999 #define UVD_LMI_EJPEG_CTRL__WR_SWAP_MASK 0x00C00000L 1000 //UVD_LMI_JRBC_IB_VMID 1001 #define UVD_LMI_JRBC_IB_VMID__IB_WR_VMID__SHIFT 0x0 1002 #define UVD_LMI_JRBC_IB_VMID__IB_RD_VMID__SHIFT 0x4 1003 #define UVD_LMI_JRBC_IB_VMID__MEM_RD_VMID__SHIFT 0x8 1004 #define UVD_LMI_JRBC_IB_VMID__IB_WR_VMID_MASK 0x0000000FL 1005 #define UVD_LMI_JRBC_IB_VMID__IB_RD_VMID_MASK 0x000000F0L 1006 #define UVD_LMI_JRBC_IB_VMID__MEM_RD_VMID_MASK 0x00000F00L 1007 //UVD_LMI_JRBC_RB_VMID 1008 #define UVD_LMI_JRBC_RB_VMID__RB_WR_VMID__SHIFT 0x0 1009 #define UVD_LMI_JRBC_RB_VMID__RB_RD_VMID__SHIFT 0x4 1010 #define UVD_LMI_JRBC_RB_VMID__MEM_RD_VMID__SHIFT 0x8 1011 #define UVD_LMI_JRBC_RB_VMID__RB_WR_VMID_MASK 0x0000000FL 1012 #define UVD_LMI_JRBC_RB_VMID__RB_RD_VMID_MASK 0x000000F0L 1013 #define UVD_LMI_JRBC_RB_VMID__MEM_RD_VMID_MASK 0x00000F00L 1014 //UVD_LMI_JPEG_VMID 1015 #define UVD_LMI_JPEG_VMID__JPEG_RD_VMID__SHIFT 0x0 1016 #define UVD_LMI_JPEG_VMID__JPEG_WR_VMID__SHIFT 0x4 1017 #define UVD_LMI_JPEG_VMID__ATOMIC_USER0_WR_VMID__SHIFT 0x8 1018 #define UVD_LMI_JPEG_VMID__JPEG_RD_VMID_MASK 0x0000000FL 1019 #define UVD_LMI_JPEG_VMID__JPEG_WR_VMID_MASK 0x000000F0L 1020 #define UVD_LMI_JPEG_VMID__ATOMIC_USER0_WR_VMID_MASK 0x00000F00L 1021 //UVD_JMI_ENC_JRBC_IB_VMID 1022 #define UVD_JMI_ENC_JRBC_IB_VMID__IB_WR_VMID__SHIFT 0x0 1023 #define UVD_JMI_ENC_JRBC_IB_VMID__IB_RD_VMID__SHIFT 0x4 1024 #define UVD_JMI_ENC_JRBC_IB_VMID__MEM_RD_VMID__SHIFT 0x8 1025 #define UVD_JMI_ENC_JRBC_IB_VMID__IB_WR_VMID_MASK 0x0000000FL 1026 #define UVD_JMI_ENC_JRBC_IB_VMID__IB_RD_VMID_MASK 0x000000F0L 1027 #define UVD_JMI_ENC_JRBC_IB_VMID__MEM_RD_VMID_MASK 0x00000F00L 1028 //UVD_JMI_ENC_JRBC_RB_VMID 1029 #define UVD_JMI_ENC_JRBC_RB_VMID__RB_WR_VMID__SHIFT 0x0 1030 #define UVD_JMI_ENC_JRBC_RB_VMID__RB_RD_VMID__SHIFT 0x4 1031 #define UVD_JMI_ENC_JRBC_RB_VMID__MEM_RD_VMID__SHIFT 0x8 1032 #define UVD_JMI_ENC_JRBC_RB_VMID__RB_WR_VMID_MASK 0x0000000FL 1033 #define UVD_JMI_ENC_JRBC_RB_VMID__RB_RD_VMID_MASK 0x000000F0L 1034 #define UVD_JMI_ENC_JRBC_RB_VMID__MEM_RD_VMID_MASK 0x00000F00L 1035 //UVD_JMI_ENC_JPEG_VMID 1036 #define UVD_JMI_ENC_JPEG_VMID__PEL_RD_VMID__SHIFT 0x0 1037 #define UVD_JMI_ENC_JPEG_VMID__BS_WR_VMID__SHIFT 0x5 1038 #define UVD_JMI_ENC_JPEG_VMID__SCALAR_RD_VMID__SHIFT 0xa 1039 #define UVD_JMI_ENC_JPEG_VMID__SCALAR_WR_VMID__SHIFT 0xf 1040 #define UVD_JMI_ENC_JPEG_VMID__HUFF_FENCE_VMID__SHIFT 0x13 1041 #define UVD_JMI_ENC_JPEG_VMID__ATOMIC_USER1_WR_VMID__SHIFT 0x17 1042 #define UVD_JMI_ENC_JPEG_VMID__PEL_RD_VMID_MASK 0x0000000FL 1043 #define UVD_JMI_ENC_JPEG_VMID__BS_WR_VMID_MASK 0x000001E0L 1044 #define UVD_JMI_ENC_JPEG_VMID__SCALAR_RD_VMID_MASK 0x00003C00L 1045 #define UVD_JMI_ENC_JPEG_VMID__SCALAR_WR_VMID_MASK 0x00078000L 1046 #define UVD_JMI_ENC_JPEG_VMID__HUFF_FENCE_VMID_MASK 0x00780000L 1047 #define UVD_JMI_ENC_JPEG_VMID__ATOMIC_USER1_WR_VMID_MASK 0x07800000L 1048 //UVD_JMI_PERFMON_CTRL 1049 #define UVD_JMI_PERFMON_CTRL__PERFMON_STATE__SHIFT 0x0 1050 #define UVD_JMI_PERFMON_CTRL__PERFMON_SEL__SHIFT 0x8 1051 #define UVD_JMI_PERFMON_CTRL__PERFMON_STATE_MASK 0x00000003L 1052 #define UVD_JMI_PERFMON_CTRL__PERFMON_SEL_MASK 0x00000F00L 1053 //UVD_JMI_PERFMON_COUNT_LO 1054 #define UVD_JMI_PERFMON_COUNT_LO__PERFMON_COUNT__SHIFT 0x0 1055 #define UVD_JMI_PERFMON_COUNT_LO__PERFMON_COUNT_MASK 0xFFFFFFFFL 1056 //UVD_JMI_PERFMON_COUNT_HI 1057 #define UVD_JMI_PERFMON_COUNT_HI__PERFMON_COUNT__SHIFT 0x0 1058 #define UVD_JMI_PERFMON_COUNT_HI__PERFMON_COUNT_MASK 0x0000FFFFL 1059 //UVD_LMI_JPEG_READ_64BIT_BAR_LOW 1060 #define UVD_LMI_JPEG_READ_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1061 #define UVD_LMI_JPEG_READ_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1062 //UVD_LMI_JPEG_READ_64BIT_BAR_HIGH 1063 #define UVD_LMI_JPEG_READ_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1064 #define UVD_LMI_JPEG_READ_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1065 //UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW 1066 #define UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1067 #define UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1068 //UVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH 1069 #define UVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1070 #define UVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1071 //UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW 1072 #define UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1073 #define UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1074 //UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH 1075 #define UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1076 #define UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1077 //UVD_LMI_JRBC_RB_64BIT_BAR_LOW 1078 #define UVD_LMI_JRBC_RB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1079 #define UVD_LMI_JRBC_RB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1080 //UVD_LMI_JRBC_RB_64BIT_BAR_HIGH 1081 #define UVD_LMI_JRBC_RB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1082 #define UVD_LMI_JRBC_RB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1083 //UVD_LMI_JRBC_IB_64BIT_BAR_LOW 1084 #define UVD_LMI_JRBC_IB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1085 #define UVD_LMI_JRBC_IB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1086 //UVD_LMI_JRBC_IB_64BIT_BAR_HIGH 1087 #define UVD_LMI_JRBC_IB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1088 #define UVD_LMI_JRBC_IB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1089 //UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW 1090 #define UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1091 #define UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1092 //UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH 1093 #define UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1094 #define UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1095 //UVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW 1096 #define UVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1097 #define UVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1098 //UVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH 1099 #define UVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1100 #define UVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1101 //UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW 1102 #define UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1103 #define UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1104 //UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH 1105 #define UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1106 #define UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1107 //UVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_LOW 1108 #define UVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1109 #define UVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1110 //UVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_HIGH 1111 #define UVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1112 #define UVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1113 //UVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_LOW 1114 #define UVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1115 #define UVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1116 //UVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_HIGH 1117 #define UVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1118 #define UVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1119 //UVD_LMI_EJRBC_RB_64BIT_BAR_LOW 1120 #define UVD_LMI_EJRBC_RB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1121 #define UVD_LMI_EJRBC_RB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1122 //UVD_LMI_EJRBC_RB_64BIT_BAR_HIGH 1123 #define UVD_LMI_EJRBC_RB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1124 #define UVD_LMI_EJRBC_RB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1125 //UVD_LMI_EJRBC_IB_64BIT_BAR_LOW 1126 #define UVD_LMI_EJRBC_IB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1127 #define UVD_LMI_EJRBC_IB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1128 //UVD_LMI_EJRBC_IB_64BIT_BAR_HIGH 1129 #define UVD_LMI_EJRBC_IB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1130 #define UVD_LMI_EJRBC_IB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1131 //UVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_LOW 1132 #define UVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1133 #define UVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1134 //UVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_HIGH 1135 #define UVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1136 #define UVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1137 //UVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_LOW 1138 #define UVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1139 #define UVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1140 //UVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_HIGH 1141 #define UVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1142 #define UVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1143 //UVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_LOW 1144 #define UVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1145 #define UVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1146 //UVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_HIGH 1147 #define UVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1148 #define UVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1149 //UVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_LOW 1150 #define UVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1151 #define UVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1152 //UVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_HIGH 1153 #define UVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1154 #define UVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1155 //UVD_LMI_JPEG_PREEMPT_VMID 1156 #define UVD_LMI_JPEG_PREEMPT_VMID__VMID__SHIFT 0x0 1157 #define UVD_LMI_JPEG_PREEMPT_VMID__VMID_MASK 0x0000000FL 1158 //UVD_LMI_ENC_JPEG_PREEMPT_VMID 1159 #define UVD_LMI_ENC_JPEG_PREEMPT_VMID__VMID__SHIFT 0x0 1160 #define UVD_LMI_ENC_JPEG_PREEMPT_VMID__VMID_MASK 0x0000000FL 1161 //UVD_LMI_JPEG2_VMID 1162 #define UVD_LMI_JPEG2_VMID__JPEG2_RD_VMID__SHIFT 0x0 1163 #define UVD_LMI_JPEG2_VMID__JPEG2_WR_VMID__SHIFT 0x4 1164 #define UVD_LMI_JPEG2_VMID__JPEG2_RD_VMID_MASK 0x0000000FL 1165 #define UVD_LMI_JPEG2_VMID__JPEG2_WR_VMID_MASK 0x000000F0L 1166 //UVD_LMI_JPEG2_READ_64BIT_BAR_LOW 1167 #define UVD_LMI_JPEG2_READ_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1168 #define UVD_LMI_JPEG2_READ_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1169 //UVD_LMI_JPEG2_READ_64BIT_BAR_HIGH 1170 #define UVD_LMI_JPEG2_READ_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1171 #define UVD_LMI_JPEG2_READ_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1172 //UVD_LMI_JPEG2_WRITE_64BIT_BAR_LOW 1173 #define UVD_LMI_JPEG2_WRITE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1174 #define UVD_LMI_JPEG2_WRITE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1175 //UVD_LMI_JPEG2_WRITE_64BIT_BAR_HIGH 1176 #define UVD_LMI_JPEG2_WRITE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1177 #define UVD_LMI_JPEG2_WRITE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1178 //UVD_LMI_JPEG_CTRL2 1179 #define UVD_LMI_JPEG_CTRL2__ARB_RD_WAIT_EN__SHIFT 0x0 1180 #define UVD_LMI_JPEG_CTRL2__ARB_WR_WAIT_EN__SHIFT 0x1 1181 #define UVD_LMI_JPEG_CTRL2__RD_MAX_BURST__SHIFT 0x4 1182 #define UVD_LMI_JPEG_CTRL2__WR_MAX_BURST__SHIFT 0x8 1183 #define UVD_LMI_JPEG_CTRL2__RD_SWAP__SHIFT 0x14 1184 #define UVD_LMI_JPEG_CTRL2__WR_SWAP__SHIFT 0x16 1185 #define UVD_LMI_JPEG_CTRL2__ARB_RD_WAIT_EN_MASK 0x00000001L 1186 #define UVD_LMI_JPEG_CTRL2__ARB_WR_WAIT_EN_MASK 0x00000002L 1187 #define UVD_LMI_JPEG_CTRL2__RD_MAX_BURST_MASK 0x000000F0L 1188 #define UVD_LMI_JPEG_CTRL2__WR_MAX_BURST_MASK 0x00000F00L 1189 #define UVD_LMI_JPEG_CTRL2__RD_SWAP_MASK 0x00300000L 1190 #define UVD_LMI_JPEG_CTRL2__WR_SWAP_MASK 0x00C00000L 1191 //UVD_JMI_DEC_SWAP_CNTL 1192 #define UVD_JMI_DEC_SWAP_CNTL__RB_MC_SWAP__SHIFT 0x0 1193 #define UVD_JMI_DEC_SWAP_CNTL__IB_MC_SWAP__SHIFT 0x2 1194 #define UVD_JMI_DEC_SWAP_CNTL__RB_MEM_WR_MC_SWAP__SHIFT 0x4 1195 #define UVD_JMI_DEC_SWAP_CNTL__IB_MEM_WR_MC_SWAP__SHIFT 0x6 1196 #define UVD_JMI_DEC_SWAP_CNTL__RB_MEM_RD_MC_SWAP__SHIFT 0x8 1197 #define UVD_JMI_DEC_SWAP_CNTL__IB_MEM_RD_MC_SWAP__SHIFT 0xa 1198 #define UVD_JMI_DEC_SWAP_CNTL__PREEMPT_WR_MC_SWAP__SHIFT 0xc 1199 #define UVD_JMI_DEC_SWAP_CNTL__JPEG_RD_MC_SWAP__SHIFT 0xe 1200 #define UVD_JMI_DEC_SWAP_CNTL__JPEG_WR_MC_SWAP__SHIFT 0x10 1201 #define UVD_JMI_DEC_SWAP_CNTL__RB_MC_SWAP_MASK 0x00000003L 1202 #define UVD_JMI_DEC_SWAP_CNTL__IB_MC_SWAP_MASK 0x0000000CL 1203 #define UVD_JMI_DEC_SWAP_CNTL__RB_MEM_WR_MC_SWAP_MASK 0x00000030L 1204 #define UVD_JMI_DEC_SWAP_CNTL__IB_MEM_WR_MC_SWAP_MASK 0x000000C0L 1205 #define UVD_JMI_DEC_SWAP_CNTL__RB_MEM_RD_MC_SWAP_MASK 0x00000300L 1206 #define UVD_JMI_DEC_SWAP_CNTL__IB_MEM_RD_MC_SWAP_MASK 0x00000C00L 1207 #define UVD_JMI_DEC_SWAP_CNTL__PREEMPT_WR_MC_SWAP_MASK 0x00003000L 1208 #define UVD_JMI_DEC_SWAP_CNTL__JPEG_RD_MC_SWAP_MASK 0x0000C000L 1209 #define UVD_JMI_DEC_SWAP_CNTL__JPEG_WR_MC_SWAP_MASK 0x00030000L 1210 //UVD_JMI_ENC_SWAP_CNTL 1211 #define UVD_JMI_ENC_SWAP_CNTL__RB_MC_SWAP__SHIFT 0x0 1212 #define UVD_JMI_ENC_SWAP_CNTL__IB_MC_SWAP__SHIFT 0x2 1213 #define UVD_JMI_ENC_SWAP_CNTL__RB_MEM_WR_MC_SWAP__SHIFT 0x4 1214 #define UVD_JMI_ENC_SWAP_CNTL__IB_MEM_WR_MC_SWAP__SHIFT 0x6 1215 #define UVD_JMI_ENC_SWAP_CNTL__RB_MEM_RD_MC_SWAP__SHIFT 0x8 1216 #define UVD_JMI_ENC_SWAP_CNTL__IB_MEM_RD_MC_SWAP__SHIFT 0xa 1217 #define UVD_JMI_ENC_SWAP_CNTL__PREEMPT_WR_MC_SWAP__SHIFT 0xc 1218 #define UVD_JMI_ENC_SWAP_CNTL__PEL_RD_MC_SWAP__SHIFT 0xe 1219 #define UVD_JMI_ENC_SWAP_CNTL__BS_WR_MC_SWAP__SHIFT 0x10 1220 #define UVD_JMI_ENC_SWAP_CNTL__SCALAR_RD_MC_SWAP__SHIFT 0x12 1221 #define UVD_JMI_ENC_SWAP_CNTL__SCALAR_WR_MC_SWAP__SHIFT 0x14 1222 #define UVD_JMI_ENC_SWAP_CNTL__HUFF_FENCE_MC_SWAP__SHIFT 0x16 1223 #define UVD_JMI_ENC_SWAP_CNTL__RB_MC_SWAP_MASK 0x00000003L 1224 #define UVD_JMI_ENC_SWAP_CNTL__IB_MC_SWAP_MASK 0x0000000CL 1225 #define UVD_JMI_ENC_SWAP_CNTL__RB_MEM_WR_MC_SWAP_MASK 0x00000030L 1226 #define UVD_JMI_ENC_SWAP_CNTL__IB_MEM_WR_MC_SWAP_MASK 0x000000C0L 1227 #define UVD_JMI_ENC_SWAP_CNTL__RB_MEM_RD_MC_SWAP_MASK 0x00000300L 1228 #define UVD_JMI_ENC_SWAP_CNTL__IB_MEM_RD_MC_SWAP_MASK 0x00000C00L 1229 #define UVD_JMI_ENC_SWAP_CNTL__PREEMPT_WR_MC_SWAP_MASK 0x00003000L 1230 #define UVD_JMI_ENC_SWAP_CNTL__PEL_RD_MC_SWAP_MASK 0x0000C000L 1231 #define UVD_JMI_ENC_SWAP_CNTL__BS_WR_MC_SWAP_MASK 0x00030000L 1232 #define UVD_JMI_ENC_SWAP_CNTL__SCALAR_RD_MC_SWAP_MASK 0x000C0000L 1233 #define UVD_JMI_ENC_SWAP_CNTL__SCALAR_WR_MC_SWAP_MASK 0x00300000L 1234 #define UVD_JMI_ENC_SWAP_CNTL__HUFF_FENCE_MC_SWAP_MASK 0x00C00000L 1235 //UVD_JMI_CNTL 1236 #define UVD_JMI_CNTL__SOFT_RESET__SHIFT 0x0 1237 #define UVD_JMI_CNTL__MC_RD_REQ_RET_MAX__SHIFT 0x8 1238 #define UVD_JMI_CNTL__SOFT_RESET_MASK 0x00000001L 1239 #define UVD_JMI_CNTL__MC_RD_REQ_RET_MAX_MASK 0x0003FF00L 1240 //UVD_JMI_HUFF_FENCE_64BIT_BAR_LOW 1241 #define UVD_JMI_HUFF_FENCE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1242 #define UVD_JMI_HUFF_FENCE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1243 //UVD_JMI_HUFF_FENCE_64BIT_BAR_HIGH 1244 #define UVD_JMI_HUFF_FENCE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1245 #define UVD_JMI_HUFF_FENCE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1246 //UVD_JMI_DEC_SWAP_CNTL2 1247 #define UVD_JMI_DEC_SWAP_CNTL2__JPEG2_RD_MC_SWAP__SHIFT 0x0 1248 #define UVD_JMI_DEC_SWAP_CNTL2__JPEG2_WR_MC_SWAP__SHIFT 0x2 1249 #define UVD_JMI_DEC_SWAP_CNTL2__JPEG2_RD_MC_SWAP_MASK 0x00000003L 1250 #define UVD_JMI_DEC_SWAP_CNTL2__JPEG2_WR_MC_SWAP_MASK 0x0000000CL 1251 1252 1253 // addressBlock: uvd0_uvd_jpeg_common_dec 1254 //JPEG_SOFT_RESET_STATUS 1255 #define JPEG_SOFT_RESET_STATUS__JPEG_DEC_RESET_STATUS__SHIFT 0x0 1256 #define JPEG_SOFT_RESET_STATUS__JPEG2_DEC_RESET_STATUS__SHIFT 0x1 1257 #define JPEG_SOFT_RESET_STATUS__DJRBC_RESET_STATUS__SHIFT 0x2 1258 #define JPEG_SOFT_RESET_STATUS__JPEG_ENC_RESET_STATUS__SHIFT 0x3 1259 #define JPEG_SOFT_RESET_STATUS__EJRBC_RESET_STATUS__SHIFT 0x4 1260 #define JPEG_SOFT_RESET_STATUS__JMCIF_RESET_STATUS__SHIFT 0x5 1261 #define JPEG_SOFT_RESET_STATUS__JPEG_DEC_RESET_STATUS_MASK 0x00000001L 1262 #define JPEG_SOFT_RESET_STATUS__JPEG2_DEC_RESET_STATUS_MASK 0x00000002L 1263 #define JPEG_SOFT_RESET_STATUS__DJRBC_RESET_STATUS_MASK 0x00000004L 1264 #define JPEG_SOFT_RESET_STATUS__JPEG_ENC_RESET_STATUS_MASK 0x00000008L 1265 #define JPEG_SOFT_RESET_STATUS__EJRBC_RESET_STATUS_MASK 0x00000010L 1266 #define JPEG_SOFT_RESET_STATUS__JMCIF_RESET_STATUS_MASK 0x00000020L 1267 //JPEG_SYS_INT_EN 1268 #define JPEG_SYS_INT_EN__DJPEG_CORE__SHIFT 0x0 1269 #define JPEG_SYS_INT_EN__DJRBC__SHIFT 0x1 1270 #define JPEG_SYS_INT_EN__DJPEG_PF_RPT__SHIFT 0x2 1271 #define JPEG_SYS_INT_EN__EJPEG_PF_RPT__SHIFT 0x3 1272 #define JPEG_SYS_INT_EN__EJPEG_CORE__SHIFT 0x4 1273 #define JPEG_SYS_INT_EN__EJRBC__SHIFT 0x5 1274 #define JPEG_SYS_INT_EN__DJPEG_CORE2__SHIFT 0x6 1275 #define JPEG_SYS_INT_EN__DJPEG_CORE_MASK 0x00000001L 1276 #define JPEG_SYS_INT_EN__DJRBC_MASK 0x00000002L 1277 #define JPEG_SYS_INT_EN__DJPEG_PF_RPT_MASK 0x00000004L 1278 #define JPEG_SYS_INT_EN__EJPEG_PF_RPT_MASK 0x00000008L 1279 #define JPEG_SYS_INT_EN__EJPEG_CORE_MASK 0x00000010L 1280 #define JPEG_SYS_INT_EN__EJRBC_MASK 0x00000020L 1281 #define JPEG_SYS_INT_EN__DJPEG_CORE2_MASK 0x00000040L 1282 //JPEG_SYS_INT_STATUS 1283 #define JPEG_SYS_INT_STATUS__DJPEG_CORE__SHIFT 0x0 1284 #define JPEG_SYS_INT_STATUS__DJRBC__SHIFT 0x1 1285 #define JPEG_SYS_INT_STATUS__DJPEG_PF_RPT__SHIFT 0x2 1286 #define JPEG_SYS_INT_STATUS__EJPEG_PF_RPT__SHIFT 0x3 1287 #define JPEG_SYS_INT_STATUS__EJPEG_CORE__SHIFT 0x4 1288 #define JPEG_SYS_INT_STATUS__EJRBC__SHIFT 0x5 1289 #define JPEG_SYS_INT_STATUS__DJPEG_CORE2__SHIFT 0x6 1290 #define JPEG_SYS_INT_STATUS__DJPEG_CORE_MASK 0x00000001L 1291 #define JPEG_SYS_INT_STATUS__DJRBC_MASK 0x00000002L 1292 #define JPEG_SYS_INT_STATUS__DJPEG_PF_RPT_MASK 0x00000004L 1293 #define JPEG_SYS_INT_STATUS__EJPEG_PF_RPT_MASK 0x00000008L 1294 #define JPEG_SYS_INT_STATUS__EJPEG_CORE_MASK 0x00000010L 1295 #define JPEG_SYS_INT_STATUS__EJRBC_MASK 0x00000020L 1296 #define JPEG_SYS_INT_STATUS__DJPEG_CORE2_MASK 0x00000040L 1297 //JPEG_SYS_INT_ACK 1298 #define JPEG_SYS_INT_ACK__DJPEG_CORE__SHIFT 0x0 1299 #define JPEG_SYS_INT_ACK__DJRBC__SHIFT 0x1 1300 #define JPEG_SYS_INT_ACK__DJPEG_PF_RPT__SHIFT 0x2 1301 #define JPEG_SYS_INT_ACK__EJPEG_PF_RPT__SHIFT 0x3 1302 #define JPEG_SYS_INT_ACK__EJPEG_CORE__SHIFT 0x4 1303 #define JPEG_SYS_INT_ACK__EJRBC__SHIFT 0x5 1304 #define JPEG_SYS_INT_ACK__DJPEG_CORE2__SHIFT 0x6 1305 #define JPEG_SYS_INT_ACK__DJPEG_CORE_MASK 0x00000001L 1306 #define JPEG_SYS_INT_ACK__DJRBC_MASK 0x00000002L 1307 #define JPEG_SYS_INT_ACK__DJPEG_PF_RPT_MASK 0x00000004L 1308 #define JPEG_SYS_INT_ACK__EJPEG_PF_RPT_MASK 0x00000008L 1309 #define JPEG_SYS_INT_ACK__EJPEG_CORE_MASK 0x00000010L 1310 #define JPEG_SYS_INT_ACK__EJRBC_MASK 0x00000020L 1311 #define JPEG_SYS_INT_ACK__DJPEG_CORE2_MASK 0x00000040L 1312 //JPEG_MASTINT_EN 1313 #define JPEG_MASTINT_EN__OVERRUN_RST__SHIFT 0x0 1314 #define JPEG_MASTINT_EN__INT_OVERRUN__SHIFT 0x4 1315 #define JPEG_MASTINT_EN__OVERRUN_RST_MASK 0x00000001L 1316 #define JPEG_MASTINT_EN__INT_OVERRUN_MASK 0x007FFFF0L 1317 //JPEG_IH_CTRL 1318 #define JPEG_IH_CTRL__IH_SOFT_RESET__SHIFT 0x0 1319 #define JPEG_IH_CTRL__IH_STALL_EN__SHIFT 0x1 1320 #define JPEG_IH_CTRL__IH_STATUS_CLEAN__SHIFT 0x2 1321 #define JPEG_IH_CTRL__IH_VMID__SHIFT 0x3 1322 #define JPEG_IH_CTRL__IH_USER_DATA__SHIFT 0x7 1323 #define JPEG_IH_CTRL__IH_RINGID__SHIFT 0x13 1324 #define JPEG_IH_CTRL__IH_SOFT_RESET_MASK 0x00000001L 1325 #define JPEG_IH_CTRL__IH_STALL_EN_MASK 0x00000002L 1326 #define JPEG_IH_CTRL__IH_STATUS_CLEAN_MASK 0x00000004L 1327 #define JPEG_IH_CTRL__IH_VMID_MASK 0x00000078L 1328 #define JPEG_IH_CTRL__IH_USER_DATA_MASK 0x0007FF80L 1329 #define JPEG_IH_CTRL__IH_RINGID_MASK 0x07F80000L 1330 //JRBBM_ARB_CTRL 1331 #define JRBBM_ARB_CTRL__DJRBC_DROP__SHIFT 0x0 1332 #define JRBBM_ARB_CTRL__EJRBC_DROP__SHIFT 0x1 1333 #define JRBBM_ARB_CTRL__SRBM_DROP__SHIFT 0x2 1334 #define JRBBM_ARB_CTRL__DJRBC_DROP_MASK 0x00000001L 1335 #define JRBBM_ARB_CTRL__EJRBC_DROP_MASK 0x00000002L 1336 #define JRBBM_ARB_CTRL__SRBM_DROP_MASK 0x00000004L 1337 1338 1339 // addressBlock: uvd0_uvd_jpeg_common_sclk_dec 1340 //JPEG_CGC_GATE 1341 #define JPEG_CGC_GATE__JPEG_DEC__SHIFT 0x0 1342 #define JPEG_CGC_GATE__JPEG2_DEC__SHIFT 0x1 1343 #define JPEG_CGC_GATE__JPEG_ENC__SHIFT 0x2 1344 #define JPEG_CGC_GATE__JMCIF__SHIFT 0x3 1345 #define JPEG_CGC_GATE__JRBBM__SHIFT 0x4 1346 #define JPEG_CGC_GATE__JPEG_DEC_MASK 0x00000001L 1347 #define JPEG_CGC_GATE__JPEG2_DEC_MASK 0x00000002L 1348 #define JPEG_CGC_GATE__JPEG_ENC_MASK 0x00000004L 1349 #define JPEG_CGC_GATE__JMCIF_MASK 0x00000008L 1350 #define JPEG_CGC_GATE__JRBBM_MASK 0x00000010L 1351 //JPEG_CGC_CTRL 1352 #define JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x0 1353 #define JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x1 1354 #define JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT 0x5 1355 #define JPEG_CGC_CTRL__DYN_OCLK_RAMP_EN__SHIFT 0xa 1356 #define JPEG_CGC_CTRL__DYN_RCLK_RAMP_EN__SHIFT 0xb 1357 #define JPEG_CGC_CTRL__GATER_DIV_ID__SHIFT 0xc 1358 #define JPEG_CGC_CTRL__JPEG_DEC_MODE__SHIFT 0x10 1359 #define JPEG_CGC_CTRL__JPEG2_DEC_MODE__SHIFT 0x11 1360 #define JPEG_CGC_CTRL__JPEG_ENC_MODE__SHIFT 0x12 1361 #define JPEG_CGC_CTRL__JMCIF_MODE__SHIFT 0x13 1362 #define JPEG_CGC_CTRL__JRBBM_MODE__SHIFT 0x14 1363 #define JPEG_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x00000001L 1364 #define JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x0000001EL 1365 #define JPEG_CGC_CTRL__CLK_OFF_DELAY_MASK 0x000003E0L 1366 #define JPEG_CGC_CTRL__DYN_OCLK_RAMP_EN_MASK 0x00000400L 1367 #define JPEG_CGC_CTRL__DYN_RCLK_RAMP_EN_MASK 0x00000800L 1368 #define JPEG_CGC_CTRL__GATER_DIV_ID_MASK 0x00007000L 1369 #define JPEG_CGC_CTRL__JPEG_DEC_MODE_MASK 0x00010000L 1370 #define JPEG_CGC_CTRL__JPEG2_DEC_MODE_MASK 0x00020000L 1371 #define JPEG_CGC_CTRL__JPEG_ENC_MODE_MASK 0x00040000L 1372 #define JPEG_CGC_CTRL__JMCIF_MODE_MASK 0x00080000L 1373 #define JPEG_CGC_CTRL__JRBBM_MODE_MASK 0x00100000L 1374 //JPEG_CGC_STATUS 1375 #define JPEG_CGC_STATUS__JPEG_DEC_VCLK_ACTIVE__SHIFT 0x0 1376 #define JPEG_CGC_STATUS__JPEG_DEC_SCLK_ACTIVE__SHIFT 0x1 1377 #define JPEG_CGC_STATUS__JPEG2_DEC_VCLK_ACTIVE__SHIFT 0x2 1378 #define JPEG_CGC_STATUS__JPEG2_DEC_SCLK_ACTIVE__SHIFT 0x3 1379 #define JPEG_CGC_STATUS__JPEG_ENC_VCLK_ACTIVE__SHIFT 0x4 1380 #define JPEG_CGC_STATUS__JPEG_ENC_SCLK_ACTIVE__SHIFT 0x5 1381 #define JPEG_CGC_STATUS__JMCIF_SCLK_ACTIVE__SHIFT 0x6 1382 #define JPEG_CGC_STATUS__JRBBM_VCLK_ACTIVE__SHIFT 0x7 1383 #define JPEG_CGC_STATUS__JRBBM_SCLK_ACTIVE__SHIFT 0x8 1384 #define JPEG_CGC_STATUS__JPEG_DEC_VCLK_ACTIVE_MASK 0x00000001L 1385 #define JPEG_CGC_STATUS__JPEG_DEC_SCLK_ACTIVE_MASK 0x00000002L 1386 #define JPEG_CGC_STATUS__JPEG2_DEC_VCLK_ACTIVE_MASK 0x00000004L 1387 #define JPEG_CGC_STATUS__JPEG2_DEC_SCLK_ACTIVE_MASK 0x00000008L 1388 #define JPEG_CGC_STATUS__JPEG_ENC_VCLK_ACTIVE_MASK 0x00000010L 1389 #define JPEG_CGC_STATUS__JPEG_ENC_SCLK_ACTIVE_MASK 0x00000020L 1390 #define JPEG_CGC_STATUS__JMCIF_SCLK_ACTIVE_MASK 0x00000040L 1391 #define JPEG_CGC_STATUS__JRBBM_VCLK_ACTIVE_MASK 0x00000080L 1392 #define JPEG_CGC_STATUS__JRBBM_SCLK_ACTIVE_MASK 0x00000100L 1393 //JPEG_COMN_CGC_MEM_CTRL 1394 #define JPEG_COMN_CGC_MEM_CTRL__JMCIF_LS_EN__SHIFT 0x0 1395 #define JPEG_COMN_CGC_MEM_CTRL__JMCIF_DS_EN__SHIFT 0x1 1396 #define JPEG_COMN_CGC_MEM_CTRL__JMCIF_SD_EN__SHIFT 0x2 1397 #define JPEG_COMN_CGC_MEM_CTRL__LS_SET_DELAY__SHIFT 0x10 1398 #define JPEG_COMN_CGC_MEM_CTRL__LS_CLEAR_DELAY__SHIFT 0x14 1399 #define JPEG_COMN_CGC_MEM_CTRL__JMCIF_LS_EN_MASK 0x00000001L 1400 #define JPEG_COMN_CGC_MEM_CTRL__JMCIF_DS_EN_MASK 0x00000002L 1401 #define JPEG_COMN_CGC_MEM_CTRL__JMCIF_SD_EN_MASK 0x00000004L 1402 #define JPEG_COMN_CGC_MEM_CTRL__LS_SET_DELAY_MASK 0x000F0000L 1403 #define JPEG_COMN_CGC_MEM_CTRL__LS_CLEAR_DELAY_MASK 0x00F00000L 1404 //JPEG_DEC_CGC_MEM_CTRL 1405 #define JPEG_DEC_CGC_MEM_CTRL__JPEG_DEC_LS_EN__SHIFT 0x0 1406 #define JPEG_DEC_CGC_MEM_CTRL__JPEG_DEC_DS_EN__SHIFT 0x1 1407 #define JPEG_DEC_CGC_MEM_CTRL__JPEG_DEC_SD_EN__SHIFT 0x2 1408 #define JPEG_DEC_CGC_MEM_CTRL__JPEG_DEC_LS_EN_MASK 0x00000001L 1409 #define JPEG_DEC_CGC_MEM_CTRL__JPEG_DEC_DS_EN_MASK 0x00000002L 1410 #define JPEG_DEC_CGC_MEM_CTRL__JPEG_DEC_SD_EN_MASK 0x00000004L 1411 //JPEG2_DEC_CGC_MEM_CTRL 1412 #define JPEG2_DEC_CGC_MEM_CTRL__JPEG2_DEC_LS_EN__SHIFT 0x0 1413 #define JPEG2_DEC_CGC_MEM_CTRL__JPEG2_DEC_DS_EN__SHIFT 0x1 1414 #define JPEG2_DEC_CGC_MEM_CTRL__JPEG2_DEC_SD_EN__SHIFT 0x2 1415 #define JPEG2_DEC_CGC_MEM_CTRL__JPEG2_DEC_LS_EN_MASK 0x00000001L 1416 #define JPEG2_DEC_CGC_MEM_CTRL__JPEG2_DEC_DS_EN_MASK 0x00000002L 1417 #define JPEG2_DEC_CGC_MEM_CTRL__JPEG2_DEC_SD_EN_MASK 0x00000004L 1418 //JPEG_ENC_CGC_MEM_CTRL 1419 #define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_LS_EN__SHIFT 0x0 1420 #define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_DS_EN__SHIFT 0x1 1421 #define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_SD_EN__SHIFT 0x2 1422 #define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_LS_EN_MASK 0x00000001L 1423 #define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_DS_EN_MASK 0x00000002L 1424 #define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_SD_EN_MASK 0x00000004L 1425 //JPEG_SOFT_RESET2 1426 #define JPEG_SOFT_RESET2__ATOMIC_SOFT_RESET__SHIFT 0x0 1427 #define JPEG_SOFT_RESET2__ATOMIC_SOFT_RESET_MASK 0x00000001L 1428 //JPEG_PERF_BANK_CONF 1429 #define JPEG_PERF_BANK_CONF__RESET__SHIFT 0x0 1430 #define JPEG_PERF_BANK_CONF__PEEK__SHIFT 0x8 1431 #define JPEG_PERF_BANK_CONF__CONCATENATE__SHIFT 0x10 1432 #define JPEG_PERF_BANK_CONF__RESET_MASK 0x0000000FL 1433 #define JPEG_PERF_BANK_CONF__PEEK_MASK 0x00000F00L 1434 #define JPEG_PERF_BANK_CONF__CONCATENATE_MASK 0x00030000L 1435 //JPEG_PERF_BANK_EVENT_SEL 1436 #define JPEG_PERF_BANK_EVENT_SEL__SEL0__SHIFT 0x0 1437 #define JPEG_PERF_BANK_EVENT_SEL__SEL1__SHIFT 0x8 1438 #define JPEG_PERF_BANK_EVENT_SEL__SEL2__SHIFT 0x10 1439 #define JPEG_PERF_BANK_EVENT_SEL__SEL3__SHIFT 0x18 1440 #define JPEG_PERF_BANK_EVENT_SEL__SEL0_MASK 0x000000FFL 1441 #define JPEG_PERF_BANK_EVENT_SEL__SEL1_MASK 0x0000FF00L 1442 #define JPEG_PERF_BANK_EVENT_SEL__SEL2_MASK 0x00FF0000L 1443 #define JPEG_PERF_BANK_EVENT_SEL__SEL3_MASK 0xFF000000L 1444 //JPEG_PERF_BANK_COUNT0 1445 #define JPEG_PERF_BANK_COUNT0__COUNT__SHIFT 0x0 1446 #define JPEG_PERF_BANK_COUNT0__COUNT_MASK 0xFFFFFFFFL 1447 //JPEG_PERF_BANK_COUNT1 1448 #define JPEG_PERF_BANK_COUNT1__COUNT__SHIFT 0x0 1449 #define JPEG_PERF_BANK_COUNT1__COUNT_MASK 0xFFFFFFFFL 1450 //JPEG_PERF_BANK_COUNT2 1451 #define JPEG_PERF_BANK_COUNT2__COUNT__SHIFT 0x0 1452 #define JPEG_PERF_BANK_COUNT2__COUNT_MASK 0xFFFFFFFFL 1453 //JPEG_PERF_BANK_COUNT3 1454 #define JPEG_PERF_BANK_COUNT3__COUNT__SHIFT 0x0 1455 #define JPEG_PERF_BANK_COUNT3__COUNT_MASK 0xFFFFFFFFL 1456 1457 1458 // addressBlock: uvd0_uvd_pg_dec 1459 //UVD_PGFSM_CONFIG 1460 #define UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 0x0 1461 #define UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 0x2 1462 #define UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 0x4 1463 #define UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 0x6 1464 #define UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 0x8 1465 #define UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT 0xa 1466 #define UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT 0xc 1467 #define UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 0xe 1468 #define UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 0x10 1469 #define UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 0x12 1470 #define UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT 0x14 1471 #define UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT 0x16 1472 #define UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG_MASK 0x00000003L 1473 #define UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG_MASK 0x0000000CL 1474 #define UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG_MASK 0x00000030L 1475 #define UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG_MASK 0x000000C0L 1476 #define UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG_MASK 0x00000300L 1477 #define UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG_MASK 0x00000C00L 1478 #define UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG_MASK 0x00003000L 1479 #define UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG_MASK 0x0000C000L 1480 #define UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG_MASK 0x00030000L 1481 #define UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG_MASK 0x000C0000L 1482 #define UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG_MASK 0x00300000L 1483 #define UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG_MASK 0x00C00000L 1484 //UVD_PGFSM_STATUS 1485 #define UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT 0x0 1486 #define UVD_PGFSM_STATUS__UVDU_PWR_STATUS__SHIFT 0x2 1487 #define UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT 0x4 1488 #define UVD_PGFSM_STATUS__UVDC_PWR_STATUS__SHIFT 0x6 1489 #define UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT 0x8 1490 #define UVD_PGFSM_STATUS__UVDIL_PWR_STATUS__SHIFT 0xa 1491 #define UVD_PGFSM_STATUS__UVDIR_PWR_STATUS__SHIFT 0xc 1492 #define UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT 0xe 1493 #define UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT 0x10 1494 #define UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT 0x12 1495 #define UVD_PGFSM_STATUS__UVDW_PWR_STATUS__SHIFT 0x14 1496 #define UVD_PGFSM_STATUS__UVDJ_PWR_STATUS__SHIFT 0x16 1497 #define UVD_PGFSM_STATUS__UVDM_PWR_STATUS_MASK 0x00000003L 1498 #define UVD_PGFSM_STATUS__UVDU_PWR_STATUS_MASK 0x0000000CL 1499 #define UVD_PGFSM_STATUS__UVDF_PWR_STATUS_MASK 0x00000030L 1500 #define UVD_PGFSM_STATUS__UVDC_PWR_STATUS_MASK 0x000000C0L 1501 #define UVD_PGFSM_STATUS__UVDB_PWR_STATUS_MASK 0x00000300L 1502 #define UVD_PGFSM_STATUS__UVDIL_PWR_STATUS_MASK 0x00000C00L 1503 #define UVD_PGFSM_STATUS__UVDIR_PWR_STATUS_MASK 0x00003000L 1504 #define UVD_PGFSM_STATUS__UVDTD_PWR_STATUS_MASK 0x0000C000L 1505 #define UVD_PGFSM_STATUS__UVDTE_PWR_STATUS_MASK 0x00030000L 1506 #define UVD_PGFSM_STATUS__UVDE_PWR_STATUS_MASK 0x000C0000L 1507 #define UVD_PGFSM_STATUS__UVDW_PWR_STATUS_MASK 0x00300000L 1508 #define UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK 0x00C00000L 1509 //UVD_POWER_STATUS 1510 #define UVD_POWER_STATUS__UVD_POWER_STATUS__SHIFT 0x0 1511 #define UVD_POWER_STATUS__UVD_PG_MODE__SHIFT 0x2 1512 #define UVD_POWER_STATUS__UVD_CG_MODE__SHIFT 0x4 1513 #define UVD_POWER_STATUS__UVD_PG_EN__SHIFT 0x8 1514 #define UVD_POWER_STATUS__RBC_SNOOP_DIS__SHIFT 0x9 1515 #define UVD_POWER_STATUS__SW_RB_SNOOP_DIS__SHIFT 0xb 1516 #define UVD_POWER_STATUS__STALL_DPG_POWER_UP__SHIFT 0x1f 1517 #define UVD_POWER_STATUS__UVD_POWER_STATUS_MASK 0x00000003L 1518 #define UVD_POWER_STATUS__UVD_PG_MODE_MASK 0x00000004L 1519 #define UVD_POWER_STATUS__UVD_CG_MODE_MASK 0x00000030L 1520 #define UVD_POWER_STATUS__UVD_PG_EN_MASK 0x00000100L 1521 #define UVD_POWER_STATUS__RBC_SNOOP_DIS_MASK 0x00000200L 1522 #define UVD_POWER_STATUS__SW_RB_SNOOP_DIS_MASK 0x00000800L 1523 #define UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK 0x80000000L 1524 //UVD_PG_IND_INDEX 1525 #define UVD_PG_IND_INDEX__INDEX__SHIFT 0x0 1526 #define UVD_PG_IND_INDEX__INDEX_MASK 0x0000003FL 1527 //UVD_PG_IND_DATA 1528 #define UVD_PG_IND_DATA__DATA__SHIFT 0x0 1529 #define UVD_PG_IND_DATA__DATA_MASK 0xFFFFFFFFL 1530 //CC_UVD_HARVESTING 1531 #define CC_UVD_HARVESTING__MMSCH_DISABLE__SHIFT 0x0 1532 #define CC_UVD_HARVESTING__UVD_DISABLE__SHIFT 0x1 1533 #define CC_UVD_HARVESTING__MMSCH_DISABLE_MASK 0x00000001L 1534 #define CC_UVD_HARVESTING__UVD_DISABLE_MASK 0x00000002L 1535 //UVD_JPEG_POWER_STATUS 1536 #define UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS__SHIFT 0x0 1537 #define UVD_JPEG_POWER_STATUS__JPEG_PG_MODE__SHIFT 0x4 1538 #define UVD_JPEG_POWER_STATUS__JRBC_DEC_SNOOP_DIS__SHIFT 0x8 1539 #define UVD_JPEG_POWER_STATUS__JRBC_ENC_SNOOP_DIS__SHIFT 0x9 1540 #define UVD_JPEG_POWER_STATUS__STALL_JDPG_POWER_UP__SHIFT 0x1f 1541 #define UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK 0x00000001L 1542 #define UVD_JPEG_POWER_STATUS__JPEG_PG_MODE_MASK 0x00000010L 1543 #define UVD_JPEG_POWER_STATUS__JRBC_DEC_SNOOP_DIS_MASK 0x00000100L 1544 #define UVD_JPEG_POWER_STATUS__JRBC_ENC_SNOOP_DIS_MASK 0x00000200L 1545 #define UVD_JPEG_POWER_STATUS__STALL_JDPG_POWER_UP_MASK 0x80000000L 1546 //UVD_DPG_LMA_CTL 1547 #define UVD_DPG_LMA_CTL__READ_WRITE__SHIFT 0x0 1548 #define UVD_DPG_LMA_CTL__MASK_EN__SHIFT 0x1 1549 #define UVD_DPG_LMA_CTL__ADDR_AUTO_INCREMENT__SHIFT 0x2 1550 #define UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT 0x4 1551 #define UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT 0x10 1552 #define UVD_DPG_LMA_CTL__READ_WRITE_MASK 0x00000001L 1553 #define UVD_DPG_LMA_CTL__MASK_EN_MASK 0x00000002L 1554 #define UVD_DPG_LMA_CTL__ADDR_AUTO_INCREMENT_MASK 0x00000004L 1555 #define UVD_DPG_LMA_CTL__SRAM_SEL_MASK 0x00000010L 1556 #define UVD_DPG_LMA_CTL__READ_WRITE_ADDR_MASK 0xFFFF0000L 1557 //UVD_DPG_LMA_DATA 1558 #define UVD_DPG_LMA_DATA__LMA_DATA__SHIFT 0x0 1559 #define UVD_DPG_LMA_DATA__LMA_DATA_MASK 0xFFFFFFFFL 1560 //UVD_DPG_LMA_MASK 1561 #define UVD_DPG_LMA_MASK__LMA_MASK__SHIFT 0x0 1562 #define UVD_DPG_LMA_MASK__LMA_MASK_MASK 0xFFFFFFFFL 1563 //UVD_DPG_PAUSE 1564 #define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ__SHIFT 0x0 1565 #define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK__SHIFT 0x1 1566 #define UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ__SHIFT 0x2 1567 #define UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK__SHIFT 0x3 1568 #define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ_MASK 0x00000001L 1569 #define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK 0x00000002L 1570 #define UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK 0x00000004L 1571 #define UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK 0x00000008L 1572 //UVD_SCRATCH1 1573 #define UVD_SCRATCH1__SCRATCH1_DATA__SHIFT 0x0 1574 #define UVD_SCRATCH1__SCRATCH1_DATA_MASK 0xFFFFFFFFL 1575 //UVD_SCRATCH2 1576 #define UVD_SCRATCH2__SCRATCH2_DATA__SHIFT 0x0 1577 #define UVD_SCRATCH2__SCRATCH2_DATA_MASK 0xFFFFFFFFL 1578 //UVD_SCRATCH3 1579 #define UVD_SCRATCH3__SCRATCH3_DATA__SHIFT 0x0 1580 #define UVD_SCRATCH3__SCRATCH3_DATA_MASK 0xFFFFFFFFL 1581 //UVD_SCRATCH4 1582 #define UVD_SCRATCH4__SCRATCH4_DATA__SHIFT 0x0 1583 #define UVD_SCRATCH4__SCRATCH4_DATA_MASK 0xFFFFFFFFL 1584 //UVD_SCRATCH5 1585 #define UVD_SCRATCH5__SCRATCH5_DATA__SHIFT 0x0 1586 #define UVD_SCRATCH5__SCRATCH5_DATA_MASK 0xFFFFFFFFL 1587 //UVD_SCRATCH6 1588 #define UVD_SCRATCH6__SCRATCH6_DATA__SHIFT 0x0 1589 #define UVD_SCRATCH6__SCRATCH6_DATA_MASK 0xFFFFFFFFL 1590 //UVD_SCRATCH7 1591 #define UVD_SCRATCH7__SCRATCH7_DATA__SHIFT 0x0 1592 #define UVD_SCRATCH7__SCRATCH7_DATA_MASK 0xFFFFFFFFL 1593 //UVD_SCRATCH8 1594 #define UVD_SCRATCH8__SCRATCH8_DATA__SHIFT 0x0 1595 #define UVD_SCRATCH8__SCRATCH8_DATA_MASK 0xFFFFFFFFL 1596 //UVD_SCRATCH9 1597 #define UVD_SCRATCH9__SCRATCH9_DATA__SHIFT 0x0 1598 #define UVD_SCRATCH9__SCRATCH9_DATA_MASK 0xFFFFFFFFL 1599 //UVD_SCRATCH10 1600 #define UVD_SCRATCH10__SCRATCH10_DATA__SHIFT 0x0 1601 #define UVD_SCRATCH10__SCRATCH10_DATA_MASK 0xFFFFFFFFL 1602 //UVD_SCRATCH11 1603 #define UVD_SCRATCH11__SCRATCH11_DATA__SHIFT 0x0 1604 #define UVD_SCRATCH11__SCRATCH11_DATA_MASK 0xFFFFFFFFL 1605 //UVD_SCRATCH12 1606 #define UVD_SCRATCH12__SCRATCH12_DATA__SHIFT 0x0 1607 #define UVD_SCRATCH12__SCRATCH12_DATA_MASK 0xFFFFFFFFL 1608 //UVD_SCRATCH13 1609 #define UVD_SCRATCH13__SCRATCH13_DATA__SHIFT 0x0 1610 #define UVD_SCRATCH13__SCRATCH13_DATA_MASK 0xFFFFFFFFL 1611 //UVD_SCRATCH14 1612 #define UVD_SCRATCH14__SCRATCH14_DATA__SHIFT 0x0 1613 #define UVD_SCRATCH14__SCRATCH14_DATA_MASK 0xFFFFFFFFL 1614 //UVD_FREE_COUNTER_REG 1615 #define UVD_FREE_COUNTER_REG__FREE_COUNTER__SHIFT 0x0 1616 #define UVD_FREE_COUNTER_REG__FREE_COUNTER_MASK 0xFFFFFFFFL 1617 //UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW 1618 #define UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1619 #define UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1620 //UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH 1621 #define UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1622 #define UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1623 //UVD_DPG_VCPU_CACHE_OFFSET0 1624 #define UVD_DPG_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT 0x0 1625 #define UVD_DPG_VCPU_CACHE_OFFSET0__CACHE_OFFSET0_MASK 0x01FFFFFFL 1626 //UVD_DPG_LMI_VCPU_CACHE_VMID 1627 #define UVD_DPG_LMI_VCPU_CACHE_VMID__VCPU_CACHE_VMID__SHIFT 0x0 1628 #define UVD_DPG_LMI_VCPU_CACHE_VMID__VCPU_CACHE_VMID_MASK 0x0000000FL 1629 //UVD_PF_STATUS 1630 #define UVD_PF_STATUS__JPEG_PF_OCCURED__SHIFT 0x0 1631 #define UVD_PF_STATUS__NJ_PF_OCCURED__SHIFT 0x1 1632 #define UVD_PF_STATUS__ENCODER0_PF_OCCURED__SHIFT 0x2 1633 #define UVD_PF_STATUS__ENCODER1_PF_OCCURED__SHIFT 0x3 1634 #define UVD_PF_STATUS__ENCODER2_PF_OCCURED__SHIFT 0x4 1635 #define UVD_PF_STATUS__ENCODER3_PF_OCCURED__SHIFT 0x5 1636 #define UVD_PF_STATUS__ENCODER4_PF_OCCURED__SHIFT 0x6 1637 #define UVD_PF_STATUS__EJPEG_PF_OCCURED__SHIFT 0x7 1638 #define UVD_PF_STATUS__JPEG_PF_CLEAR__SHIFT 0x8 1639 #define UVD_PF_STATUS__NJ_PF_CLEAR__SHIFT 0x9 1640 #define UVD_PF_STATUS__ENCODER0_PF_CLEAR__SHIFT 0xa 1641 #define UVD_PF_STATUS__ENCODER1_PF_CLEAR__SHIFT 0xb 1642 #define UVD_PF_STATUS__ENCODER2_PF_CLEAR__SHIFT 0xc 1643 #define UVD_PF_STATUS__ENCODER3_PF_CLEAR__SHIFT 0xd 1644 #define UVD_PF_STATUS__ENCODER4_PF_CLEAR__SHIFT 0xe 1645 #define UVD_PF_STATUS__EJPEG_PF_CLEAR__SHIFT 0xf 1646 #define UVD_PF_STATUS__NJ_ATM_PF_OCCURED__SHIFT 0x10 1647 #define UVD_PF_STATUS__DJ_ATM_PF_OCCURED__SHIFT 0x11 1648 #define UVD_PF_STATUS__EJ_ATM_PF_OCCURED__SHIFT 0x12 1649 #define UVD_PF_STATUS__JPEG_PF_OCCURED_MASK 0x00000001L 1650 #define UVD_PF_STATUS__NJ_PF_OCCURED_MASK 0x00000002L 1651 #define UVD_PF_STATUS__ENCODER0_PF_OCCURED_MASK 0x00000004L 1652 #define UVD_PF_STATUS__ENCODER1_PF_OCCURED_MASK 0x00000008L 1653 #define UVD_PF_STATUS__ENCODER2_PF_OCCURED_MASK 0x00000010L 1654 #define UVD_PF_STATUS__ENCODER3_PF_OCCURED_MASK 0x00000020L 1655 #define UVD_PF_STATUS__ENCODER4_PF_OCCURED_MASK 0x00000040L 1656 #define UVD_PF_STATUS__EJPEG_PF_OCCURED_MASK 0x00000080L 1657 #define UVD_PF_STATUS__JPEG_PF_CLEAR_MASK 0x00000100L 1658 #define UVD_PF_STATUS__NJ_PF_CLEAR_MASK 0x00000200L 1659 #define UVD_PF_STATUS__ENCODER0_PF_CLEAR_MASK 0x00000400L 1660 #define UVD_PF_STATUS__ENCODER1_PF_CLEAR_MASK 0x00000800L 1661 #define UVD_PF_STATUS__ENCODER2_PF_CLEAR_MASK 0x00001000L 1662 #define UVD_PF_STATUS__ENCODER3_PF_CLEAR_MASK 0x00002000L 1663 #define UVD_PF_STATUS__ENCODER4_PF_CLEAR_MASK 0x00004000L 1664 #define UVD_PF_STATUS__EJPEG_PF_CLEAR_MASK 0x00008000L 1665 #define UVD_PF_STATUS__NJ_ATM_PF_OCCURED_MASK 0x00010000L 1666 #define UVD_PF_STATUS__DJ_ATM_PF_OCCURED_MASK 0x00020000L 1667 #define UVD_PF_STATUS__EJ_ATM_PF_OCCURED_MASK 0x00040000L 1668 //UVD_DPG_CLK_EN_VCPU_REPORT 1669 #define UVD_DPG_CLK_EN_VCPU_REPORT__CLK_EN__SHIFT 0x0 1670 #define UVD_DPG_CLK_EN_VCPU_REPORT__VCPU_REPORT__SHIFT 0x1 1671 #define UVD_DPG_CLK_EN_VCPU_REPORT__CLK_EN_MASK 0x00000001L 1672 #define UVD_DPG_CLK_EN_VCPU_REPORT__VCPU_REPORT_MASK 0x000000FEL 1673 //UVD_GFX8_ADDR_CONFIG 1674 #define UVD_GFX8_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 1675 #define UVD_GFX8_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000070L 1676 //UVD_GFX10_ADDR_CONFIG 1677 #define UVD_GFX10_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 1678 #define UVD_GFX10_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 1679 #define UVD_GFX10_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc 1680 #define UVD_GFX10_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 1681 #define UVD_GFX10_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L 1682 #define UVD_GFX10_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L 1683 #define UVD_GFX10_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L 1684 #define UVD_GFX10_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L 1685 //UVD_GPCNT2_CNTL 1686 #define UVD_GPCNT2_CNTL__CLR__SHIFT 0x0 1687 #define UVD_GPCNT2_CNTL__START__SHIFT 0x1 1688 #define UVD_GPCNT2_CNTL__COUNTUP__SHIFT 0x2 1689 #define UVD_GPCNT2_CNTL__CLR_MASK 0x00000001L 1690 #define UVD_GPCNT2_CNTL__START_MASK 0x00000002L 1691 #define UVD_GPCNT2_CNTL__COUNTUP_MASK 0x00000004L 1692 //UVD_GPCNT2_TARGET_LOWER 1693 #define UVD_GPCNT2_TARGET_LOWER__TARGET__SHIFT 0x0 1694 #define UVD_GPCNT2_TARGET_LOWER__TARGET_MASK 0xFFFFFFFFL 1695 //UVD_GPCNT2_STATUS_LOWER 1696 #define UVD_GPCNT2_STATUS_LOWER__COUNT__SHIFT 0x0 1697 #define UVD_GPCNT2_STATUS_LOWER__COUNT_MASK 0xFFFFFFFFL 1698 //UVD_GPCNT2_TARGET_UPPER 1699 #define UVD_GPCNT2_TARGET_UPPER__TARGET__SHIFT 0x0 1700 #define UVD_GPCNT2_TARGET_UPPER__TARGET_MASK 0x0000FFFFL 1701 //UVD_GPCNT2_STATUS_UPPER 1702 #define UVD_GPCNT2_STATUS_UPPER__COUNT__SHIFT 0x0 1703 #define UVD_GPCNT2_STATUS_UPPER__COUNT_MASK 0x0000FFFFL 1704 //UVD_GPCNT3_CNTL 1705 #define UVD_GPCNT3_CNTL__CLR__SHIFT 0x0 1706 #define UVD_GPCNT3_CNTL__START__SHIFT 0x1 1707 #define UVD_GPCNT3_CNTL__COUNTUP__SHIFT 0x2 1708 #define UVD_GPCNT3_CNTL__FREQ__SHIFT 0x3 1709 #define UVD_GPCNT3_CNTL__DIV__SHIFT 0xa 1710 #define UVD_GPCNT3_CNTL__CLR_MASK 0x00000001L 1711 #define UVD_GPCNT3_CNTL__START_MASK 0x00000002L 1712 #define UVD_GPCNT3_CNTL__COUNTUP_MASK 0x00000004L 1713 #define UVD_GPCNT3_CNTL__FREQ_MASK 0x000003F8L 1714 #define UVD_GPCNT3_CNTL__DIV_MASK 0x0001FC00L 1715 //UVD_GPCNT3_TARGET_LOWER 1716 #define UVD_GPCNT3_TARGET_LOWER__TARGET__SHIFT 0x0 1717 #define UVD_GPCNT3_TARGET_LOWER__TARGET_MASK 0xFFFFFFFFL 1718 //UVD_GPCNT3_STATUS_LOWER 1719 #define UVD_GPCNT3_STATUS_LOWER__COUNT__SHIFT 0x0 1720 #define UVD_GPCNT3_STATUS_LOWER__COUNT_MASK 0xFFFFFFFFL 1721 //UVD_GPCNT3_TARGET_UPPER 1722 #define UVD_GPCNT3_TARGET_UPPER__TARGET__SHIFT 0x0 1723 #define UVD_GPCNT3_TARGET_UPPER__TARGET_MASK 0x0000FFFFL 1724 //UVD_GPCNT3_STATUS_UPPER 1725 #define UVD_GPCNT3_STATUS_UPPER__COUNT__SHIFT 0x0 1726 #define UVD_GPCNT3_STATUS_UPPER__COUNT_MASK 0x0000FFFFL 1727 //UVD_TSC_LOWER 1728 #define UVD_TSC_LOWER__COUNT__SHIFT 0x0 1729 #define UVD_TSC_LOWER__COUNT_MASK 0xFFFFFFFFL 1730 //UVD_TSC_UPPER 1731 #define UVD_TSC_UPPER__COUNT__SHIFT 0x0 1732 #define UVD_TSC_UPPER__COUNT_MASK 0x00FFFFFFL 1733 1734 1735 // addressBlock: uvd0_uvddec 1736 //UVD_SEMA_CNTL 1737 #define UVD_SEMA_CNTL__SEMAPHORE_EN__SHIFT 0x0 1738 #define UVD_SEMA_CNTL__ADVANCED_MODE_DIS__SHIFT 0x1 1739 #define UVD_SEMA_CNTL__SEMAPHORE_EN_MASK 0x00000001L 1740 #define UVD_SEMA_CNTL__ADVANCED_MODE_DIS_MASK 0x00000002L 1741 //UVD_RB_RPTR3 1742 #define UVD_RB_RPTR3__RB_RPTR__SHIFT 0x4 1743 #define UVD_RB_RPTR3__RB_RPTR_MASK 0x007FFFF0L 1744 //UVD_RB_WPTR3 1745 #define UVD_RB_WPTR3__RB_WPTR__SHIFT 0x4 1746 #define UVD_RB_WPTR3__RB_WPTR_MASK 0x007FFFF0L 1747 //UVD_RB_BASE_LO3 1748 #define UVD_RB_BASE_LO3__RB_BASE_LO__SHIFT 0x6 1749 #define UVD_RB_BASE_LO3__RB_BASE_LO_MASK 0xFFFFFFC0L 1750 //UVD_RB_BASE_HI3 1751 #define UVD_RB_BASE_HI3__RB_BASE_HI__SHIFT 0x0 1752 #define UVD_RB_BASE_HI3__RB_BASE_HI_MASK 0xFFFFFFFFL 1753 //UVD_RB_SIZE3 1754 #define UVD_RB_SIZE3__RB_SIZE__SHIFT 0x4 1755 #define UVD_RB_SIZE3__RB_SIZE_MASK 0x007FFFF0L 1756 //UVD_RB_ARB_CTRL 1757 #define UVD_RB_ARB_CTRL__SRBM_DROP__SHIFT 0x0 1758 #define UVD_RB_ARB_CTRL__SRBM_DIS__SHIFT 0x1 1759 #define UVD_RB_ARB_CTRL__VCPU_DROP__SHIFT 0x2 1760 #define UVD_RB_ARB_CTRL__VCPU_DIS__SHIFT 0x3 1761 #define UVD_RB_ARB_CTRL__RBC_DROP__SHIFT 0x4 1762 #define UVD_RB_ARB_CTRL__RBC_DIS__SHIFT 0x5 1763 #define UVD_RB_ARB_CTRL__FWOFLD_DROP__SHIFT 0x6 1764 #define UVD_RB_ARB_CTRL__FWOFLD_DIS__SHIFT 0x7 1765 #define UVD_RB_ARB_CTRL__FAST_PATH_EN__SHIFT 0x8 1766 #define UVD_RB_ARB_CTRL__SRBM_DROP_MASK 0x00000001L 1767 #define UVD_RB_ARB_CTRL__SRBM_DIS_MASK 0x00000002L 1768 #define UVD_RB_ARB_CTRL__VCPU_DROP_MASK 0x00000004L 1769 #define UVD_RB_ARB_CTRL__VCPU_DIS_MASK 0x00000008L 1770 #define UVD_RB_ARB_CTRL__RBC_DROP_MASK 0x00000010L 1771 #define UVD_RB_ARB_CTRL__RBC_DIS_MASK 0x00000020L 1772 #define UVD_RB_ARB_CTRL__FWOFLD_DROP_MASK 0x00000040L 1773 #define UVD_RB_ARB_CTRL__FWOFLD_DIS_MASK 0x00000080L 1774 #define UVD_RB_ARB_CTRL__FAST_PATH_EN_MASK 0x00000100L 1775 //UVD_LMI_LAT_CTRL 1776 #define UVD_LMI_LAT_CTRL__SCALE__SHIFT 0x0 1777 #define UVD_LMI_LAT_CTRL__MAX_START__SHIFT 0x8 1778 #define UVD_LMI_LAT_CTRL__MIN_START__SHIFT 0x9 1779 #define UVD_LMI_LAT_CTRL__AVG_START__SHIFT 0xa 1780 #define UVD_LMI_LAT_CTRL__PERFMON_SYNC__SHIFT 0xb 1781 #define UVD_LMI_LAT_CTRL__SKIP__SHIFT 0x10 1782 #define UVD_LMI_LAT_CTRL__SCALE_MASK 0x000000FFL 1783 #define UVD_LMI_LAT_CTRL__MAX_START_MASK 0x00000100L 1784 #define UVD_LMI_LAT_CTRL__MIN_START_MASK 0x00000200L 1785 #define UVD_LMI_LAT_CTRL__AVG_START_MASK 0x00000400L 1786 #define UVD_LMI_LAT_CTRL__PERFMON_SYNC_MASK 0x00000800L 1787 #define UVD_LMI_LAT_CTRL__SKIP_MASK 0x000F0000L 1788 //UVD_LMI_LAT_CNTR 1789 #define UVD_LMI_LAT_CNTR__MAX_LAT__SHIFT 0x0 1790 #define UVD_LMI_LAT_CNTR__MIN_LAT__SHIFT 0x8 1791 #define UVD_LMI_LAT_CNTR__MAX_LAT_MASK 0x000000FFL 1792 #define UVD_LMI_LAT_CNTR__MIN_LAT_MASK 0x0000FF00L 1793 //UVD_LMI_AVG_LAT_CNTR 1794 #define UVD_LMI_AVG_LAT_CNTR__ENV_LOW__SHIFT 0x0 1795 #define UVD_LMI_AVG_LAT_CNTR__ENV_HIGH__SHIFT 0x8 1796 #define UVD_LMI_AVG_LAT_CNTR__ENV_HIT__SHIFT 0x10 1797 #define UVD_LMI_AVG_LAT_CNTR__ENV_LOW_MASK 0x000000FFL 1798 #define UVD_LMI_AVG_LAT_CNTR__ENV_HIGH_MASK 0x0000FF00L 1799 #define UVD_LMI_AVG_LAT_CNTR__ENV_HIT_MASK 0xFFFF0000L 1800 //UVD_SOFT_RESET2 1801 #define UVD_SOFT_RESET2__ATOMIC_SOFT_RESET__SHIFT 0x0 1802 #define UVD_SOFT_RESET2__MMSCH_VCLK_RESET_STATUS__SHIFT 0x10 1803 #define UVD_SOFT_RESET2__MMSCH_SCLK_RESET_STATUS__SHIFT 0x11 1804 #define UVD_SOFT_RESET2__ATOMIC_SOFT_RESET_MASK 0x00000001L 1805 #define UVD_SOFT_RESET2__MMSCH_VCLK_RESET_STATUS_MASK 0x00010000L 1806 #define UVD_SOFT_RESET2__MMSCH_SCLK_RESET_STATUS_MASK 0x00020000L 1807 //UVD_LMI_SPH 1808 #define UVD_LMI_SPH__ADDR__SHIFT 0x0 1809 #define UVD_LMI_SPH__STS__SHIFT 0x1c 1810 #define UVD_LMI_SPH__STS_VALID__SHIFT 0x1e 1811 #define UVD_LMI_SPH__STS_OVERFLOW__SHIFT 0x1f 1812 #define UVD_LMI_SPH__ADDR_MASK 0x0FFFFFFFL 1813 #define UVD_LMI_SPH__STS_MASK 0x30000000L 1814 #define UVD_LMI_SPH__STS_VALID_MASK 0x40000000L 1815 #define UVD_LMI_SPH__STS_OVERFLOW_MASK 0x80000000L 1816 //UVD_CTX_INDEX 1817 #define UVD_CTX_INDEX__INDEX__SHIFT 0x0 1818 #define UVD_CTX_INDEX__INDEX_MASK 0x000001FFL 1819 //UVD_CTX_DATA 1820 #define UVD_CTX_DATA__DATA__SHIFT 0x0 1821 #define UVD_CTX_DATA__DATA_MASK 0xFFFFFFFFL 1822 //UVD_CGC_GATE 1823 #define UVD_CGC_GATE__SYS__SHIFT 0x0 1824 #define UVD_CGC_GATE__UDEC__SHIFT 0x1 1825 #define UVD_CGC_GATE__MPEG2__SHIFT 0x2 1826 #define UVD_CGC_GATE__REGS__SHIFT 0x3 1827 #define UVD_CGC_GATE__RBC__SHIFT 0x4 1828 #define UVD_CGC_GATE__LMI_MC__SHIFT 0x5 1829 #define UVD_CGC_GATE__LMI_UMC__SHIFT 0x6 1830 #define UVD_CGC_GATE__IDCT__SHIFT 0x7 1831 #define UVD_CGC_GATE__MPRD__SHIFT 0x8 1832 #define UVD_CGC_GATE__MPC__SHIFT 0x9 1833 #define UVD_CGC_GATE__LBSI__SHIFT 0xa 1834 #define UVD_CGC_GATE__LRBBM__SHIFT 0xb 1835 #define UVD_CGC_GATE__UDEC_RE__SHIFT 0xc 1836 #define UVD_CGC_GATE__UDEC_CM__SHIFT 0xd 1837 #define UVD_CGC_GATE__UDEC_IT__SHIFT 0xe 1838 #define UVD_CGC_GATE__UDEC_DB__SHIFT 0xf 1839 #define UVD_CGC_GATE__UDEC_MP__SHIFT 0x10 1840 #define UVD_CGC_GATE__WCB__SHIFT 0x11 1841 #define UVD_CGC_GATE__VCPU__SHIFT 0x12 1842 #define UVD_CGC_GATE__SCPU__SHIFT 0x13 1843 #define UVD_CGC_GATE__MMSCH__SHIFT 0x14 1844 #define UVD_CGC_GATE__SYS_MASK 0x00000001L 1845 #define UVD_CGC_GATE__UDEC_MASK 0x00000002L 1846 #define UVD_CGC_GATE__MPEG2_MASK 0x00000004L 1847 #define UVD_CGC_GATE__REGS_MASK 0x00000008L 1848 #define UVD_CGC_GATE__RBC_MASK 0x00000010L 1849 #define UVD_CGC_GATE__LMI_MC_MASK 0x00000020L 1850 #define UVD_CGC_GATE__LMI_UMC_MASK 0x00000040L 1851 #define UVD_CGC_GATE__IDCT_MASK 0x00000080L 1852 #define UVD_CGC_GATE__MPRD_MASK 0x00000100L 1853 #define UVD_CGC_GATE__MPC_MASK 0x00000200L 1854 #define UVD_CGC_GATE__LBSI_MASK 0x00000400L 1855 #define UVD_CGC_GATE__LRBBM_MASK 0x00000800L 1856 #define UVD_CGC_GATE__UDEC_RE_MASK 0x00001000L 1857 #define UVD_CGC_GATE__UDEC_CM_MASK 0x00002000L 1858 #define UVD_CGC_GATE__UDEC_IT_MASK 0x00004000L 1859 #define UVD_CGC_GATE__UDEC_DB_MASK 0x00008000L 1860 #define UVD_CGC_GATE__UDEC_MP_MASK 0x00010000L 1861 #define UVD_CGC_GATE__WCB_MASK 0x00020000L 1862 #define UVD_CGC_GATE__VCPU_MASK 0x00040000L 1863 #define UVD_CGC_GATE__SCPU_MASK 0x00080000L 1864 #define UVD_CGC_GATE__MMSCH_MASK 0x00100000L 1865 //UVD_CGC_STATUS 1866 #define UVD_CGC_STATUS__SYS_SCLK__SHIFT 0x0 1867 #define UVD_CGC_STATUS__SYS_DCLK__SHIFT 0x1 1868 #define UVD_CGC_STATUS__SYS_VCLK__SHIFT 0x2 1869 #define UVD_CGC_STATUS__UDEC_SCLK__SHIFT 0x3 1870 #define UVD_CGC_STATUS__UDEC_DCLK__SHIFT 0x4 1871 #define UVD_CGC_STATUS__UDEC_VCLK__SHIFT 0x5 1872 #define UVD_CGC_STATUS__MPEG2_SCLK__SHIFT 0x6 1873 #define UVD_CGC_STATUS__MPEG2_DCLK__SHIFT 0x7 1874 #define UVD_CGC_STATUS__MPEG2_VCLK__SHIFT 0x8 1875 #define UVD_CGC_STATUS__REGS_SCLK__SHIFT 0x9 1876 #define UVD_CGC_STATUS__REGS_VCLK__SHIFT 0xa 1877 #define UVD_CGC_STATUS__RBC_SCLK__SHIFT 0xb 1878 #define UVD_CGC_STATUS__LMI_MC_SCLK__SHIFT 0xc 1879 #define UVD_CGC_STATUS__LMI_UMC_SCLK__SHIFT 0xd 1880 #define UVD_CGC_STATUS__IDCT_SCLK__SHIFT 0xe 1881 #define UVD_CGC_STATUS__IDCT_VCLK__SHIFT 0xf 1882 #define UVD_CGC_STATUS__MPRD_SCLK__SHIFT 0x10 1883 #define UVD_CGC_STATUS__MPRD_DCLK__SHIFT 0x11 1884 #define UVD_CGC_STATUS__MPRD_VCLK__SHIFT 0x12 1885 #define UVD_CGC_STATUS__MPC_SCLK__SHIFT 0x13 1886 #define UVD_CGC_STATUS__MPC_DCLK__SHIFT 0x14 1887 #define UVD_CGC_STATUS__LBSI_SCLK__SHIFT 0x15 1888 #define UVD_CGC_STATUS__LBSI_VCLK__SHIFT 0x16 1889 #define UVD_CGC_STATUS__LRBBM_SCLK__SHIFT 0x17 1890 #define UVD_CGC_STATUS__WCB_SCLK__SHIFT 0x18 1891 #define UVD_CGC_STATUS__VCPU_SCLK__SHIFT 0x19 1892 #define UVD_CGC_STATUS__VCPU_VCLK__SHIFT 0x1a 1893 #define UVD_CGC_STATUS__MMSCH_SCLK__SHIFT 0x1b 1894 #define UVD_CGC_STATUS__MMSCH_VCLK__SHIFT 0x1c 1895 #define UVD_CGC_STATUS__ALL_ENC_ACTIVE__SHIFT 0x1d 1896 #define UVD_CGC_STATUS__ALL_DEC_ACTIVE__SHIFT 0x1f 1897 #define UVD_CGC_STATUS__SYS_SCLK_MASK 0x00000001L 1898 #define UVD_CGC_STATUS__SYS_DCLK_MASK 0x00000002L 1899 #define UVD_CGC_STATUS__SYS_VCLK_MASK 0x00000004L 1900 #define UVD_CGC_STATUS__UDEC_SCLK_MASK 0x00000008L 1901 #define UVD_CGC_STATUS__UDEC_DCLK_MASK 0x00000010L 1902 #define UVD_CGC_STATUS__UDEC_VCLK_MASK 0x00000020L 1903 #define UVD_CGC_STATUS__MPEG2_SCLK_MASK 0x00000040L 1904 #define UVD_CGC_STATUS__MPEG2_DCLK_MASK 0x00000080L 1905 #define UVD_CGC_STATUS__MPEG2_VCLK_MASK 0x00000100L 1906 #define UVD_CGC_STATUS__REGS_SCLK_MASK 0x00000200L 1907 #define UVD_CGC_STATUS__REGS_VCLK_MASK 0x00000400L 1908 #define UVD_CGC_STATUS__RBC_SCLK_MASK 0x00000800L 1909 #define UVD_CGC_STATUS__LMI_MC_SCLK_MASK 0x00001000L 1910 #define UVD_CGC_STATUS__LMI_UMC_SCLK_MASK 0x00002000L 1911 #define UVD_CGC_STATUS__IDCT_SCLK_MASK 0x00004000L 1912 #define UVD_CGC_STATUS__IDCT_VCLK_MASK 0x00008000L 1913 #define UVD_CGC_STATUS__MPRD_SCLK_MASK 0x00010000L 1914 #define UVD_CGC_STATUS__MPRD_DCLK_MASK 0x00020000L 1915 #define UVD_CGC_STATUS__MPRD_VCLK_MASK 0x00040000L 1916 #define UVD_CGC_STATUS__MPC_SCLK_MASK 0x00080000L 1917 #define UVD_CGC_STATUS__MPC_DCLK_MASK 0x00100000L 1918 #define UVD_CGC_STATUS__LBSI_SCLK_MASK 0x00200000L 1919 #define UVD_CGC_STATUS__LBSI_VCLK_MASK 0x00400000L 1920 #define UVD_CGC_STATUS__LRBBM_SCLK_MASK 0x00800000L 1921 #define UVD_CGC_STATUS__WCB_SCLK_MASK 0x01000000L 1922 #define UVD_CGC_STATUS__VCPU_SCLK_MASK 0x02000000L 1923 #define UVD_CGC_STATUS__VCPU_VCLK_MASK 0x04000000L 1924 #define UVD_CGC_STATUS__MMSCH_SCLK_MASK 0x08000000L 1925 #define UVD_CGC_STATUS__MMSCH_VCLK_MASK 0x10000000L 1926 #define UVD_CGC_STATUS__ALL_ENC_ACTIVE_MASK 0x20000000L 1927 #define UVD_CGC_STATUS__ALL_DEC_ACTIVE_MASK 0x80000000L 1928 //UVD_CGC_CTRL 1929 #define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x0 1930 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x2 1931 #define UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT 0x6 1932 #define UVD_CGC_CTRL__UDEC_RE_MODE__SHIFT 0xb 1933 #define UVD_CGC_CTRL__UDEC_CM_MODE__SHIFT 0xc 1934 #define UVD_CGC_CTRL__UDEC_IT_MODE__SHIFT 0xd 1935 #define UVD_CGC_CTRL__UDEC_DB_MODE__SHIFT 0xe 1936 #define UVD_CGC_CTRL__UDEC_MP_MODE__SHIFT 0xf 1937 #define UVD_CGC_CTRL__SYS_MODE__SHIFT 0x10 1938 #define UVD_CGC_CTRL__UDEC_MODE__SHIFT 0x11 1939 #define UVD_CGC_CTRL__MPEG2_MODE__SHIFT 0x12 1940 #define UVD_CGC_CTRL__REGS_MODE__SHIFT 0x13 1941 #define UVD_CGC_CTRL__RBC_MODE__SHIFT 0x14 1942 #define UVD_CGC_CTRL__LMI_MC_MODE__SHIFT 0x15 1943 #define UVD_CGC_CTRL__LMI_UMC_MODE__SHIFT 0x16 1944 #define UVD_CGC_CTRL__IDCT_MODE__SHIFT 0x17 1945 #define UVD_CGC_CTRL__MPRD_MODE__SHIFT 0x18 1946 #define UVD_CGC_CTRL__MPC_MODE__SHIFT 0x19 1947 #define UVD_CGC_CTRL__LBSI_MODE__SHIFT 0x1a 1948 #define UVD_CGC_CTRL__LRBBM_MODE__SHIFT 0x1b 1949 #define UVD_CGC_CTRL__WCB_MODE__SHIFT 0x1c 1950 #define UVD_CGC_CTRL__VCPU_MODE__SHIFT 0x1d 1951 #define UVD_CGC_CTRL__SCPU_MODE__SHIFT 0x1e 1952 #define UVD_CGC_CTRL__MMSCH_MODE__SHIFT 0x1f 1953 #define UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x00000001L 1954 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x0000003CL 1955 #define UVD_CGC_CTRL__CLK_OFF_DELAY_MASK 0x000007C0L 1956 #define UVD_CGC_CTRL__UDEC_RE_MODE_MASK 0x00000800L 1957 #define UVD_CGC_CTRL__UDEC_CM_MODE_MASK 0x00001000L 1958 #define UVD_CGC_CTRL__UDEC_IT_MODE_MASK 0x00002000L 1959 #define UVD_CGC_CTRL__UDEC_DB_MODE_MASK 0x00004000L 1960 #define UVD_CGC_CTRL__UDEC_MP_MODE_MASK 0x00008000L 1961 #define UVD_CGC_CTRL__SYS_MODE_MASK 0x00010000L 1962 #define UVD_CGC_CTRL__UDEC_MODE_MASK 0x00020000L 1963 #define UVD_CGC_CTRL__MPEG2_MODE_MASK 0x00040000L 1964 #define UVD_CGC_CTRL__REGS_MODE_MASK 0x00080000L 1965 #define UVD_CGC_CTRL__RBC_MODE_MASK 0x00100000L 1966 #define UVD_CGC_CTRL__LMI_MC_MODE_MASK 0x00200000L 1967 #define UVD_CGC_CTRL__LMI_UMC_MODE_MASK 0x00400000L 1968 #define UVD_CGC_CTRL__IDCT_MODE_MASK 0x00800000L 1969 #define UVD_CGC_CTRL__MPRD_MODE_MASK 0x01000000L 1970 #define UVD_CGC_CTRL__MPC_MODE_MASK 0x02000000L 1971 #define UVD_CGC_CTRL__LBSI_MODE_MASK 0x04000000L 1972 #define UVD_CGC_CTRL__LRBBM_MODE_MASK 0x08000000L 1973 #define UVD_CGC_CTRL__WCB_MODE_MASK 0x10000000L 1974 #define UVD_CGC_CTRL__VCPU_MODE_MASK 0x20000000L 1975 #define UVD_CGC_CTRL__SCPU_MODE_MASK 0x40000000L 1976 #define UVD_CGC_CTRL__MMSCH_MODE_MASK 0x80000000L 1977 //UVD_CGC_UDEC_STATUS 1978 #define UVD_CGC_UDEC_STATUS__RE_SCLK__SHIFT 0x0 1979 #define UVD_CGC_UDEC_STATUS__RE_DCLK__SHIFT 0x1 1980 #define UVD_CGC_UDEC_STATUS__RE_VCLK__SHIFT 0x2 1981 #define UVD_CGC_UDEC_STATUS__CM_SCLK__SHIFT 0x3 1982 #define UVD_CGC_UDEC_STATUS__CM_DCLK__SHIFT 0x4 1983 #define UVD_CGC_UDEC_STATUS__CM_VCLK__SHIFT 0x5 1984 #define UVD_CGC_UDEC_STATUS__IT_SCLK__SHIFT 0x6 1985 #define UVD_CGC_UDEC_STATUS__IT_DCLK__SHIFT 0x7 1986 #define UVD_CGC_UDEC_STATUS__IT_VCLK__SHIFT 0x8 1987 #define UVD_CGC_UDEC_STATUS__DB_SCLK__SHIFT 0x9 1988 #define UVD_CGC_UDEC_STATUS__DB_DCLK__SHIFT 0xa 1989 #define UVD_CGC_UDEC_STATUS__DB_VCLK__SHIFT 0xb 1990 #define UVD_CGC_UDEC_STATUS__MP_SCLK__SHIFT 0xc 1991 #define UVD_CGC_UDEC_STATUS__MP_DCLK__SHIFT 0xd 1992 #define UVD_CGC_UDEC_STATUS__MP_VCLK__SHIFT 0xe 1993 #define UVD_CGC_UDEC_STATUS__RE_SCLK_MASK 0x00000001L 1994 #define UVD_CGC_UDEC_STATUS__RE_DCLK_MASK 0x00000002L 1995 #define UVD_CGC_UDEC_STATUS__RE_VCLK_MASK 0x00000004L 1996 #define UVD_CGC_UDEC_STATUS__CM_SCLK_MASK 0x00000008L 1997 #define UVD_CGC_UDEC_STATUS__CM_DCLK_MASK 0x00000010L 1998 #define UVD_CGC_UDEC_STATUS__CM_VCLK_MASK 0x00000020L 1999 #define UVD_CGC_UDEC_STATUS__IT_SCLK_MASK 0x00000040L 2000 #define UVD_CGC_UDEC_STATUS__IT_DCLK_MASK 0x00000080L 2001 #define UVD_CGC_UDEC_STATUS__IT_VCLK_MASK 0x00000100L 2002 #define UVD_CGC_UDEC_STATUS__DB_SCLK_MASK 0x00000200L 2003 #define UVD_CGC_UDEC_STATUS__DB_DCLK_MASK 0x00000400L 2004 #define UVD_CGC_UDEC_STATUS__DB_VCLK_MASK 0x00000800L 2005 #define UVD_CGC_UDEC_STATUS__MP_SCLK_MASK 0x00001000L 2006 #define UVD_CGC_UDEC_STATUS__MP_DCLK_MASK 0x00002000L 2007 #define UVD_CGC_UDEC_STATUS__MP_VCLK_MASK 0x00004000L 2008 //UVD_CXW_WR_INT_ID 2009 #define UVD_CXW_WR_INT_ID__ID__SHIFT 0x0 2010 #define UVD_CXW_WR_INT_ID__ID_MASK 0x000000FFL 2011 //UVD_CXW_WR_INT_CTX_ID 2012 #define UVD_CXW_WR_INT_CTX_ID__ID__SHIFT 0x0 2013 #define UVD_CXW_WR_INT_CTX_ID__ID_MASK 0x0FFFFFFFL 2014 //UVD_VCPU_INT_ROUTE 2015 #define UVD_VCPU_INT_ROUTE__DRV_FW_MSG__SHIFT 0x0 2016 #define UVD_VCPU_INT_ROUTE__FW_DRV_MSG_ACK__SHIFT 0x1 2017 #define UVD_VCPU_INT_ROUTE__VCPU_GPCOM__SHIFT 0x2 2018 #define UVD_VCPU_INT_ROUTE__DRV_FW_MSG_MASK 0x00000001L 2019 #define UVD_VCPU_INT_ROUTE__FW_DRV_MSG_ACK_MASK 0x00000002L 2020 #define UVD_VCPU_INT_ROUTE__VCPU_GPCOM_MASK 0x00000004L 2021 //UVD_GP_SCRATCH0 2022 #define UVD_GP_SCRATCH0__DATA__SHIFT 0x0 2023 #define UVD_GP_SCRATCH0__DATA_MASK 0xFFFFFFFFL 2024 //UVD_GP_SCRATCH1 2025 #define UVD_GP_SCRATCH1__DATA__SHIFT 0x0 2026 #define UVD_GP_SCRATCH1__DATA_MASK 0xFFFFFFFFL 2027 //UVD_GP_SCRATCH2 2028 #define UVD_GP_SCRATCH2__DATA__SHIFT 0x0 2029 #define UVD_GP_SCRATCH2__DATA_MASK 0xFFFFFFFFL 2030 //UVD_GP_SCRATCH3 2031 #define UVD_GP_SCRATCH3__DATA__SHIFT 0x0 2032 #define UVD_GP_SCRATCH3__DATA_MASK 0xFFFFFFFFL 2033 //UVD_GP_SCRATCH4 2034 #define UVD_GP_SCRATCH4__DATA__SHIFT 0x0 2035 #define UVD_GP_SCRATCH4__DATA_MASK 0xFFFFFFFFL 2036 //UVD_GP_SCRATCH5 2037 #define UVD_GP_SCRATCH5__DATA__SHIFT 0x0 2038 #define UVD_GP_SCRATCH5__DATA_MASK 0xFFFFFFFFL 2039 //UVD_GP_SCRATCH6 2040 #define UVD_GP_SCRATCH6__DATA__SHIFT 0x0 2041 #define UVD_GP_SCRATCH6__DATA_MASK 0xFFFFFFFFL 2042 //UVD_GP_SCRATCH7 2043 #define UVD_GP_SCRATCH7__DATA__SHIFT 0x0 2044 #define UVD_GP_SCRATCH7__DATA_MASK 0xFFFFFFFFL 2045 //UVD_LMI_VCPU_CACHE_VMID 2046 #define UVD_LMI_VCPU_CACHE_VMID__VCPU_CACHE_VMID__SHIFT 0x0 2047 #define UVD_LMI_VCPU_CACHE_VMID__VCPU_CACHE_VMID_MASK 0x0000000FL 2048 //UVD_LMI_CTRL2 2049 #define UVD_LMI_CTRL2__SPH_DIS__SHIFT 0x0 2050 #define UVD_LMI_CTRL2__STALL_ARB__SHIFT 0x1 2051 #define UVD_LMI_CTRL2__ASSERT_UMC_URGENT__SHIFT 0x2 2052 #define UVD_LMI_CTRL2__MASK_UMC_URGENT__SHIFT 0x3 2053 #define UVD_LMI_CTRL2__CRC1_RESET__SHIFT 0x4 2054 #define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS__SHIFT 0x7 2055 #define UVD_LMI_CTRL2__STALL_ARB_UMC__SHIFT 0x8 2056 #define UVD_LMI_CTRL2__MC_READ_ID_SEL__SHIFT 0x9 2057 #define UVD_LMI_CTRL2__MC_WRITE_ID_SEL__SHIFT 0xb 2058 #define UVD_LMI_CTRL2__VCPU_NC0_EXT_EN__SHIFT 0xd 2059 #define UVD_LMI_CTRL2__VCPU_NC1_EXT_EN__SHIFT 0xe 2060 #define UVD_LMI_CTRL2__SPU_EXTRA_CID_EN__SHIFT 0xf 2061 #define UVD_LMI_CTRL2__RE_OFFLOAD_EN__SHIFT 0x10 2062 #define UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT 0x11 2063 #define UVD_LMI_CTRL2__CLEAR_NJ_PF_BP__SHIFT 0x19 2064 #define UVD_LMI_CTRL2__NJ_MIF_GATING__SHIFT 0x1a 2065 #define UVD_LMI_CTRL2__CRC1_SEL__SHIFT 0x1b 2066 #define UVD_LMI_CTRL2__SPH_DIS_MASK 0x00000001L 2067 #define UVD_LMI_CTRL2__STALL_ARB_MASK 0x00000002L 2068 #define UVD_LMI_CTRL2__ASSERT_UMC_URGENT_MASK 0x00000004L 2069 #define UVD_LMI_CTRL2__MASK_UMC_URGENT_MASK 0x00000008L 2070 #define UVD_LMI_CTRL2__CRC1_RESET_MASK 0x00000010L 2071 #define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS_MASK 0x00000080L 2072 #define UVD_LMI_CTRL2__STALL_ARB_UMC_MASK 0x00000100L 2073 #define UVD_LMI_CTRL2__MC_READ_ID_SEL_MASK 0x00000600L 2074 #define UVD_LMI_CTRL2__MC_WRITE_ID_SEL_MASK 0x00001800L 2075 #define UVD_LMI_CTRL2__VCPU_NC0_EXT_EN_MASK 0x00002000L 2076 #define UVD_LMI_CTRL2__VCPU_NC1_EXT_EN_MASK 0x00004000L 2077 #define UVD_LMI_CTRL2__SPU_EXTRA_CID_EN_MASK 0x00008000L 2078 #define UVD_LMI_CTRL2__RE_OFFLOAD_EN_MASK 0x00010000L 2079 #define UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM_MASK 0x01FE0000L 2080 #define UVD_LMI_CTRL2__CLEAR_NJ_PF_BP_MASK 0x02000000L 2081 #define UVD_LMI_CTRL2__NJ_MIF_GATING_MASK 0x04000000L 2082 #define UVD_LMI_CTRL2__CRC1_SEL_MASK 0xF8000000L 2083 //UVD_MASTINT_EN 2084 #define UVD_MASTINT_EN__OVERRUN_RST__SHIFT 0x0 2085 #define UVD_MASTINT_EN__VCPU_EN__SHIFT 0x1 2086 #define UVD_MASTINT_EN__SYS_EN__SHIFT 0x2 2087 #define UVD_MASTINT_EN__INT_OVERRUN__SHIFT 0x4 2088 #define UVD_MASTINT_EN__OVERRUN_RST_MASK 0x00000001L 2089 #define UVD_MASTINT_EN__VCPU_EN_MASK 0x00000002L 2090 #define UVD_MASTINT_EN__SYS_EN_MASK 0x00000004L 2091 #define UVD_MASTINT_EN__INT_OVERRUN_MASK 0x007FFFF0L 2092 //UVD_SYS_INT_EN 2093 #define UVD_SYS_INT_EN__PIF_ADDR_ERR_EN__SHIFT 0x0 2094 #define UVD_SYS_INT_EN__SEMA_WAIT_FAULT_TIMEOUT_EN__SHIFT 0x1 2095 #define UVD_SYS_INT_EN__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_EN__SHIFT 0x2 2096 #define UVD_SYS_INT_EN__CXW_WR_EN__SHIFT 0x3 2097 #define UVD_SYS_INT_EN__RBC_REG_PRIV_FAULT_EN__SHIFT 0x6 2098 #define UVD_SYS_INT_EN__UVD_HOST_CXW_EN__SHIFT 0x8 2099 #define UVD_SYS_INT_EN__LBSI_EN__SHIFT 0xb 2100 #define UVD_SYS_INT_EN__UDEC_EN__SHIFT 0xc 2101 #define UVD_SYS_INT_EN__JOB_DONE_EN__SHIFT 0x10 2102 #define UVD_SYS_INT_EN__WPTR_IDLE_EN__SHIFT 0x15 2103 #define UVD_SYS_INT_EN__RBC_REG_PRIV_FAULT_IDCT_EN__SHIFT 0x16 2104 #define UVD_SYS_INT_EN__SEMA_WAIT_FAIL_SIG_EN__SHIFT 0x17 2105 #define UVD_SYS_INT_EN__IDCT_EN__SHIFT 0x18 2106 #define UVD_SYS_INT_EN__MPRD_EN__SHIFT 0x19 2107 #define UVD_SYS_INT_EN__FCS_EN__SHIFT 0x1a 2108 #define UVD_SYS_INT_EN__CLK_SWT_EN__SHIFT 0x1b 2109 #define UVD_SYS_INT_EN__MIF_HWINT_EN__SHIFT 0x1c 2110 #define UVD_SYS_INT_EN__MPRD_ERR_EN__SHIFT 0x1d 2111 #define UVD_SYS_INT_EN__AVM_INT_EN__SHIFT 0x1f 2112 #define UVD_SYS_INT_EN__PIF_ADDR_ERR_EN_MASK 0x00000001L 2113 #define UVD_SYS_INT_EN__SEMA_WAIT_FAULT_TIMEOUT_EN_MASK 0x00000002L 2114 #define UVD_SYS_INT_EN__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_EN_MASK 0x00000004L 2115 #define UVD_SYS_INT_EN__CXW_WR_EN_MASK 0x00000008L 2116 #define UVD_SYS_INT_EN__RBC_REG_PRIV_FAULT_EN_MASK 0x00000040L 2117 #define UVD_SYS_INT_EN__UVD_HOST_CXW_EN_MASK 0x00000100L 2118 #define UVD_SYS_INT_EN__LBSI_EN_MASK 0x00000800L 2119 #define UVD_SYS_INT_EN__UDEC_EN_MASK 0x00001000L 2120 #define UVD_SYS_INT_EN__JOB_DONE_EN_MASK 0x00010000L 2121 #define UVD_SYS_INT_EN__WPTR_IDLE_EN_MASK 0x00200000L 2122 #define UVD_SYS_INT_EN__RBC_REG_PRIV_FAULT_IDCT_EN_MASK 0x00400000L 2123 #define UVD_SYS_INT_EN__SEMA_WAIT_FAIL_SIG_EN_MASK 0x00800000L 2124 #define UVD_SYS_INT_EN__IDCT_EN_MASK 0x01000000L 2125 #define UVD_SYS_INT_EN__MPRD_EN_MASK 0x02000000L 2126 #define UVD_SYS_INT_EN__FCS_EN_MASK 0x04000000L 2127 #define UVD_SYS_INT_EN__CLK_SWT_EN_MASK 0x08000000L 2128 #define UVD_SYS_INT_EN__MIF_HWINT_EN_MASK 0x10000000L 2129 #define UVD_SYS_INT_EN__MPRD_ERR_EN_MASK 0x20000000L 2130 #define UVD_SYS_INT_EN__AVM_INT_EN_MASK 0x80000000L 2131 //UVD_SYS_INT_STATUS 2132 #define UVD_SYS_INT_STATUS__PIF_ADDR_ERR_INT__SHIFT 0x0 2133 #define UVD_SYS_INT_STATUS__SEMA_WAIT_FAULT_TIMEOUT_INT__SHIFT 0x1 2134 #define UVD_SYS_INT_STATUS__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_INT__SHIFT 0x2 2135 #define UVD_SYS_INT_STATUS__CXW_WR_INT__SHIFT 0x3 2136 #define UVD_SYS_INT_STATUS__RBC_REG_PRIV_FAULT_INT__SHIFT 0x6 2137 #define UVD_SYS_INT_STATUS__UVD_HOST_CXW_INT__SHIFT 0x8 2138 #define UVD_SYS_INT_STATUS__LBSI_INT__SHIFT 0xb 2139 #define UVD_SYS_INT_STATUS__UDEC_INT__SHIFT 0xc 2140 #define UVD_SYS_INT_STATUS__JOB_DONE_INT__SHIFT 0x10 2141 #define UVD_SYS_INT_STATUS__GPCOM_INT__SHIFT 0x12 2142 #define UVD_SYS_INT_STATUS__WPTR_IDLE_INT__SHIFT 0x15 2143 #define UVD_SYS_INT_STATUS__RBC_REG_PRIV_FAULT_IDCT_INT__SHIFT 0x16 2144 #define UVD_SYS_INT_STATUS__SEMA_WAIT_FAIL_SIG_INT__SHIFT 0x17 2145 #define UVD_SYS_INT_STATUS__IDCT_INT__SHIFT 0x18 2146 #define UVD_SYS_INT_STATUS__MPRD_INT__SHIFT 0x19 2147 #define UVD_SYS_INT_STATUS__FCS_INT__SHIFT 0x1a 2148 #define UVD_SYS_INT_STATUS__CLK_SWT_INT__SHIFT 0x1b 2149 #define UVD_SYS_INT_STATUS__MIF_HWINT__SHIFT 0x1c 2150 #define UVD_SYS_INT_STATUS__MPRD_ERR_INT__SHIFT 0x1d 2151 #define UVD_SYS_INT_STATUS__AVM_INT__SHIFT 0x1f 2152 #define UVD_SYS_INT_STATUS__PIF_ADDR_ERR_INT_MASK 0x00000001L 2153 #define UVD_SYS_INT_STATUS__SEMA_WAIT_FAULT_TIMEOUT_INT_MASK 0x00000002L 2154 #define UVD_SYS_INT_STATUS__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_INT_MASK 0x00000004L 2155 #define UVD_SYS_INT_STATUS__CXW_WR_INT_MASK 0x00000008L 2156 #define UVD_SYS_INT_STATUS__RBC_REG_PRIV_FAULT_INT_MASK 0x00000040L 2157 #define UVD_SYS_INT_STATUS__UVD_HOST_CXW_INT_MASK 0x00000100L 2158 #define UVD_SYS_INT_STATUS__LBSI_INT_MASK 0x00000800L 2159 #define UVD_SYS_INT_STATUS__UDEC_INT_MASK 0x00001000L 2160 #define UVD_SYS_INT_STATUS__JOB_DONE_INT_MASK 0x00010000L 2161 #define UVD_SYS_INT_STATUS__GPCOM_INT_MASK 0x00040000L 2162 #define UVD_SYS_INT_STATUS__WPTR_IDLE_INT_MASK 0x00200000L 2163 #define UVD_SYS_INT_STATUS__RBC_REG_PRIV_FAULT_IDCT_INT_MASK 0x00400000L 2164 #define UVD_SYS_INT_STATUS__SEMA_WAIT_FAIL_SIG_INT_MASK 0x00800000L 2165 #define UVD_SYS_INT_STATUS__IDCT_INT_MASK 0x01000000L 2166 #define UVD_SYS_INT_STATUS__MPRD_INT_MASK 0x02000000L 2167 #define UVD_SYS_INT_STATUS__FCS_INT_MASK 0x04000000L 2168 #define UVD_SYS_INT_STATUS__CLK_SWT_INT_MASK 0x08000000L 2169 #define UVD_SYS_INT_STATUS__MIF_HWINT_MASK 0x10000000L 2170 #define UVD_SYS_INT_STATUS__MPRD_ERR_INT_MASK 0x20000000L 2171 #define UVD_SYS_INT_STATUS__AVM_INT_MASK 0x80000000L 2172 //UVD_SYS_INT_ACK 2173 #define UVD_SYS_INT_ACK__PIF_ADDR_ERR_ACK__SHIFT 0x0 2174 #define UVD_SYS_INT_ACK__SEMA_WAIT_FAULT_TIMEOUT_ACK__SHIFT 0x1 2175 #define UVD_SYS_INT_ACK__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_ACK__SHIFT 0x2 2176 #define UVD_SYS_INT_ACK__CXW_WR_ACK__SHIFT 0x3 2177 #define UVD_SYS_INT_ACK__RBC_REG_PRIV_FAULT_ACK__SHIFT 0x6 2178 #define UVD_SYS_INT_ACK__UVD_HOST_CXW_ACK__SHIFT 0x8 2179 #define UVD_SYS_INT_ACK__LBSI_ACK__SHIFT 0xb 2180 #define UVD_SYS_INT_ACK__UDEC_ACK__SHIFT 0xc 2181 #define UVD_SYS_INT_ACK__JOB_DONE_ACK__SHIFT 0x10 2182 #define UVD_SYS_INT_ACK__WPTR_IDLE_ACK__SHIFT 0x15 2183 #define UVD_SYS_INT_ACK__RBC_REG_PRIV_FAULT_IDCT_ACK__SHIFT 0x16 2184 #define UVD_SYS_INT_ACK__SEMA_WAIT_FAIL_SIG_ACK__SHIFT 0x17 2185 #define UVD_SYS_INT_ACK__IDCT_ACK__SHIFT 0x18 2186 #define UVD_SYS_INT_ACK__MPRD_ACK__SHIFT 0x19 2187 #define UVD_SYS_INT_ACK__FCS_ACK__SHIFT 0x1a 2188 #define UVD_SYS_INT_ACK__CLK_SWT_ACK__SHIFT 0x1b 2189 #define UVD_SYS_INT_ACK__MIF_HWINT_ACK__SHIFT 0x1c 2190 #define UVD_SYS_INT_ACK__MPRD_ERR_ACK__SHIFT 0x1d 2191 #define UVD_SYS_INT_ACK__AVM_INT_ACK__SHIFT 0x1f 2192 #define UVD_SYS_INT_ACK__PIF_ADDR_ERR_ACK_MASK 0x00000001L 2193 #define UVD_SYS_INT_ACK__SEMA_WAIT_FAULT_TIMEOUT_ACK_MASK 0x00000002L 2194 #define UVD_SYS_INT_ACK__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_ACK_MASK 0x00000004L 2195 #define UVD_SYS_INT_ACK__CXW_WR_ACK_MASK 0x00000008L 2196 #define UVD_SYS_INT_ACK__RBC_REG_PRIV_FAULT_ACK_MASK 0x00000040L 2197 #define UVD_SYS_INT_ACK__UVD_HOST_CXW_ACK_MASK 0x00000100L 2198 #define UVD_SYS_INT_ACK__LBSI_ACK_MASK 0x00000800L 2199 #define UVD_SYS_INT_ACK__UDEC_ACK_MASK 0x00001000L 2200 #define UVD_SYS_INT_ACK__JOB_DONE_ACK_MASK 0x00010000L 2201 #define UVD_SYS_INT_ACK__WPTR_IDLE_ACK_MASK 0x00200000L 2202 #define UVD_SYS_INT_ACK__RBC_REG_PRIV_FAULT_IDCT_ACK_MASK 0x00400000L 2203 #define UVD_SYS_INT_ACK__SEMA_WAIT_FAIL_SIG_ACK_MASK 0x00800000L 2204 #define UVD_SYS_INT_ACK__IDCT_ACK_MASK 0x01000000L 2205 #define UVD_SYS_INT_ACK__MPRD_ACK_MASK 0x02000000L 2206 #define UVD_SYS_INT_ACK__FCS_ACK_MASK 0x04000000L 2207 #define UVD_SYS_INT_ACK__CLK_SWT_ACK_MASK 0x08000000L 2208 #define UVD_SYS_INT_ACK__MIF_HWINT_ACK_MASK 0x10000000L 2209 #define UVD_SYS_INT_ACK__MPRD_ERR_ACK_MASK 0x20000000L 2210 #define UVD_SYS_INT_ACK__AVM_INT_ACK_MASK 0x80000000L 2211 //UVD_VCPU_INT_EN 2212 #define UVD_VCPU_INT_EN__PIF_ADDR_ERR_EN__SHIFT 0x0 2213 #define UVD_VCPU_INT_EN__SEMA_WAIT_FAULT_TIMEOUT_EN__SHIFT 0x1 2214 #define UVD_VCPU_INT_EN__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_EN__SHIFT 0x2 2215 #define UVD_VCPU_INT_EN__NJ_PF_RPT_EN__SHIFT 0x3 2216 #define UVD_VCPU_INT_EN__SW_RB1_INT_EN__SHIFT 0x4 2217 #define UVD_VCPU_INT_EN__SW_RB2_INT_EN__SHIFT 0x5 2218 #define UVD_VCPU_INT_EN__RBC_REG_PRIV_FAULT_EN__SHIFT 0x6 2219 #define UVD_VCPU_INT_EN__SW_RB3_INT_EN__SHIFT 0x7 2220 #define UVD_VCPU_INT_EN__UVD_HOST_CXW_EN__SHIFT 0x8 2221 #define UVD_VCPU_INT_EN__SW_RB4_INT_EN__SHIFT 0x9 2222 #define UVD_VCPU_INT_EN__SW_RB5_INT_EN__SHIFT 0xa 2223 #define UVD_VCPU_INT_EN__LBSI_EN__SHIFT 0xb 2224 #define UVD_VCPU_INT_EN__UDEC_EN__SHIFT 0xc 2225 #define UVD_VCPU_INT_EN__RPTR_WR_EN__SHIFT 0x10 2226 #define UVD_VCPU_INT_EN__JOB_START_EN__SHIFT 0x11 2227 #define UVD_VCPU_INT_EN__NJ_PF_EN__SHIFT 0x12 2228 #define UVD_VCPU_INT_EN__WPTR_IDLE_EN__SHIFT 0x15 2229 #define UVD_VCPU_INT_EN__RBC_REG_PRIV_FAULT_IDCT_EN__SHIFT 0x16 2230 #define UVD_VCPU_INT_EN__SEMA_WAIT_FAIL_SIG_EN__SHIFT 0x17 2231 #define UVD_VCPU_INT_EN__IDCT_EN__SHIFT 0x18 2232 #define UVD_VCPU_INT_EN__MPRD_EN__SHIFT 0x19 2233 #define UVD_VCPU_INT_EN__AVM_INT_EN__SHIFT 0x1a 2234 #define UVD_VCPU_INT_EN__CLK_SWT_EN__SHIFT 0x1b 2235 #define UVD_VCPU_INT_EN__MIF_HWINT_EN__SHIFT 0x1c 2236 #define UVD_VCPU_INT_EN__MPRD_ERR_EN__SHIFT 0x1d 2237 #define UVD_VCPU_INT_EN__DRV_FW_REQ_EN__SHIFT 0x1e 2238 #define UVD_VCPU_INT_EN__DRV_FW_ACK_EN__SHIFT 0x1f 2239 #define UVD_VCPU_INT_EN__PIF_ADDR_ERR_EN_MASK 0x00000001L 2240 #define UVD_VCPU_INT_EN__SEMA_WAIT_FAULT_TIMEOUT_EN_MASK 0x00000002L 2241 #define UVD_VCPU_INT_EN__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_EN_MASK 0x00000004L 2242 #define UVD_VCPU_INT_EN__NJ_PF_RPT_EN_MASK 0x00000008L 2243 #define UVD_VCPU_INT_EN__SW_RB1_INT_EN_MASK 0x00000010L 2244 #define UVD_VCPU_INT_EN__SW_RB2_INT_EN_MASK 0x00000020L 2245 #define UVD_VCPU_INT_EN__RBC_REG_PRIV_FAULT_EN_MASK 0x00000040L 2246 #define UVD_VCPU_INT_EN__SW_RB3_INT_EN_MASK 0x00000080L 2247 #define UVD_VCPU_INT_EN__UVD_HOST_CXW_EN_MASK 0x00000100L 2248 #define UVD_VCPU_INT_EN__SW_RB4_INT_EN_MASK 0x00000200L 2249 #define UVD_VCPU_INT_EN__SW_RB5_INT_EN_MASK 0x00000400L 2250 #define UVD_VCPU_INT_EN__LBSI_EN_MASK 0x00000800L 2251 #define UVD_VCPU_INT_EN__UDEC_EN_MASK 0x00001000L 2252 #define UVD_VCPU_INT_EN__RPTR_WR_EN_MASK 0x00010000L 2253 #define UVD_VCPU_INT_EN__JOB_START_EN_MASK 0x00020000L 2254 #define UVD_VCPU_INT_EN__NJ_PF_EN_MASK 0x00040000L 2255 #define UVD_VCPU_INT_EN__WPTR_IDLE_EN_MASK 0x00200000L 2256 #define UVD_VCPU_INT_EN__RBC_REG_PRIV_FAULT_IDCT_EN_MASK 0x00400000L 2257 #define UVD_VCPU_INT_EN__SEMA_WAIT_FAIL_SIG_EN_MASK 0x00800000L 2258 #define UVD_VCPU_INT_EN__IDCT_EN_MASK 0x01000000L 2259 #define UVD_VCPU_INT_EN__MPRD_EN_MASK 0x02000000L 2260 #define UVD_VCPU_INT_EN__AVM_INT_EN_MASK 0x04000000L 2261 #define UVD_VCPU_INT_EN__CLK_SWT_EN_MASK 0x08000000L 2262 #define UVD_VCPU_INT_EN__MIF_HWINT_EN_MASK 0x10000000L 2263 #define UVD_VCPU_INT_EN__MPRD_ERR_EN_MASK 0x20000000L 2264 #define UVD_VCPU_INT_EN__DRV_FW_REQ_EN_MASK 0x40000000L 2265 #define UVD_VCPU_INT_EN__DRV_FW_ACK_EN_MASK 0x80000000L 2266 //UVD_VCPU_INT_ACK 2267 #define UVD_VCPU_INT_ACK__PIF_ADDR_ERR_ACK__SHIFT 0x0 2268 #define UVD_VCPU_INT_ACK__SEMA_WAIT_FAULT_TIMEOUT_ACK__SHIFT 0x1 2269 #define UVD_VCPU_INT_ACK__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_ACK__SHIFT 0x2 2270 #define UVD_VCPU_INT_ACK__NJ_PF_RPT_ACK__SHIFT 0x3 2271 #define UVD_VCPU_INT_ACK__SW_RB1_INT_ACK__SHIFT 0x4 2272 #define UVD_VCPU_INT_ACK__SW_RB2_INT_ACK__SHIFT 0x5 2273 #define UVD_VCPU_INT_ACK__RBC_REG_PRIV_FAULT_ACK__SHIFT 0x6 2274 #define UVD_VCPU_INT_ACK__SW_RB3_INT_ACK__SHIFT 0x7 2275 #define UVD_VCPU_INT_ACK__UVD_HOST_CXW_ACK__SHIFT 0x8 2276 #define UVD_VCPU_INT_ACK__SW_RB4_INT_ACK__SHIFT 0x9 2277 #define UVD_VCPU_INT_ACK__SW_RB5_INT_ACK__SHIFT 0xa 2278 #define UVD_VCPU_INT_ACK__LBSI_ACK__SHIFT 0xb 2279 #define UVD_VCPU_INT_ACK__UDEC_ACK__SHIFT 0xc 2280 #define UVD_VCPU_INT_ACK__RPTR_WR_ACK__SHIFT 0x10 2281 #define UVD_VCPU_INT_ACK__JOB_START_ACK__SHIFT 0x11 2282 #define UVD_VCPU_INT_ACK__NJ_PF_ACK__SHIFT 0x12 2283 #define UVD_VCPU_INT_ACK__WPTR_IDLE_ACK__SHIFT 0x15 2284 #define UVD_VCPU_INT_ACK__RBC_REG_PRIV_FAULT_IDCT_ACK__SHIFT 0x16 2285 #define UVD_VCPU_INT_ACK__SEMA_WAIT_FAIL_SIG_ACK__SHIFT 0x17 2286 #define UVD_VCPU_INT_ACK__IDCT_ACK__SHIFT 0x18 2287 #define UVD_VCPU_INT_ACK__MPRD_ACK__SHIFT 0x19 2288 #define UVD_VCPU_INT_ACK__AVM_INT_ACK__SHIFT 0x1a 2289 #define UVD_VCPU_INT_ACK__CLK_SWT_ACK__SHIFT 0x1b 2290 #define UVD_VCPU_INT_ACK__MIF_HWINT_ACK__SHIFT 0x1c 2291 #define UVD_VCPU_INT_ACK__MPRD_ERR_ACK__SHIFT 0x1d 2292 #define UVD_VCPU_INT_ACK__DRV_FW_REQ_ACK__SHIFT 0x1e 2293 #define UVD_VCPU_INT_ACK__DRV_FW_ACK_ACK__SHIFT 0x1f 2294 #define UVD_VCPU_INT_ACK__PIF_ADDR_ERR_ACK_MASK 0x00000001L 2295 #define UVD_VCPU_INT_ACK__SEMA_WAIT_FAULT_TIMEOUT_ACK_MASK 0x00000002L 2296 #define UVD_VCPU_INT_ACK__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_ACK_MASK 0x00000004L 2297 #define UVD_VCPU_INT_ACK__NJ_PF_RPT_ACK_MASK 0x00000008L 2298 #define UVD_VCPU_INT_ACK__SW_RB1_INT_ACK_MASK 0x00000010L 2299 #define UVD_VCPU_INT_ACK__SW_RB2_INT_ACK_MASK 0x00000020L 2300 #define UVD_VCPU_INT_ACK__RBC_REG_PRIV_FAULT_ACK_MASK 0x00000040L 2301 #define UVD_VCPU_INT_ACK__SW_RB3_INT_ACK_MASK 0x00000080L 2302 #define UVD_VCPU_INT_ACK__UVD_HOST_CXW_ACK_MASK 0x00000100L 2303 #define UVD_VCPU_INT_ACK__SW_RB4_INT_ACK_MASK 0x00000200L 2304 #define UVD_VCPU_INT_ACK__SW_RB5_INT_ACK_MASK 0x00000400L 2305 #define UVD_VCPU_INT_ACK__LBSI_ACK_MASK 0x00000800L 2306 #define UVD_VCPU_INT_ACK__UDEC_ACK_MASK 0x00001000L 2307 #define UVD_VCPU_INT_ACK__RPTR_WR_ACK_MASK 0x00010000L 2308 #define UVD_VCPU_INT_ACK__JOB_START_ACK_MASK 0x00020000L 2309 #define UVD_VCPU_INT_ACK__NJ_PF_ACK_MASK 0x00040000L 2310 #define UVD_VCPU_INT_ACK__WPTR_IDLE_ACK_MASK 0x00200000L 2311 #define UVD_VCPU_INT_ACK__RBC_REG_PRIV_FAULT_IDCT_ACK_MASK 0x00400000L 2312 #define UVD_VCPU_INT_ACK__SEMA_WAIT_FAIL_SIG_ACK_MASK 0x00800000L 2313 #define UVD_VCPU_INT_ACK__IDCT_ACK_MASK 0x01000000L 2314 #define UVD_VCPU_INT_ACK__MPRD_ACK_MASK 0x02000000L 2315 #define UVD_VCPU_INT_ACK__AVM_INT_ACK_MASK 0x04000000L 2316 #define UVD_VCPU_INT_ACK__CLK_SWT_ACK_MASK 0x08000000L 2317 #define UVD_VCPU_INT_ACK__MIF_HWINT_ACK_MASK 0x10000000L 2318 #define UVD_VCPU_INT_ACK__MPRD_ERR_ACK_MASK 0x20000000L 2319 #define UVD_VCPU_INT_ACK__DRV_FW_REQ_ACK_MASK 0x40000000L 2320 #define UVD_VCPU_INT_ACK__DRV_FW_ACK_ACK_MASK 0x80000000L 2321 //UVD_TOP_CTRL 2322 #define UVD_TOP_CTRL__STANDARD__SHIFT 0x0 2323 #define UVD_TOP_CTRL__STD_VERSION__SHIFT 0x4 2324 #define UVD_TOP_CTRL__STANDARD_MASK 0x0000000FL 2325 #define UVD_TOP_CTRL__STD_VERSION_MASK 0x000000F0L 2326 //UVD_ENC_VCPU_INT_EN 2327 #define UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR_EN__SHIFT 0x0 2328 #define UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR2_EN__SHIFT 0x1 2329 #define UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR3_EN__SHIFT 0x2 2330 #define UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR_EN_MASK 0x00000001L 2331 #define UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR2_EN_MASK 0x00000002L 2332 #define UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR3_EN_MASK 0x00000004L 2333 //UVD_ENC_VCPU_INT_ACK 2334 #define UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR_ACK__SHIFT 0x0 2335 #define UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR2_ACK__SHIFT 0x1 2336 #define UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR3_ACK__SHIFT 0x2 2337 #define UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR_ACK_MASK 0x00000001L 2338 #define UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR2_ACK_MASK 0x00000002L 2339 #define UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR3_ACK_MASK 0x00000004L 2340 //UVD_LMI_VCPU_CACHE_VMIDS_MULTI 2341 #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE1_VMID__SHIFT 0x0 2342 #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE2_VMID__SHIFT 0x4 2343 #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE3_VMID__SHIFT 0x8 2344 #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE4_VMID__SHIFT 0xc 2345 #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE5_VMID__SHIFT 0x10 2346 #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE6_VMID__SHIFT 0x14 2347 #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE7_VMID__SHIFT 0x18 2348 #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE8_VMID__SHIFT 0x1c 2349 #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE1_VMID_MASK 0x0000000FL 2350 #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE2_VMID_MASK 0x000000F0L 2351 #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE3_VMID_MASK 0x00000F00L 2352 #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE4_VMID_MASK 0x0000F000L 2353 #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE5_VMID_MASK 0x000F0000L 2354 #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE6_VMID_MASK 0x00F00000L 2355 #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE7_VMID_MASK 0x0F000000L 2356 #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE8_VMID_MASK 0xF0000000L 2357 //UVD_LMI_VCPU_NC_VMIDS_MULTI 2358 #define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC2_VMID__SHIFT 0x4 2359 #define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC3_VMID__SHIFT 0x8 2360 #define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC4_VMID__SHIFT 0xc 2361 #define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC5_VMID__SHIFT 0x10 2362 #define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC6_VMID__SHIFT 0x14 2363 #define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC7_VMID__SHIFT 0x18 2364 #define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC2_VMID_MASK 0x000000F0L 2365 #define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC3_VMID_MASK 0x00000F00L 2366 #define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC4_VMID_MASK 0x0000F000L 2367 #define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC5_VMID_MASK 0x000F0000L 2368 #define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC6_VMID_MASK 0x00F00000L 2369 #define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC7_VMID_MASK 0x0F000000L 2370 //UVD_LMI_URGENT_CTRL 2371 #define UVD_LMI_URGENT_CTRL__ENABLE_MC_RD_URGENT_STALL__SHIFT 0x0 2372 #define UVD_LMI_URGENT_CTRL__ASSERT_MC_RD_STALL__SHIFT 0x1 2373 #define UVD_LMI_URGENT_CTRL__ASSERT_MC_RD_URGENT__SHIFT 0x2 2374 #define UVD_LMI_URGENT_CTRL__ENABLE_MC_WR_URGENT_STALL__SHIFT 0x8 2375 #define UVD_LMI_URGENT_CTRL__ASSERT_MC_WR_STALL__SHIFT 0x9 2376 #define UVD_LMI_URGENT_CTRL__ASSERT_MC_WR_URGENT__SHIFT 0xa 2377 #define UVD_LMI_URGENT_CTRL__ENABLE_UMC_RD_URGENT_STALL__SHIFT 0x10 2378 #define UVD_LMI_URGENT_CTRL__ASSERT_UMC_RD_STALL__SHIFT 0x11 2379 #define UVD_LMI_URGENT_CTRL__ASSERT_UMC_RD_URGENT__SHIFT 0x12 2380 #define UVD_LMI_URGENT_CTRL__ENABLE_UMC_WR_URGENT_STALL__SHIFT 0x18 2381 #define UVD_LMI_URGENT_CTRL__ASSERT_UMC_WR_STALL__SHIFT 0x19 2382 #define UVD_LMI_URGENT_CTRL__ASSERT_UMC_WR_URGENT__SHIFT 0x1a 2383 #define UVD_LMI_URGENT_CTRL__ENABLE_MC_RD_URGENT_STALL_MASK 0x00000001L 2384 #define UVD_LMI_URGENT_CTRL__ASSERT_MC_RD_STALL_MASK 0x00000002L 2385 #define UVD_LMI_URGENT_CTRL__ASSERT_MC_RD_URGENT_MASK 0x0000003CL 2386 #define UVD_LMI_URGENT_CTRL__ENABLE_MC_WR_URGENT_STALL_MASK 0x00000100L 2387 #define UVD_LMI_URGENT_CTRL__ASSERT_MC_WR_STALL_MASK 0x00000200L 2388 #define UVD_LMI_URGENT_CTRL__ASSERT_MC_WR_URGENT_MASK 0x00003C00L 2389 #define UVD_LMI_URGENT_CTRL__ENABLE_UMC_RD_URGENT_STALL_MASK 0x00010000L 2390 #define UVD_LMI_URGENT_CTRL__ASSERT_UMC_RD_STALL_MASK 0x00020000L 2391 #define UVD_LMI_URGENT_CTRL__ASSERT_UMC_RD_URGENT_MASK 0x003C0000L 2392 #define UVD_LMI_URGENT_CTRL__ENABLE_UMC_WR_URGENT_STALL_MASK 0x01000000L 2393 #define UVD_LMI_URGENT_CTRL__ASSERT_UMC_WR_STALL_MASK 0x02000000L 2394 #define UVD_LMI_URGENT_CTRL__ASSERT_UMC_WR_URGENT_MASK 0x3C000000L 2395 //UVD_LMI_CTRL 2396 #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT 0x0 2397 #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN__SHIFT 0x8 2398 #define UVD_LMI_CTRL__REQ_MODE__SHIFT 0x9 2399 #define UVD_LMI_CTRL__ASSERT_MC_URGENT__SHIFT 0xb 2400 #define UVD_LMI_CTRL__MASK_MC_URGENT__SHIFT 0xc 2401 #define UVD_LMI_CTRL__DATA_COHERENCY_EN__SHIFT 0xd 2402 #define UVD_LMI_CTRL__CRC_RESET__SHIFT 0xe 2403 #define UVD_LMI_CTRL__CRC_SEL__SHIFT 0xf 2404 #define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN__SHIFT 0x15 2405 #define UVD_LMI_CTRL__CM_DATA_COHERENCY_EN__SHIFT 0x16 2406 #define UVD_LMI_CTRL__DB_DB_DATA_COHERENCY_EN__SHIFT 0x17 2407 #define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN__SHIFT 0x18 2408 #define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN__SHIFT 0x19 2409 #define UVD_LMI_CTRL__MIF_MIF_DATA_COHERENCY_EN__SHIFT 0x1a 2410 #define UVD_LMI_CTRL__MIF_LESS_OUTSTANDING_RD_REQ__SHIFT 0x1b 2411 #define UVD_LMI_CTRL__RFU__SHIFT 0x1c 2412 #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_MASK 0x000000FFL 2413 #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK 0x00000100L 2414 #define UVD_LMI_CTRL__REQ_MODE_MASK 0x00000200L 2415 #define UVD_LMI_CTRL__ASSERT_MC_URGENT_MASK 0x00000800L 2416 #define UVD_LMI_CTRL__MASK_MC_URGENT_MASK 0x00001000L 2417 #define UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK 0x00002000L 2418 #define UVD_LMI_CTRL__CRC_RESET_MASK 0x00004000L 2419 #define UVD_LMI_CTRL__CRC_SEL_MASK 0x000F8000L 2420 #define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK 0x00200000L 2421 #define UVD_LMI_CTRL__CM_DATA_COHERENCY_EN_MASK 0x00400000L 2422 #define UVD_LMI_CTRL__DB_DB_DATA_COHERENCY_EN_MASK 0x00800000L 2423 #define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN_MASK 0x01000000L 2424 #define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN_MASK 0x02000000L 2425 #define UVD_LMI_CTRL__MIF_MIF_DATA_COHERENCY_EN_MASK 0x04000000L 2426 #define UVD_LMI_CTRL__MIF_LESS_OUTSTANDING_RD_REQ_MASK 0x08000000L 2427 #define UVD_LMI_CTRL__RFU_MASK 0xF0000000L 2428 //UVD_LMI_STATUS 2429 #define UVD_LMI_STATUS__READ_CLEAN__SHIFT 0x0 2430 #define UVD_LMI_STATUS__WRITE_CLEAN__SHIFT 0x1 2431 #define UVD_LMI_STATUS__WRITE_CLEAN_RAW__SHIFT 0x2 2432 #define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN__SHIFT 0x3 2433 #define UVD_LMI_STATUS__UMC_READ_CLEAN__SHIFT 0x4 2434 #define UVD_LMI_STATUS__UMC_WRITE_CLEAN__SHIFT 0x5 2435 #define UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW__SHIFT 0x6 2436 #define UVD_LMI_STATUS__PENDING_UVD_MC_WRITE__SHIFT 0x7 2437 #define UVD_LMI_STATUS__READ_CLEAN_RAW__SHIFT 0x8 2438 #define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW__SHIFT 0x9 2439 #define UVD_LMI_STATUS__UMC_UVD_IDLE__SHIFT 0xa 2440 #define UVD_LMI_STATUS__UMC_AVP_IDLE__SHIFT 0xb 2441 #define UVD_LMI_STATUS__ADP_MC_READ_CLEAN__SHIFT 0xc 2442 #define UVD_LMI_STATUS__ADP_UMC_READ_CLEAN__SHIFT 0xd 2443 #define UVD_LMI_STATUS__BSP0_WRITE_CLEAN__SHIFT 0x12 2444 #define UVD_LMI_STATUS__BSP1_WRITE_CLEAN__SHIFT 0x13 2445 #define UVD_LMI_STATUS__BSP2_WRITE_CLEAN__SHIFT 0x14 2446 #define UVD_LMI_STATUS__BSP3_WRITE_CLEAN__SHIFT 0x15 2447 #define UVD_LMI_STATUS__CENC_READ_CLEAN__SHIFT 0x16 2448 #define UVD_LMI_STATUS__READ_CLEAN_MASK 0x00000001L 2449 #define UVD_LMI_STATUS__WRITE_CLEAN_MASK 0x00000002L 2450 #define UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK 0x00000004L 2451 #define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK 0x00000008L 2452 #define UVD_LMI_STATUS__UMC_READ_CLEAN_MASK 0x00000010L 2453 #define UVD_LMI_STATUS__UMC_WRITE_CLEAN_MASK 0x00000020L 2454 #define UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK 0x00000040L 2455 #define UVD_LMI_STATUS__PENDING_UVD_MC_WRITE_MASK 0x00000080L 2456 #define UVD_LMI_STATUS__READ_CLEAN_RAW_MASK 0x00000100L 2457 #define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK 0x00000200L 2458 #define UVD_LMI_STATUS__UMC_UVD_IDLE_MASK 0x00000400L 2459 #define UVD_LMI_STATUS__UMC_AVP_IDLE_MASK 0x00000800L 2460 #define UVD_LMI_STATUS__ADP_MC_READ_CLEAN_MASK 0x00001000L 2461 #define UVD_LMI_STATUS__ADP_UMC_READ_CLEAN_MASK 0x00002000L 2462 #define UVD_LMI_STATUS__BSP0_WRITE_CLEAN_MASK 0x00040000L 2463 #define UVD_LMI_STATUS__BSP1_WRITE_CLEAN_MASK 0x00080000L 2464 #define UVD_LMI_STATUS__BSP2_WRITE_CLEAN_MASK 0x00100000L 2465 #define UVD_LMI_STATUS__BSP3_WRITE_CLEAN_MASK 0x00200000L 2466 #define UVD_LMI_STATUS__CENC_READ_CLEAN_MASK 0x00400000L 2467 //UVD_LMI_VM_CTRL 2468 #define UVD_LMI_VM_CTRL__VCPU_VM__SHIFT 0x0 2469 #define UVD_LMI_VM_CTRL__CM_VM__SHIFT 0x1 2470 #define UVD_LMI_VM_CTRL__IT_VM__SHIFT 0x2 2471 #define UVD_LMI_VM_CTRL__MP_VM__SHIFT 0x3 2472 #define UVD_LMI_VM_CTRL__DB_VM__SHIFT 0x4 2473 #define UVD_LMI_VM_CTRL__RB_VM__SHIFT 0x5 2474 #define UVD_LMI_VM_CTRL__IB_VM__SHIFT 0x6 2475 #define UVD_LMI_VM_CTRL__CSM_VM__SHIFT 0x7 2476 #define UVD_LMI_VM_CTRL__RB_WR_VM__SHIFT 0x8 2477 #define UVD_LMI_VM_CTRL__DBW_VM__SHIFT 0xa 2478 #define UVD_LMI_VM_CTRL__RB_RPTR_VM__SHIFT 0xb 2479 #define UVD_LMI_VM_CTRL__RE_VM__SHIFT 0xc 2480 #define UVD_LMI_VM_CTRL__SCPU_VM__SHIFT 0xd 2481 #define UVD_LMI_VM_CTRL__ACAP_VM__SHIFT 0xe 2482 #define UVD_LMI_VM_CTRL__VCPU_VM_MASK 0x00000001L 2483 #define UVD_LMI_VM_CTRL__CM_VM_MASK 0x00000002L 2484 #define UVD_LMI_VM_CTRL__IT_VM_MASK 0x00000004L 2485 #define UVD_LMI_VM_CTRL__MP_VM_MASK 0x00000008L 2486 #define UVD_LMI_VM_CTRL__DB_VM_MASK 0x00000010L 2487 #define UVD_LMI_VM_CTRL__RB_VM_MASK 0x00000020L 2488 #define UVD_LMI_VM_CTRL__IB_VM_MASK 0x00000040L 2489 #define UVD_LMI_VM_CTRL__CSM_VM_MASK 0x00000080L 2490 #define UVD_LMI_VM_CTRL__RB_WR_VM_MASK 0x00000100L 2491 #define UVD_LMI_VM_CTRL__DBW_VM_MASK 0x00000400L 2492 #define UVD_LMI_VM_CTRL__RB_RPTR_VM_MASK 0x00000800L 2493 #define UVD_LMI_VM_CTRL__RE_VM_MASK 0x00001000L 2494 #define UVD_LMI_VM_CTRL__SCPU_VM_MASK 0x00002000L 2495 #define UVD_LMI_VM_CTRL__ACAP_VM_MASK 0x00004000L 2496 //UVD_LMI_PERFMON_CTRL 2497 #define UVD_LMI_PERFMON_CTRL__PERFMON_STATE__SHIFT 0x0 2498 #define UVD_LMI_PERFMON_CTRL__PERFMON_SEL__SHIFT 0x8 2499 #define UVD_LMI_PERFMON_CTRL__PERFMON_STATE_MASK 0x00000003L 2500 #define UVD_LMI_PERFMON_CTRL__PERFMON_SEL_MASK 0x00001F00L 2501 //UVD_LMI_PERFMON_COUNT_LO 2502 #define UVD_LMI_PERFMON_COUNT_LO__PERFMON_COUNT__SHIFT 0x0 2503 #define UVD_LMI_PERFMON_COUNT_LO__PERFMON_COUNT_MASK 0xFFFFFFFFL 2504 //UVD_LMI_PERFMON_COUNT_HI 2505 #define UVD_LMI_PERFMON_COUNT_HI__PERFMON_COUNT__SHIFT 0x0 2506 #define UVD_LMI_PERFMON_COUNT_HI__PERFMON_COUNT_MASK 0x0000FFFFL 2507 //UVD_LMI_SWAP_CNTL 2508 #define UVD_LMI_SWAP_CNTL__RB_MC_SWAP__SHIFT 0x0 2509 #define UVD_LMI_SWAP_CNTL__IB_MC_SWAP__SHIFT 0x2 2510 #define UVD_LMI_SWAP_CNTL__RB_RPTR_MC_SWAP__SHIFT 0x4 2511 #define UVD_LMI_SWAP_CNTL__VCPU_R_MC_SWAP__SHIFT 0x6 2512 #define UVD_LMI_SWAP_CNTL__VCPU_W_MC_SWAP__SHIFT 0x8 2513 #define UVD_LMI_SWAP_CNTL__CM_MC_SWAP__SHIFT 0xa 2514 #define UVD_LMI_SWAP_CNTL__IT_MC_SWAP__SHIFT 0xc 2515 #define UVD_LMI_SWAP_CNTL__DB_R_MC_SWAP__SHIFT 0xe 2516 #define UVD_LMI_SWAP_CNTL__DB_W_MC_SWAP__SHIFT 0x10 2517 #define UVD_LMI_SWAP_CNTL__CSM_MC_SWAP__SHIFT 0x12 2518 #define UVD_LMI_SWAP_CNTL__ACAP_MC_SWAP__SHIFT 0x14 2519 #define UVD_LMI_SWAP_CNTL__MP_REF16_MC_SWAP__SHIFT 0x16 2520 #define UVD_LMI_SWAP_CNTL__DBW_MC_SWAP__SHIFT 0x18 2521 #define UVD_LMI_SWAP_CNTL__RB_WR_MC_SWAP__SHIFT 0x1a 2522 #define UVD_LMI_SWAP_CNTL__RE_MC_SWAP__SHIFT 0x1c 2523 #define UVD_LMI_SWAP_CNTL__MP_MC_SWAP__SHIFT 0x1e 2524 #define UVD_LMI_SWAP_CNTL__RB_MC_SWAP_MASK 0x00000003L 2525 #define UVD_LMI_SWAP_CNTL__IB_MC_SWAP_MASK 0x0000000CL 2526 #define UVD_LMI_SWAP_CNTL__RB_RPTR_MC_SWAP_MASK 0x00000030L 2527 #define UVD_LMI_SWAP_CNTL__VCPU_R_MC_SWAP_MASK 0x000000C0L 2528 #define UVD_LMI_SWAP_CNTL__VCPU_W_MC_SWAP_MASK 0x00000300L 2529 #define UVD_LMI_SWAP_CNTL__CM_MC_SWAP_MASK 0x00000C00L 2530 #define UVD_LMI_SWAP_CNTL__IT_MC_SWAP_MASK 0x00003000L 2531 #define UVD_LMI_SWAP_CNTL__DB_R_MC_SWAP_MASK 0x0000C000L 2532 #define UVD_LMI_SWAP_CNTL__DB_W_MC_SWAP_MASK 0x00030000L 2533 #define UVD_LMI_SWAP_CNTL__CSM_MC_SWAP_MASK 0x000C0000L 2534 #define UVD_LMI_SWAP_CNTL__ACAP_MC_SWAP_MASK 0x00300000L 2535 #define UVD_LMI_SWAP_CNTL__MP_REF16_MC_SWAP_MASK 0x00C00000L 2536 #define UVD_LMI_SWAP_CNTL__DBW_MC_SWAP_MASK 0x03000000L 2537 #define UVD_LMI_SWAP_CNTL__RB_WR_MC_SWAP_MASK 0x0C000000L 2538 #define UVD_LMI_SWAP_CNTL__RE_MC_SWAP_MASK 0x30000000L 2539 #define UVD_LMI_SWAP_CNTL__MP_MC_SWAP_MASK 0xC0000000L 2540 //UVD_UDEC_ADR 2541 #define UVD_UDEC_ADR__SYNC_RE__SHIFT 0x7 2542 #define UVD_UDEC_ADR__SYNC_RE_MASK 0x00000080L 2543 //UVD_MP_SWAP_CNTL 2544 #define UVD_MP_SWAP_CNTL__MP_REF0_MC_SWAP__SHIFT 0x0 2545 #define UVD_MP_SWAP_CNTL__MP_REF1_MC_SWAP__SHIFT 0x2 2546 #define UVD_MP_SWAP_CNTL__MP_REF2_MC_SWAP__SHIFT 0x4 2547 #define UVD_MP_SWAP_CNTL__MP_REF3_MC_SWAP__SHIFT 0x6 2548 #define UVD_MP_SWAP_CNTL__MP_REF4_MC_SWAP__SHIFT 0x8 2549 #define UVD_MP_SWAP_CNTL__MP_REF5_MC_SWAP__SHIFT 0xa 2550 #define UVD_MP_SWAP_CNTL__MP_REF6_MC_SWAP__SHIFT 0xc 2551 #define UVD_MP_SWAP_CNTL__MP_REF7_MC_SWAP__SHIFT 0xe 2552 #define UVD_MP_SWAP_CNTL__MP_REF8_MC_SWAP__SHIFT 0x10 2553 #define UVD_MP_SWAP_CNTL__MP_REF9_MC_SWAP__SHIFT 0x12 2554 #define UVD_MP_SWAP_CNTL__MP_REF10_MC_SWAP__SHIFT 0x14 2555 #define UVD_MP_SWAP_CNTL__MP_REF11_MC_SWAP__SHIFT 0x16 2556 #define UVD_MP_SWAP_CNTL__MP_REF12_MC_SWAP__SHIFT 0x18 2557 #define UVD_MP_SWAP_CNTL__MP_REF13_MC_SWAP__SHIFT 0x1a 2558 #define UVD_MP_SWAP_CNTL__MP_REF14_MC_SWAP__SHIFT 0x1c 2559 #define UVD_MP_SWAP_CNTL__MP_REF15_MC_SWAP__SHIFT 0x1e 2560 #define UVD_MP_SWAP_CNTL__MP_REF0_MC_SWAP_MASK 0x00000003L 2561 #define UVD_MP_SWAP_CNTL__MP_REF1_MC_SWAP_MASK 0x0000000CL 2562 #define UVD_MP_SWAP_CNTL__MP_REF2_MC_SWAP_MASK 0x00000030L 2563 #define UVD_MP_SWAP_CNTL__MP_REF3_MC_SWAP_MASK 0x000000C0L 2564 #define UVD_MP_SWAP_CNTL__MP_REF4_MC_SWAP_MASK 0x00000300L 2565 #define UVD_MP_SWAP_CNTL__MP_REF5_MC_SWAP_MASK 0x00000C00L 2566 #define UVD_MP_SWAP_CNTL__MP_REF6_MC_SWAP_MASK 0x00003000L 2567 #define UVD_MP_SWAP_CNTL__MP_REF7_MC_SWAP_MASK 0x0000C000L 2568 #define UVD_MP_SWAP_CNTL__MP_REF8_MC_SWAP_MASK 0x00030000L 2569 #define UVD_MP_SWAP_CNTL__MP_REF9_MC_SWAP_MASK 0x000C0000L 2570 #define UVD_MP_SWAP_CNTL__MP_REF10_MC_SWAP_MASK 0x00300000L 2571 #define UVD_MP_SWAP_CNTL__MP_REF11_MC_SWAP_MASK 0x00C00000L 2572 #define UVD_MP_SWAP_CNTL__MP_REF12_MC_SWAP_MASK 0x03000000L 2573 #define UVD_MP_SWAP_CNTL__MP_REF13_MC_SWAP_MASK 0x0C000000L 2574 #define UVD_MP_SWAP_CNTL__MP_REF14_MC_SWAP_MASK 0x30000000L 2575 #define UVD_MP_SWAP_CNTL__MP_REF15_MC_SWAP_MASK 0xC0000000L 2576 //UVD_MPC_LUMA_SRCH 2577 #define UVD_MPC_LUMA_SRCH__CNTR__SHIFT 0x0 2578 #define UVD_MPC_LUMA_SRCH__CNTR_MASK 0xFFFFFFFFL 2579 //UVD_MPC_LUMA_HIT 2580 #define UVD_MPC_LUMA_HIT__CNTR__SHIFT 0x0 2581 #define UVD_MPC_LUMA_HIT__CNTR_MASK 0xFFFFFFFFL 2582 //UVD_MPC_LUMA_HITPEND 2583 #define UVD_MPC_LUMA_HITPEND__CNTR__SHIFT 0x0 2584 #define UVD_MPC_LUMA_HITPEND__CNTR_MASK 0xFFFFFFFFL 2585 //UVD_MPC_CHROMA_SRCH 2586 #define UVD_MPC_CHROMA_SRCH__CNTR__SHIFT 0x0 2587 #define UVD_MPC_CHROMA_SRCH__CNTR_MASK 0xFFFFFFFFL 2588 //UVD_MPC_CHROMA_HIT 2589 #define UVD_MPC_CHROMA_HIT__CNTR__SHIFT 0x0 2590 #define UVD_MPC_CHROMA_HIT__CNTR_MASK 0xFFFFFFFFL 2591 //UVD_MPC_CHROMA_HITPEND 2592 #define UVD_MPC_CHROMA_HITPEND__CNTR__SHIFT 0x0 2593 #define UVD_MPC_CHROMA_HITPEND__CNTR_MASK 0xFFFFFFFFL 2594 //UVD_MPC_CNTL 2595 #define UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT 0x3 2596 #define UVD_MPC_CNTL__PERF_RST__SHIFT 0x6 2597 #define UVD_MPC_CNTL__AVE_WEIGHT__SHIFT 0x10 2598 #define UVD_MPC_CNTL__URGENT_EN__SHIFT 0x12 2599 #define UVD_MPC_CNTL__SMPAT_REQ_SPEED_UP__SHIFT 0x13 2600 #define UVD_MPC_CNTL__TEST_MODE_EN__SHIFT 0x14 2601 #define UVD_MPC_CNTL__REPLACEMENT_MODE_MASK 0x00000038L 2602 #define UVD_MPC_CNTL__PERF_RST_MASK 0x00000040L 2603 #define UVD_MPC_CNTL__AVE_WEIGHT_MASK 0x00030000L 2604 #define UVD_MPC_CNTL__URGENT_EN_MASK 0x00040000L 2605 #define UVD_MPC_CNTL__SMPAT_REQ_SPEED_UP_MASK 0x00080000L 2606 #define UVD_MPC_CNTL__TEST_MODE_EN_MASK 0x00100000L 2607 //UVD_MPC_PITCH 2608 #define UVD_MPC_PITCH__LUMA_PITCH__SHIFT 0x0 2609 #define UVD_MPC_PITCH__LUMA_PITCH_MASK 0x000007FFL 2610 //UVD_MPC_SET_MUXA0 2611 #define UVD_MPC_SET_MUXA0__VARA_0__SHIFT 0x0 2612 #define UVD_MPC_SET_MUXA0__VARA_1__SHIFT 0x6 2613 #define UVD_MPC_SET_MUXA0__VARA_2__SHIFT 0xc 2614 #define UVD_MPC_SET_MUXA0__VARA_3__SHIFT 0x12 2615 #define UVD_MPC_SET_MUXA0__VARA_4__SHIFT 0x18 2616 #define UVD_MPC_SET_MUXA0__VARA_0_MASK 0x0000003FL 2617 #define UVD_MPC_SET_MUXA0__VARA_1_MASK 0x00000FC0L 2618 #define UVD_MPC_SET_MUXA0__VARA_2_MASK 0x0003F000L 2619 #define UVD_MPC_SET_MUXA0__VARA_3_MASK 0x00FC0000L 2620 #define UVD_MPC_SET_MUXA0__VARA_4_MASK 0x3F000000L 2621 //UVD_MPC_SET_MUXA1 2622 #define UVD_MPC_SET_MUXA1__VARA_5__SHIFT 0x0 2623 #define UVD_MPC_SET_MUXA1__VARA_6__SHIFT 0x6 2624 #define UVD_MPC_SET_MUXA1__VARA_7__SHIFT 0xc 2625 #define UVD_MPC_SET_MUXA1__VARA_5_MASK 0x0000003FL 2626 #define UVD_MPC_SET_MUXA1__VARA_6_MASK 0x00000FC0L 2627 #define UVD_MPC_SET_MUXA1__VARA_7_MASK 0x0003F000L 2628 //UVD_MPC_SET_MUXB0 2629 #define UVD_MPC_SET_MUXB0__VARB_0__SHIFT 0x0 2630 #define UVD_MPC_SET_MUXB0__VARB_1__SHIFT 0x6 2631 #define UVD_MPC_SET_MUXB0__VARB_2__SHIFT 0xc 2632 #define UVD_MPC_SET_MUXB0__VARB_3__SHIFT 0x12 2633 #define UVD_MPC_SET_MUXB0__VARB_4__SHIFT 0x18 2634 #define UVD_MPC_SET_MUXB0__VARB_0_MASK 0x0000003FL 2635 #define UVD_MPC_SET_MUXB0__VARB_1_MASK 0x00000FC0L 2636 #define UVD_MPC_SET_MUXB0__VARB_2_MASK 0x0003F000L 2637 #define UVD_MPC_SET_MUXB0__VARB_3_MASK 0x00FC0000L 2638 #define UVD_MPC_SET_MUXB0__VARB_4_MASK 0x3F000000L 2639 //UVD_MPC_SET_MUXB1 2640 #define UVD_MPC_SET_MUXB1__VARB_5__SHIFT 0x0 2641 #define UVD_MPC_SET_MUXB1__VARB_6__SHIFT 0x6 2642 #define UVD_MPC_SET_MUXB1__VARB_7__SHIFT 0xc 2643 #define UVD_MPC_SET_MUXB1__VARB_5_MASK 0x0000003FL 2644 #define UVD_MPC_SET_MUXB1__VARB_6_MASK 0x00000FC0L 2645 #define UVD_MPC_SET_MUXB1__VARB_7_MASK 0x0003F000L 2646 //UVD_MPC_SET_MUX 2647 #define UVD_MPC_SET_MUX__SET_0__SHIFT 0x0 2648 #define UVD_MPC_SET_MUX__SET_1__SHIFT 0x3 2649 #define UVD_MPC_SET_MUX__SET_2__SHIFT 0x6 2650 #define UVD_MPC_SET_MUX__SET_0_MASK 0x00000007L 2651 #define UVD_MPC_SET_MUX__SET_1_MASK 0x00000038L 2652 #define UVD_MPC_SET_MUX__SET_2_MASK 0x000001C0L 2653 //UVD_MPC_SET_ALU 2654 #define UVD_MPC_SET_ALU__FUNCT__SHIFT 0x0 2655 #define UVD_MPC_SET_ALU__OPERAND__SHIFT 0x4 2656 #define UVD_MPC_SET_ALU__FUNCT_MASK 0x00000007L 2657 #define UVD_MPC_SET_ALU__OPERAND_MASK 0x00000FF0L 2658 //UVD_GPCOM_SYS_CMD 2659 #define UVD_GPCOM_SYS_CMD__CMD_SEND__SHIFT 0x0 2660 #define UVD_GPCOM_SYS_CMD__CMD__SHIFT 0x1 2661 #define UVD_GPCOM_SYS_CMD__CMD_SOURCE__SHIFT 0x1f 2662 #define UVD_GPCOM_SYS_CMD__CMD_SEND_MASK 0x00000001L 2663 #define UVD_GPCOM_SYS_CMD__CMD_MASK 0x7FFFFFFEL 2664 #define UVD_GPCOM_SYS_CMD__CMD_SOURCE_MASK 0x80000000L 2665 //UVD_GPCOM_SYS_DATA0 2666 #define UVD_GPCOM_SYS_DATA0__DATA0__SHIFT 0x0 2667 #define UVD_GPCOM_SYS_DATA0__DATA0_MASK 0xFFFFFFFFL 2668 //UVD_GPCOM_SYS_DATA1 2669 #define UVD_GPCOM_SYS_DATA1__DATA1__SHIFT 0x0 2670 #define UVD_GPCOM_SYS_DATA1__DATA1_MASK 0xFFFFFFFFL 2671 //UVD_VCPU_CACHE_OFFSET0 2672 #define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT 0x0 2673 #define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0_MASK 0x001FFFFFL 2674 //UVD_VCPU_CACHE_SIZE0 2675 #define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0__SHIFT 0x0 2676 #define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0_MASK 0x001FFFFFL 2677 //UVD_VCPU_CACHE_OFFSET1 2678 #define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1__SHIFT 0x0 2679 #define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1_MASK 0x001FFFFFL 2680 //UVD_VCPU_CACHE_SIZE1 2681 #define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1__SHIFT 0x0 2682 #define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1_MASK 0x001FFFFFL 2683 //UVD_VCPU_CACHE_OFFSET2 2684 #define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2__SHIFT 0x0 2685 #define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2_MASK 0x001FFFFFL 2686 //UVD_VCPU_CACHE_SIZE2 2687 #define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2__SHIFT 0x0 2688 #define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2_MASK 0x001FFFFFL 2689 //UVD_VCPU_CACHE_OFFSET3 2690 #define UVD_VCPU_CACHE_OFFSET3__CACHE_OFFSET3__SHIFT 0x0 2691 #define UVD_VCPU_CACHE_OFFSET3__CACHE_OFFSET3_MASK 0x001FFFFFL 2692 //UVD_VCPU_CACHE_SIZE3 2693 #define UVD_VCPU_CACHE_SIZE3__CACHE_SIZE3__SHIFT 0x0 2694 #define UVD_VCPU_CACHE_SIZE3__CACHE_SIZE3_MASK 0x001FFFFFL 2695 //UVD_VCPU_CACHE_OFFSET4 2696 #define UVD_VCPU_CACHE_OFFSET4__CACHE_OFFSET4__SHIFT 0x0 2697 #define UVD_VCPU_CACHE_OFFSET4__CACHE_OFFSET4_MASK 0x001FFFFFL 2698 //UVD_VCPU_CACHE_SIZE4 2699 #define UVD_VCPU_CACHE_SIZE4__CACHE_SIZE4__SHIFT 0x0 2700 #define UVD_VCPU_CACHE_SIZE4__CACHE_SIZE4_MASK 0x001FFFFFL 2701 //UVD_VCPU_CACHE_OFFSET5 2702 #define UVD_VCPU_CACHE_OFFSET5__CACHE_OFFSET5__SHIFT 0x0 2703 #define UVD_VCPU_CACHE_OFFSET5__CACHE_OFFSET5_MASK 0x001FFFFFL 2704 //UVD_VCPU_CACHE_SIZE5 2705 #define UVD_VCPU_CACHE_SIZE5__CACHE_SIZE5__SHIFT 0x0 2706 #define UVD_VCPU_CACHE_SIZE5__CACHE_SIZE5_MASK 0x001FFFFFL 2707 //UVD_VCPU_CACHE_OFFSET6 2708 #define UVD_VCPU_CACHE_OFFSET6__CACHE_OFFSET6__SHIFT 0x0 2709 #define UVD_VCPU_CACHE_OFFSET6__CACHE_OFFSET6_MASK 0x001FFFFFL 2710 //UVD_VCPU_CACHE_SIZE6 2711 #define UVD_VCPU_CACHE_SIZE6__CACHE_SIZE6__SHIFT 0x0 2712 #define UVD_VCPU_CACHE_SIZE6__CACHE_SIZE6_MASK 0x001FFFFFL 2713 //UVD_VCPU_CACHE_OFFSET7 2714 #define UVD_VCPU_CACHE_OFFSET7__CACHE_OFFSET7__SHIFT 0x0 2715 #define UVD_VCPU_CACHE_OFFSET7__CACHE_OFFSET7_MASK 0x001FFFFFL 2716 //UVD_VCPU_CACHE_SIZE7 2717 #define UVD_VCPU_CACHE_SIZE7__CACHE_SIZE7__SHIFT 0x0 2718 #define UVD_VCPU_CACHE_SIZE7__CACHE_SIZE7_MASK 0x001FFFFFL 2719 //UVD_VCPU_CACHE_OFFSET8 2720 #define UVD_VCPU_CACHE_OFFSET8__CACHE_OFFSET8__SHIFT 0x0 2721 #define UVD_VCPU_CACHE_OFFSET8__CACHE_OFFSET8_MASK 0x001FFFFFL 2722 //UVD_VCPU_CACHE_SIZE8 2723 #define UVD_VCPU_CACHE_SIZE8__CACHE_SIZE8__SHIFT 0x0 2724 #define UVD_VCPU_CACHE_SIZE8__CACHE_SIZE8_MASK 0x001FFFFFL 2725 //UVD_VCPU_NONCACHE_OFFSET0 2726 #define UVD_VCPU_NONCACHE_OFFSET0__NONCACHE_OFFSET0__SHIFT 0x0 2727 #define UVD_VCPU_NONCACHE_OFFSET0__NONCACHE_OFFSET0_MASK 0x01FFFFFFL 2728 //UVD_VCPU_NONCACHE_SIZE0 2729 #define UVD_VCPU_NONCACHE_SIZE0__NONCACHE_SIZE0__SHIFT 0x0 2730 #define UVD_VCPU_NONCACHE_SIZE0__NONCACHE_SIZE0_MASK 0x001FFFFFL 2731 //UVD_VCPU_NONCACHE_OFFSET1 2732 #define UVD_VCPU_NONCACHE_OFFSET1__NONCACHE_OFFSET1__SHIFT 0x0 2733 #define UVD_VCPU_NONCACHE_OFFSET1__NONCACHE_OFFSET1_MASK 0x01FFFFFFL 2734 //UVD_VCPU_NONCACHE_SIZE1 2735 #define UVD_VCPU_NONCACHE_SIZE1__NONCACHE_SIZE1__SHIFT 0x0 2736 #define UVD_VCPU_NONCACHE_SIZE1__NONCACHE_SIZE1_MASK 0x001FFFFFL 2737 //UVD_VCPU_CNTL 2738 #define UVD_VCPU_CNTL__IRQ_ERR__SHIFT 0x0 2739 #define UVD_VCPU_CNTL__PMB_ED_ENABLE__SHIFT 0x5 2740 #define UVD_VCPU_CNTL__PMB_SOFT_RESET__SHIFT 0x6 2741 #define UVD_VCPU_CNTL__RBBM_SOFT_RESET__SHIFT 0x7 2742 #define UVD_VCPU_CNTL__ABORT_REQ__SHIFT 0x8 2743 #define UVD_VCPU_CNTL__CLK_EN__SHIFT 0x9 2744 #define UVD_VCPU_CNTL__TRCE_EN__SHIFT 0xa 2745 #define UVD_VCPU_CNTL__TRCE_MUX__SHIFT 0xb 2746 #define UVD_VCPU_CNTL__JTAG_EN__SHIFT 0x10 2747 #define UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP__SHIFT 0x11 2748 #define UVD_VCPU_CNTL__TIMEOUT_DIS__SHIFT 0x12 2749 #define UVD_VCPU_CNTL__SUVD_EN__SHIFT 0x13 2750 #define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT 0x14 2751 #define UVD_VCPU_CNTL__CABAC_MB_ACC__SHIFT 0x1c 2752 #define UVD_VCPU_CNTL__WMV9_EN__SHIFT 0x1e 2753 #define UVD_VCPU_CNTL__RE_OFFLOAD_EN__SHIFT 0x1f 2754 #define UVD_VCPU_CNTL__IRQ_ERR_MASK 0x0000000FL 2755 #define UVD_VCPU_CNTL__PMB_ED_ENABLE_MASK 0x00000020L 2756 #define UVD_VCPU_CNTL__PMB_SOFT_RESET_MASK 0x00000040L 2757 #define UVD_VCPU_CNTL__RBBM_SOFT_RESET_MASK 0x00000080L 2758 #define UVD_VCPU_CNTL__ABORT_REQ_MASK 0x00000100L 2759 #define UVD_VCPU_CNTL__CLK_EN_MASK 0x00000200L 2760 #define UVD_VCPU_CNTL__TRCE_EN_MASK 0x00000400L 2761 #define UVD_VCPU_CNTL__TRCE_MUX_MASK 0x00001800L 2762 #define UVD_VCPU_CNTL__JTAG_EN_MASK 0x00010000L 2763 #define UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK 0x00020000L 2764 #define UVD_VCPU_CNTL__TIMEOUT_DIS_MASK 0x00040000L 2765 #define UVD_VCPU_CNTL__SUVD_EN_MASK 0x00080000L 2766 #define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL_MASK 0x0FF00000L 2767 #define UVD_VCPU_CNTL__CABAC_MB_ACC_MASK 0x10000000L 2768 #define UVD_VCPU_CNTL__WMV9_EN_MASK 0x40000000L 2769 #define UVD_VCPU_CNTL__RE_OFFLOAD_EN_MASK 0x80000000L 2770 //UVD_VCPU_PRID 2771 #define UVD_VCPU_PRID__PRID__SHIFT 0x0 2772 #define UVD_VCPU_PRID__PRID_MASK 0x0000FFFFL 2773 //UVD_VCPU_TRCE 2774 #define UVD_VCPU_TRCE__PC__SHIFT 0x0 2775 #define UVD_VCPU_TRCE__PC_MASK 0x0FFFFFFFL 2776 //UVD_VCPU_TRCE_RD 2777 #define UVD_VCPU_TRCE_RD__DATA__SHIFT 0x0 2778 #define UVD_VCPU_TRCE_RD__DATA_MASK 0xFFFFFFFFL 2779 //UVD_MPC_PERF0 2780 #define UVD_MPC_PERF0__MAX_LAT__SHIFT 0x0 2781 #define UVD_MPC_PERF0__MAX_LAT_MASK 0x000003FFL 2782 //UVD_MPC_PERF1 2783 #define UVD_MPC_PERF1__AVE_LAT__SHIFT 0x0 2784 #define UVD_MPC_PERF1__AVE_LAT_MASK 0x000003FFL 2785 //UVD_CXW_WR 2786 #define UVD_CXW_WR__DAT__SHIFT 0x0 2787 #define UVD_CXW_WR__STAT__SHIFT 0x1f 2788 #define UVD_CXW_WR__DAT_MASK 0x0FFFFFFFL 2789 #define UVD_CXW_WR__STAT_MASK 0x80000000L 2790 //UVD_SOFT_RESET 2791 #define UVD_SOFT_RESET__RBC_SOFT_RESET__SHIFT 0x0 2792 #define UVD_SOFT_RESET__LBSI_SOFT_RESET__SHIFT 0x1 2793 #define UVD_SOFT_RESET__LMI_SOFT_RESET__SHIFT 0x2 2794 #define UVD_SOFT_RESET__VCPU_SOFT_RESET__SHIFT 0x3 2795 #define UVD_SOFT_RESET__UDEC_SOFT_RESET__SHIFT 0x4 2796 #define UVD_SOFT_RESET__CSM_SOFT_RESET__SHIFT 0x5 2797 #define UVD_SOFT_RESET__CXW_SOFT_RESET__SHIFT 0x6 2798 #define UVD_SOFT_RESET__TAP_SOFT_RESET__SHIFT 0x7 2799 #define UVD_SOFT_RESET__MPC_SOFT_RESET__SHIFT 0x8 2800 #define UVD_SOFT_RESET__EFC_SOFT_RESET__SHIFT 0x9 2801 #define UVD_SOFT_RESET__IH_SOFT_RESET__SHIFT 0xa 2802 #define UVD_SOFT_RESET__MPRD_SOFT_RESET__SHIFT 0xb 2803 #define UVD_SOFT_RESET__IDCT_SOFT_RESET__SHIFT 0xc 2804 #define UVD_SOFT_RESET__LMI_UMC_SOFT_RESET__SHIFT 0xd 2805 #define UVD_SOFT_RESET__SPH_SOFT_RESET__SHIFT 0xe 2806 #define UVD_SOFT_RESET__MIF_SOFT_RESET__SHIFT 0xf 2807 #define UVD_SOFT_RESET__LCM_SOFT_RESET__SHIFT 0x10 2808 #define UVD_SOFT_RESET__SUVD_SOFT_RESET__SHIFT 0x11 2809 #define UVD_SOFT_RESET__LBSI_VCLK_RESET_STATUS__SHIFT 0x12 2810 #define UVD_SOFT_RESET__VCPU_VCLK_RESET_STATUS__SHIFT 0x13 2811 #define UVD_SOFT_RESET__UDEC_VCLK_RESET_STATUS__SHIFT 0x14 2812 #define UVD_SOFT_RESET__UDEC_DCLK_RESET_STATUS__SHIFT 0x15 2813 #define UVD_SOFT_RESET__MPC_DCLK_RESET_STATUS__SHIFT 0x16 2814 #define UVD_SOFT_RESET__MPRD_VCLK_RESET_STATUS__SHIFT 0x17 2815 #define UVD_SOFT_RESET__MPRD_DCLK_RESET_STATUS__SHIFT 0x18 2816 #define UVD_SOFT_RESET__IDCT_VCLK_RESET_STATUS__SHIFT 0x19 2817 #define UVD_SOFT_RESET__MIF_DCLK_RESET_STATUS__SHIFT 0x1a 2818 #define UVD_SOFT_RESET__LCM_DCLK_RESET_STATUS__SHIFT 0x1b 2819 #define UVD_SOFT_RESET__SUVD_VCLK_RESET_STATUS__SHIFT 0x1c 2820 #define UVD_SOFT_RESET__SUVD_DCLK_RESET_STATUS__SHIFT 0x1d 2821 #define UVD_SOFT_RESET__RE_DCLK_RESET_STATUS__SHIFT 0x1e 2822 #define UVD_SOFT_RESET__SRE_DCLK_RESET_STATUS__SHIFT 0x1f 2823 #define UVD_SOFT_RESET__RBC_SOFT_RESET_MASK 0x00000001L 2824 #define UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK 0x00000002L 2825 #define UVD_SOFT_RESET__LMI_SOFT_RESET_MASK 0x00000004L 2826 #define UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK 0x00000008L 2827 #define UVD_SOFT_RESET__UDEC_SOFT_RESET_MASK 0x00000010L 2828 #define UVD_SOFT_RESET__CSM_SOFT_RESET_MASK 0x00000020L 2829 #define UVD_SOFT_RESET__CXW_SOFT_RESET_MASK 0x00000040L 2830 #define UVD_SOFT_RESET__TAP_SOFT_RESET_MASK 0x00000080L 2831 #define UVD_SOFT_RESET__MPC_SOFT_RESET_MASK 0x00000100L 2832 #define UVD_SOFT_RESET__EFC_SOFT_RESET_MASK 0x00000200L 2833 #define UVD_SOFT_RESET__IH_SOFT_RESET_MASK 0x00000400L 2834 #define UVD_SOFT_RESET__MPRD_SOFT_RESET_MASK 0x00000800L 2835 #define UVD_SOFT_RESET__IDCT_SOFT_RESET_MASK 0x00001000L 2836 #define UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK 0x00002000L 2837 #define UVD_SOFT_RESET__SPH_SOFT_RESET_MASK 0x00004000L 2838 #define UVD_SOFT_RESET__MIF_SOFT_RESET_MASK 0x00008000L 2839 #define UVD_SOFT_RESET__LCM_SOFT_RESET_MASK 0x00010000L 2840 #define UVD_SOFT_RESET__SUVD_SOFT_RESET_MASK 0x00020000L 2841 #define UVD_SOFT_RESET__LBSI_VCLK_RESET_STATUS_MASK 0x00040000L 2842 #define UVD_SOFT_RESET__VCPU_VCLK_RESET_STATUS_MASK 0x00080000L 2843 #define UVD_SOFT_RESET__UDEC_VCLK_RESET_STATUS_MASK 0x00100000L 2844 #define UVD_SOFT_RESET__UDEC_DCLK_RESET_STATUS_MASK 0x00200000L 2845 #define UVD_SOFT_RESET__MPC_DCLK_RESET_STATUS_MASK 0x00400000L 2846 #define UVD_SOFT_RESET__MPRD_VCLK_RESET_STATUS_MASK 0x00800000L 2847 #define UVD_SOFT_RESET__MPRD_DCLK_RESET_STATUS_MASK 0x01000000L 2848 #define UVD_SOFT_RESET__IDCT_VCLK_RESET_STATUS_MASK 0x02000000L 2849 #define UVD_SOFT_RESET__MIF_DCLK_RESET_STATUS_MASK 0x04000000L 2850 #define UVD_SOFT_RESET__LCM_DCLK_RESET_STATUS_MASK 0x08000000L 2851 #define UVD_SOFT_RESET__SUVD_VCLK_RESET_STATUS_MASK 0x10000000L 2852 #define UVD_SOFT_RESET__SUVD_DCLK_RESET_STATUS_MASK 0x20000000L 2853 #define UVD_SOFT_RESET__RE_DCLK_RESET_STATUS_MASK 0x40000000L 2854 #define UVD_SOFT_RESET__SRE_DCLK_RESET_STATUS_MASK 0x80000000L 2855 //UVD_LMI_RBC_IB_VMID 2856 #define UVD_LMI_RBC_IB_VMID__IB_VMID__SHIFT 0x0 2857 #define UVD_LMI_RBC_IB_VMID__IB_VMID_MASK 0x0000000FL 2858 //UVD_RBC_IB_SIZE 2859 #define UVD_RBC_IB_SIZE__IB_SIZE__SHIFT 0x4 2860 #define UVD_RBC_IB_SIZE__IB_SIZE_MASK 0x007FFFF0L 2861 //UVD_LMI_RBC_RB_VMID 2862 #define UVD_LMI_RBC_RB_VMID__RB_VMID__SHIFT 0x0 2863 #define UVD_LMI_RBC_RB_VMID__RB_VMID_MASK 0x0000000FL 2864 //UVD_RBC_RB_RPTR 2865 #define UVD_RBC_RB_RPTR__RB_RPTR__SHIFT 0x4 2866 #define UVD_RBC_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L 2867 //UVD_RBC_RB_WPTR 2868 #define UVD_RBC_RB_WPTR__RB_WPTR__SHIFT 0x4 2869 #define UVD_RBC_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L 2870 //UVD_RBC_RB_WPTR_CNTL 2871 #define UVD_RBC_RB_WPTR_CNTL__RB_PRE_WRITE_TIMER__SHIFT 0x0 2872 #define UVD_RBC_RB_WPTR_CNTL__RB_PRE_WRITE_TIMER_MASK 0x00007FFFL 2873 //UVD_RBC_READ_REQ_URGENT_CNTL 2874 #define UVD_RBC_READ_REQ_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK__SHIFT 0x0 2875 #define UVD_RBC_READ_REQ_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK_MASK 0x00000003L 2876 //UVD_RBC_WPTR_STATUS 2877 #define UVD_RBC_WPTR_STATUS__RB_WPTR_IN_USE__SHIFT 0x4 2878 #define UVD_RBC_WPTR_STATUS__RB_WPTR_IN_USE_MASK 0x007FFFF0L 2879 //UVD_RBC_RB_CNTL 2880 #define UVD_RBC_RB_CNTL__RB_BUFSZ__SHIFT 0x0 2881 #define UVD_RBC_RB_CNTL__RB_BLKSZ__SHIFT 0x8 2882 #define UVD_RBC_RB_CNTL__RB_NO_FETCH__SHIFT 0x10 2883 #define UVD_RBC_RB_CNTL__RB_WPTR_POLL_EN__SHIFT 0x14 2884 #define UVD_RBC_RB_CNTL__RB_NO_UPDATE__SHIFT 0x18 2885 #define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN__SHIFT 0x1c 2886 #define UVD_RBC_RB_CNTL__RB_BUFSZ_MASK 0x0000001FL 2887 #define UVD_RBC_RB_CNTL__RB_BLKSZ_MASK 0x00001F00L 2888 #define UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK 0x00010000L 2889 #define UVD_RBC_RB_CNTL__RB_WPTR_POLL_EN_MASK 0x00100000L 2890 #define UVD_RBC_RB_CNTL__RB_NO_UPDATE_MASK 0x01000000L 2891 #define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x10000000L 2892 //UVD_RBC_RB_RPTR_ADDR 2893 #define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x0 2894 #define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xFFFFFFFFL 2895 //UVD_JOB_START 2896 #define UVD_JOB_START__JOB_START__SHIFT 0x0 2897 #define UVD_JOB_START__JOB_START_MASK 0x00000001L 2898 //UVD_JOB_DONE 2899 #define UVD_JOB_DONE__JOB_DONE__SHIFT 0x0 2900 #define UVD_JOB_DONE__JOB_DONE_MASK 0x00000003L 2901 //UVD_STATUS 2902 #define UVD_STATUS__RBC_BUSY__SHIFT 0x0 2903 #define UVD_STATUS__VCPU_REPORT__SHIFT 0x1 2904 #define UVD_STATUS__AVP_BUSY__SHIFT 0x8 2905 #define UVD_STATUS__IDCT_BUSY__SHIFT 0x9 2906 #define UVD_STATUS__IDCT_CTL_ACK__SHIFT 0xb 2907 #define UVD_STATUS__UVD_CTL_ACK__SHIFT 0xc 2908 #define UVD_STATUS__AVP_BLOCK_ACK__SHIFT 0xd 2909 #define UVD_STATUS__IDCT_BLOCK_ACK__SHIFT 0xe 2910 #define UVD_STATUS__UVD_BLOCK_ACK__SHIFT 0xf 2911 #define UVD_STATUS__RBC_ACCESS_GPCOM__SHIFT 0x10 2912 #define UVD_STATUS__SYS_GPCOM_REQ__SHIFT 0x1f 2913 #define UVD_STATUS__RBC_BUSY_MASK 0x00000001L 2914 #define UVD_STATUS__VCPU_REPORT_MASK 0x000000FEL 2915 #define UVD_STATUS__AVP_BUSY_MASK 0x00000100L 2916 #define UVD_STATUS__IDCT_BUSY_MASK 0x00000200L 2917 #define UVD_STATUS__IDCT_CTL_ACK_MASK 0x00000800L 2918 #define UVD_STATUS__UVD_CTL_ACK_MASK 0x00001000L 2919 #define UVD_STATUS__AVP_BLOCK_ACK_MASK 0x00002000L 2920 #define UVD_STATUS__IDCT_BLOCK_ACK_MASK 0x00004000L 2921 #define UVD_STATUS__UVD_BLOCK_ACK_MASK 0x00008000L 2922 #define UVD_STATUS__RBC_ACCESS_GPCOM_MASK 0x00010000L 2923 #define UVD_STATUS__SYS_GPCOM_REQ_MASK 0x80000000L 2924 //UVD_SEMA_TIMEOUT_STATUS 2925 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT__SHIFT 0x0 2926 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT__SHIFT 0x1 2927 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT__SHIFT 0x2 2928 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_TIMEOUT_CLEAR__SHIFT 0x3 2929 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT_MASK 0x00000001L 2930 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT_MASK 0x00000002L 2931 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT_MASK 0x00000004L 2932 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_TIMEOUT_CLEAR_MASK 0x00000008L 2933 //UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL 2934 #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_EN__SHIFT 0x0 2935 #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_COUNT__SHIFT 0x1 2936 #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18 2937 #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_EN_MASK 0x00000001L 2938 #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_COUNT_MASK 0x001FFFFEL 2939 #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x07000000L 2940 //UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL 2941 #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_EN__SHIFT 0x0 2942 #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_COUNT__SHIFT 0x1 2943 #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18 2944 #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_EN_MASK 0x00000001L 2945 #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_COUNT_MASK 0x001FFFFEL 2946 #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x07000000L 2947 //UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL 2948 #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_EN__SHIFT 0x0 2949 #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_COUNT__SHIFT 0x1 2950 #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18 2951 #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_EN_MASK 0x00000001L 2952 #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_COUNT_MASK 0x001FFFFEL 2953 #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x07000000L 2954 //UVD_CXW_EN 2955 #define UVD_CXW_EN__CXW_ENABLE__SHIFT 0x0 2956 #define UVD_CXW_EN__CXW_ENABLE_MASK 0x00000001L 2957 //UVD_CXW_SE 2958 #define UVD_CXW_SE__CXW_SCAN_ENABLE__SHIFT 0x0 2959 #define UVD_CXW_SE__CXW_SCAN_ENABLE_MASK 0x00000001L 2960 //UVD_CXW_FINISHED 2961 #define UVD_CXW_FINISHED__CXW_FINISHED__SHIFT 0x0 2962 #define UVD_CXW_FINISHED__CXW_FINISHED_MASK 0x00000001L 2963 //UVD_CXW_SHIFT_FINISHED 2964 #define UVD_CXW_SHIFT_FINISHED__SHIFT_FINISHED__SHIFT 0x0 2965 #define UVD_CXW_SHIFT_FINISHED__SHIFT_FINISHED_MASK 0x00000001L 2966 //UVD_CXW_START 2967 #define UVD_CXW_START__START_CXW__SHIFT 0x0 2968 #define UVD_CXW_START__START_CXW_MASK 0x00000001L 2969 //UVD_CXW_BLOCK_STATUS 2970 #define UVD_CXW_BLOCK_STATUS__VCPU_IDLE__SHIFT 0x0 2971 #define UVD_CXW_BLOCK_STATUS__LBSI_IDLE__SHIFT 0x1 2972 #define UVD_CXW_BLOCK_STATUS__LMI_IDLE__SHIFT 0x2 2973 #define UVD_CXW_BLOCK_STATUS__VCPU_IDLE_MASK 0x00000001L 2974 #define UVD_CXW_BLOCK_STATUS__LBSI_IDLE_MASK 0x00000002L 2975 #define UVD_CXW_BLOCK_STATUS__LMI_IDLE_MASK 0x00000004L 2976 //UVD_STOP_CONTEXT 2977 #define UVD_STOP_CONTEXT__STOP_CONTEXT__SHIFT 0x0 2978 #define UVD_STOP_CONTEXT__CONTEXT_MODE__SHIFT 0x1 2979 #define UVD_STOP_CONTEXT__STOP_CONTEXT_MASK 0x00000001L 2980 #define UVD_STOP_CONTEXT__CONTEXT_MODE_MASK 0x00000002L 2981 //UVD_CXW_SAVE_AREA_ADDR 2982 #define UVD_CXW_SAVE_AREA_ADDR__CXW_SAVE_AREA_ADDR__SHIFT 0x6 2983 #define UVD_CXW_SAVE_AREA_ADDR__CXW_SAVE_AREA_ADDR_MASK 0xFFFFFFC0L 2984 //UVD_CBUF_ID 2985 #define UVD_CBUF_ID__CBUF_ID__SHIFT 0x0 2986 #define UVD_CBUF_ID__CBUF_ID_MASK 0xFFFFFFFFL 2987 //UVD_CONTEXT_ID 2988 #define UVD_CONTEXT_ID__CONTEXT_ID__SHIFT 0x0 2989 #define UVD_CONTEXT_ID__CONTEXT_ID_MASK 0xFFFFFFFFL 2990 //UVD_CXW_SAVE_AREA_SIZE 2991 #define UVD_CXW_SAVE_AREA_SIZE__CXW_SAVE_AREA_SIZE__SHIFT 0x0 2992 #define UVD_CXW_SAVE_AREA_SIZE__CXW_SAVE_AREA_SIZE_MASK 0xFFFFFFFFL 2993 //UVD_CONTEXT_ID2 2994 #define UVD_CONTEXT_ID2__CONTEXT_ID2__SHIFT 0x0 2995 #define UVD_CONTEXT_ID2__CONTEXT_ID2_MASK 0xFFFFFFFFL 2996 //UVD_CXW_CNTL 2997 #define UVD_CXW_CNTL__HOST_CXW_EN__SHIFT 0x0 2998 #define UVD_CXW_CNTL__EXTERNAL_CXW_EN__SHIFT 0x1 2999 #define UVD_CXW_CNTL__SEMAPHORE_TIMEOUT_CXW_EN__SHIFT 0x3 3000 #define UVD_CXW_CNTL__HOST_CXW_INT_EN__SHIFT 0x4 3001 #define UVD_CXW_CNTL__EXTERNAL_CXW_INT_EN__SHIFT 0x5 3002 #define UVD_CXW_CNTL__SEMAPHORE_TIMEOUT_CXW_INT_EN__SHIFT 0x7 3003 #define UVD_CXW_CNTL__HOST_CXW_EN_MASK 0x00000001L 3004 #define UVD_CXW_CNTL__EXTERNAL_CXW_EN_MASK 0x00000002L 3005 #define UVD_CXW_CNTL__SEMAPHORE_TIMEOUT_CXW_EN_MASK 0x00000008L 3006 #define UVD_CXW_CNTL__HOST_CXW_INT_EN_MASK 0x00000010L 3007 #define UVD_CXW_CNTL__EXTERNAL_CXW_INT_EN_MASK 0x00000020L 3008 #define UVD_CXW_CNTL__SEMAPHORE_TIMEOUT_CXW_INT_EN_MASK 0x00000080L 3009 //UVD_CXW_EVENT 3010 #define UVD_CXW_EVENT__HOST_CXW_EVENT_OCCURRED__SHIFT 0x0 3011 #define UVD_CXW_EVENT__EXTERNAL_CXW_EVENT_OCCURRED__SHIFT 0x1 3012 #define UVD_CXW_EVENT__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_EVENT_OCCURRED__SHIFT 0x3 3013 #define UVD_CXW_EVENT__SEMAPHORE_WAIT_FAULT_TIMEOUT_EVENT_OCCURRED__SHIFT 0x4 3014 #define UVD_CXW_EVENT__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_EVENT_OCCURRED__SHIFT 0x5 3015 #define UVD_CXW_EVENT__HOST_CXW_EVENT_OCCURRED_MASK 0x00000001L 3016 #define UVD_CXW_EVENT__EXTERNAL_CXW_EVENT_OCCURRED_MASK 0x00000002L 3017 #define UVD_CXW_EVENT__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_EVENT_OCCURRED_MASK 0x00000008L 3018 #define UVD_CXW_EVENT__SEMAPHORE_WAIT_FAULT_TIMEOUT_EVENT_OCCURRED_MASK 0x00000010L 3019 #define UVD_CXW_EVENT__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_EVENT_OCCURRED_MASK 0x00000020L 3020 //UVD_CXW_SCAN_AREA_OFFSET 3021 #define UVD_CXW_SCAN_AREA_OFFSET__CXW_SCAN_AREA_OFFSET__SHIFT 0x0 3022 #define UVD_CXW_SCAN_AREA_OFFSET__CXW_CONTEXT_RESTORE__SHIFT 0x1a 3023 #define UVD_CXW_SCAN_AREA_OFFSET__CXW_CONTEXT_SAVE__SHIFT 0x1b 3024 #define UVD_CXW_SCAN_AREA_OFFSET__CXW_SCAN_AREA_OFFSET_MASK 0x03FFFFFFL 3025 #define UVD_CXW_SCAN_AREA_OFFSET__CXW_CONTEXT_RESTORE_MASK 0x04000000L 3026 #define UVD_CXW_SCAN_AREA_OFFSET__CXW_CONTEXT_SAVE_MASK 0x08000000L 3027 //UVD_CXW_SHIFT_CNTL 3028 #define UVD_CXW_SHIFT_CNTL__SHIFT_CNTL__SHIFT 0x0 3029 #define UVD_CXW_SHIFT_CNTL__SHIFT_COUNT__SHIFT 0x1 3030 #define UVD_CXW_SHIFT_CNTL__SHIFT_CNTL_MASK 0x00000001L 3031 #define UVD_CXW_SHIFT_CNTL__SHIFT_COUNT_MASK 0x00000FFEL 3032 //UVD_RBC_CAM_EN 3033 #define UVD_RBC_CAM_EN__RBC_CAM_EN__SHIFT 0x0 3034 #define UVD_RBC_CAM_EN__RBC_CAM_EN_MASK 0x00000001L 3035 //UVD_RBC_CAM_INDEX 3036 #define UVD_RBC_CAM_INDEX__RBC_CAM_INDEX__SHIFT 0x0 3037 #define UVD_RBC_CAM_INDEX__RBC_CAM_INDEX_MASK 0xFFFFFFFFL 3038 //UVD_RBC_CAM_DATA 3039 #define UVD_RBC_CAM_DATA__RBC_CAM_DATA_ORG__SHIFT 0x0 3040 #define UVD_RBC_CAM_DATA__RBC_CAM_DATA_MAP__SHIFT 0x10 3041 #define UVD_RBC_CAM_DATA__RBC_CAM_DATA_ORG_MASK 0x0000FFFFL 3042 #define UVD_RBC_CAM_DATA__RBC_CAM_DATA_MAP_MASK 0xFFFF0000L 3043 //UVD_RBC_VCPU_ACCESS 3044 #define UVD_RBC_VCPU_ACCESS__ENABLE_RBC__SHIFT 0x0 3045 #define UVD_RBC_VCPU_ACCESS__ENABLE_RBC_MASK 0x00000001L 3046 //UVD_CXW_INT_ID 3047 #define UVD_CXW_INT_ID__ID__SHIFT 0x0 3048 #define UVD_CXW_INT_ID__ID_MASK 0x000000FFL 3049 //UVD_LMI_CRC0 3050 #define UVD_LMI_CRC0__CRC32__SHIFT 0x0 3051 #define UVD_LMI_CRC0__CRC32_MASK 0xFFFFFFFFL 3052 //UVD_LMI_CRC1 3053 #define UVD_LMI_CRC1__CRC32__SHIFT 0x0 3054 #define UVD_LMI_CRC1__CRC32_MASK 0xFFFFFFFFL 3055 //UVD_LMI_CRC2 3056 #define UVD_LMI_CRC2__CRC32__SHIFT 0x0 3057 #define UVD_LMI_CRC2__CRC32_MASK 0xFFFFFFFFL 3058 //UVD_LMI_CRC3 3059 #define UVD_LMI_CRC3__CRC32__SHIFT 0x0 3060 #define UVD_LMI_CRC3__CRC32_MASK 0xFFFFFFFFL 3061 //UVD_RBC_WPTR_POLL_CNTL 3062 #define UVD_RBC_WPTR_POLL_CNTL__POLL_FREQ__SHIFT 0x0 3063 #define UVD_RBC_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 3064 #define UVD_RBC_WPTR_POLL_CNTL__POLL_FREQ_MASK 0x0000FFFFL 3065 #define UVD_RBC_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 3066 //UVD_RBC_WPTR_POLL_ADDR 3067 #define UVD_RBC_WPTR_POLL_ADDR__POLL_ADDR__SHIFT 0x2 3068 #define UVD_RBC_WPTR_POLL_ADDR__POLL_ADDR_MASK 0xFFFFFFFCL 3069 //UVD_RB_BASE_LO4 3070 #define UVD_RB_BASE_LO4__RB_BASE_LO__SHIFT 0x6 3071 #define UVD_RB_BASE_LO4__RB_BASE_LO_MASK 0xFFFFFFC0L 3072 //UVD_RB_BASE_HI4 3073 #define UVD_RB_BASE_HI4__RB_BASE_HI__SHIFT 0x0 3074 #define UVD_RB_BASE_HI4__RB_BASE_HI_MASK 0xFFFFFFFFL 3075 //UVD_RB_SIZE4 3076 #define UVD_RB_SIZE4__RB_SIZE__SHIFT 0x4 3077 #define UVD_RB_SIZE4__RB_SIZE_MASK 0x007FFFF0L 3078 //UVD_RB_RPTR4 3079 #define UVD_RB_RPTR4__RB_RPTR__SHIFT 0x4 3080 #define UVD_RB_RPTR4__RB_RPTR_MASK 0x007FFFF0L 3081 //UVD_LMI_MC_CREDITS 3082 #define UVD_LMI_MC_CREDITS__UVD_RD_CREDITS__SHIFT 0x0 3083 #define UVD_LMI_MC_CREDITS__UVD_WR_CREDITS__SHIFT 0x8 3084 #define UVD_LMI_MC_CREDITS__UMC_RD_CREDITS__SHIFT 0x10 3085 #define UVD_LMI_MC_CREDITS__UMC_WR_CREDITS__SHIFT 0x18 3086 #define UVD_LMI_MC_CREDITS__UVD_RD_CREDITS_MASK 0x0000003FL 3087 #define UVD_LMI_MC_CREDITS__UVD_WR_CREDITS_MASK 0x00003F00L 3088 #define UVD_LMI_MC_CREDITS__UMC_RD_CREDITS_MASK 0x003F0000L 3089 #define UVD_LMI_MC_CREDITS__UMC_WR_CREDITS_MASK 0x3F000000L 3090 //UVD_RBC_BUF_STATUS 3091 #define UVD_RBC_BUF_STATUS__RB_BUF_VALID__SHIFT 0x0 3092 #define UVD_RBC_BUF_STATUS__IB_BUF_VALID__SHIFT 0x8 3093 #define UVD_RBC_BUF_STATUS__RB_BUF_RD_ADDR__SHIFT 0x10 3094 #define UVD_RBC_BUF_STATUS__IB_BUF_RD_ADDR__SHIFT 0x13 3095 #define UVD_RBC_BUF_STATUS__RB_BUF_WR_ADDR__SHIFT 0x16 3096 #define UVD_RBC_BUF_STATUS__IB_BUF_WR_ADDR__SHIFT 0x19 3097 #define UVD_RBC_BUF_STATUS__RB_BUF_VALID_MASK 0x000000FFL 3098 #define UVD_RBC_BUF_STATUS__IB_BUF_VALID_MASK 0x0000FF00L 3099 #define UVD_RBC_BUF_STATUS__RB_BUF_RD_ADDR_MASK 0x00070000L 3100 #define UVD_RBC_BUF_STATUS__IB_BUF_RD_ADDR_MASK 0x00380000L 3101 #define UVD_RBC_BUF_STATUS__RB_BUF_WR_ADDR_MASK 0x01C00000L 3102 #define UVD_RBC_BUF_STATUS__IB_BUF_WR_ADDR_MASK 0x0E000000L 3103 //UVD_RBC_IB_SIZE_UPDATE 3104 #define UVD_RBC_IB_SIZE_UPDATE__REMAIN_IB_SIZE__SHIFT 0x4 3105 #define UVD_RBC_IB_SIZE_UPDATE__REMAIN_IB_SIZE_MASK 0x007FFFF0L 3106 //UVD_RBC_BDM_PRE 3107 #define UVD_RBC_BDM_PRE__BDM_ENABLE__SHIFT 0x0 3108 #define UVD_RBC_BDM_PRE__BDM_ENABLE_MASK 0x00000001L 3109 //CG_TIMESTAMP_LOW 3110 #define CG_TIMESTAMP_LOW__CG_LOW__SHIFT 0x0 3111 #define CG_TIMESTAMP_LOW__CG_LOW_MASK 0xFFFFFFFFL 3112 //CG_TIMESTAMP_HIGH 3113 #define CG_TIMESTAMP_HIGH__CG_HIGH__SHIFT 0x0 3114 #define CG_TIMESTAMP_HIGH__CG_HIGH_MASK 0xFFFFFFFFL 3115 //UVD_UMC_UVD_CTL_CMD 3116 #define UVD_UMC_UVD_CTL_CMD__CMC_REQ__SHIFT 0x0 3117 #define UVD_UMC_UVD_CTL_CMD__CMC_REQ_MASK 0x00000001L 3118 //UVD_UMC_UVD_BLOCK_REQ 3119 #define UVD_UMC_UVD_BLOCK_REQ__CMC_BLOCK_REQ__SHIFT 0x0 3120 #define UVD_UMC_UVD_BLOCK_REQ__CMC_BLOCK_REQ_MASK 0x00000001L 3121 //UVD_RBC_CXW_RELEASE 3122 #define UVD_RBC_CXW_RELEASE__SOFT_RELEASE_RBC__SHIFT 0x0 3123 #define UVD_RBC_CXW_RELEASE__SOFT_RELEASE_RBC_MASK 0x00000001L 3124 //UVD_YBASE 3125 #define UVD_YBASE__DUM__SHIFT 0x0 3126 #define UVD_YBASE__DUM_MASK 0xFFFFFFFFL 3127 //UVD_UVBASE 3128 #define UVD_UVBASE__DUM__SHIFT 0x0 3129 #define UVD_UVBASE__DUM_MASK 0xFFFFFFFFL 3130 //UVD_PITCH 3131 #define UVD_PITCH__DUM__SHIFT 0x0 3132 #define UVD_PITCH__DUM_MASK 0xFFFFFFFFL 3133 //UVD_WIDTH 3134 #define UVD_WIDTH__DUM__SHIFT 0x0 3135 #define UVD_WIDTH__DUM_MASK 0xFFFFFFFFL 3136 //UVD_HEIGHT 3137 #define UVD_HEIGHT__DUM__SHIFT 0x0 3138 #define UVD_HEIGHT__DUM_MASK 0xFFFFFFFFL 3139 //UVD_PICCOUNT 3140 #define UVD_PICCOUNT__DUM__SHIFT 0x0 3141 #define UVD_PICCOUNT__DUM_MASK 0xFFFFFFFFL 3142 3143 3144 // addressBlock: uvd0_uvdnpdec 3145 //UVD_SEMA_ADDR_LOW 3146 #define UVD_SEMA_ADDR_LOW__ADDR_26_3__SHIFT 0x0 3147 #define UVD_SEMA_ADDR_LOW__ADDR_26_3_MASK 0x00FFFFFFL 3148 //UVD_SEMA_ADDR_HIGH 3149 #define UVD_SEMA_ADDR_HIGH__ADDR_47_27__SHIFT 0x0 3150 #define UVD_SEMA_ADDR_HIGH__ADDR_47_27_MASK 0x001FFFFFL 3151 //UVD_SEMA_CMD 3152 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0 3153 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4 3154 #define UVD_SEMA_CMD__MODE__SHIFT 0x6 3155 #define UVD_SEMA_CMD__VMID_EN__SHIFT 0x7 3156 #define UVD_SEMA_CMD__VMID__SHIFT 0x8 3157 #define UVD_SEMA_CMD__REQ_CMD_MASK 0x0000000FL 3158 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x00000030L 3159 #define UVD_SEMA_CMD__MODE_MASK 0x00000040L 3160 #define UVD_SEMA_CMD__VMID_EN_MASK 0x00000080L 3161 #define UVD_SEMA_CMD__VMID_MASK 0x00000F00L 3162 //UVD_GPCOM_VCPU_CMD 3163 #define UVD_GPCOM_VCPU_CMD__CMD_SEND__SHIFT 0x0 3164 #define UVD_GPCOM_VCPU_CMD__CMD__SHIFT 0x1 3165 #define UVD_GPCOM_VCPU_CMD__CMD_SOURCE__SHIFT 0x1f 3166 #define UVD_GPCOM_VCPU_CMD__CMD_SEND_MASK 0x00000001L 3167 #define UVD_GPCOM_VCPU_CMD__CMD_MASK 0x7FFFFFFEL 3168 #define UVD_GPCOM_VCPU_CMD__CMD_SOURCE_MASK 0x80000000L 3169 //UVD_GPCOM_VCPU_DATA0 3170 #define UVD_GPCOM_VCPU_DATA0__DATA0__SHIFT 0x0 3171 #define UVD_GPCOM_VCPU_DATA0__DATA0_MASK 0xFFFFFFFFL 3172 //UVD_GPCOM_VCPU_DATA1 3173 #define UVD_GPCOM_VCPU_DATA1__DATA1__SHIFT 0x0 3174 #define UVD_GPCOM_VCPU_DATA1__DATA1_MASK 0xFFFFFFFFL 3175 //UVD_ENGINE_CNTL 3176 #define UVD_ENGINE_CNTL__ENGINE_START__SHIFT 0x0 3177 #define UVD_ENGINE_CNTL__ENGINE_START_MODE__SHIFT 0x1 3178 #define UVD_ENGINE_CNTL__NJ_PF_HANDLE_DISABLE__SHIFT 0x2 3179 #define UVD_ENGINE_CNTL__ENGINE_START_MASK 0x00000001L 3180 #define UVD_ENGINE_CNTL__ENGINE_START_MODE_MASK 0x00000002L 3181 #define UVD_ENGINE_CNTL__NJ_PF_HANDLE_DISABLE_MASK 0x00000004L 3182 //UVD_SUVD_CGC_GATE 3183 #define UVD_SUVD_CGC_GATE__SRE__SHIFT 0x0 3184 #define UVD_SUVD_CGC_GATE__SIT__SHIFT 0x1 3185 #define UVD_SUVD_CGC_GATE__SMP__SHIFT 0x2 3186 #define UVD_SUVD_CGC_GATE__SCM__SHIFT 0x3 3187 #define UVD_SUVD_CGC_GATE__SDB__SHIFT 0x4 3188 #define UVD_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 3189 #define UVD_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 3190 #define UVD_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 3191 #define UVD_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 3192 #define UVD_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 3193 #define UVD_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa 3194 #define UVD_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb 3195 #define UVD_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc 3196 #define UVD_SUVD_CGC_GATE__SCLR__SHIFT 0xd 3197 #define UVD_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe 3198 #define UVD_SUVD_CGC_GATE__ENT__SHIFT 0xf 3199 #define UVD_SUVD_CGC_GATE__IME__SHIFT 0x10 3200 #define UVD_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11 3201 #define UVD_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT 0x12 3202 #define UVD_SUVD_CGC_GATE__SITE__SHIFT 0x13 3203 #define UVD_SUVD_CGC_GATE__SRE_VP9__SHIFT 0x14 3204 #define UVD_SUVD_CGC_GATE__SCM_VP9__SHIFT 0x15 3205 #define UVD_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16 3206 #define UVD_SUVD_CGC_GATE__SDB_VP9__SHIFT 0x17 3207 #define UVD_SUVD_CGC_GATE__IME_HEVC__SHIFT 0x18 3208 #define UVD_SUVD_CGC_GATE__EFC__SHIFT 0x19 3209 #define UVD_SUVD_CGC_GATE__SRE_MASK 0x00000001L 3210 #define UVD_SUVD_CGC_GATE__SIT_MASK 0x00000002L 3211 #define UVD_SUVD_CGC_GATE__SMP_MASK 0x00000004L 3212 #define UVD_SUVD_CGC_GATE__SCM_MASK 0x00000008L 3213 #define UVD_SUVD_CGC_GATE__SDB_MASK 0x00000010L 3214 #define UVD_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L 3215 #define UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L 3216 #define UVD_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L 3217 #define UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L 3218 #define UVD_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L 3219 #define UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L 3220 #define UVD_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L 3221 #define UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L 3222 #define UVD_SUVD_CGC_GATE__SCLR_MASK 0x00002000L 3223 #define UVD_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L 3224 #define UVD_SUVD_CGC_GATE__ENT_MASK 0x00008000L 3225 #define UVD_SUVD_CGC_GATE__IME_MASK 0x00010000L 3226 #define UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L 3227 #define UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L 3228 #define UVD_SUVD_CGC_GATE__SITE_MASK 0x00080000L 3229 #define UVD_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L 3230 #define UVD_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L 3231 #define UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L 3232 #define UVD_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L 3233 #define UVD_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L 3234 #define UVD_SUVD_CGC_GATE__EFC_MASK 0x02000000L 3235 //UVD_SUVD_CGC_STATUS 3236 #define UVD_SUVD_CGC_STATUS__SRE_VCLK__SHIFT 0x0 3237 #define UVD_SUVD_CGC_STATUS__SRE_DCLK__SHIFT 0x1 3238 #define UVD_SUVD_CGC_STATUS__SIT_DCLK__SHIFT 0x2 3239 #define UVD_SUVD_CGC_STATUS__SMP_DCLK__SHIFT 0x3 3240 #define UVD_SUVD_CGC_STATUS__SCM_DCLK__SHIFT 0x4 3241 #define UVD_SUVD_CGC_STATUS__SDB_DCLK__SHIFT 0x5 3242 #define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK__SHIFT 0x6 3243 #define UVD_SUVD_CGC_STATUS__SRE_HEVC_VCLK__SHIFT 0x7 3244 #define UVD_SUVD_CGC_STATUS__SIT_H264_DCLK__SHIFT 0x8 3245 #define UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK__SHIFT 0x9 3246 #define UVD_SUVD_CGC_STATUS__SCM_H264_DCLK__SHIFT 0xa 3247 #define UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK__SHIFT 0xb 3248 #define UVD_SUVD_CGC_STATUS__SDB_H264_DCLK__SHIFT 0xc 3249 #define UVD_SUVD_CGC_STATUS__SDB_HEVC_DCLK__SHIFT 0xd 3250 #define UVD_SUVD_CGC_STATUS__SCLR_DCLK__SHIFT 0xe 3251 #define UVD_SUVD_CGC_STATUS__UVD_SC__SHIFT 0xf 3252 #define UVD_SUVD_CGC_STATUS__ENT_DCLK__SHIFT 0x10 3253 #define UVD_SUVD_CGC_STATUS__IME_DCLK__SHIFT 0x11 3254 #define UVD_SUVD_CGC_STATUS__SIT_HEVC_DEC_DCLK__SHIFT 0x12 3255 #define UVD_SUVD_CGC_STATUS__SIT_HEVC_ENC_DCLK__SHIFT 0x13 3256 #define UVD_SUVD_CGC_STATUS__SITE_DCLK__SHIFT 0x14 3257 #define UVD_SUVD_CGC_STATUS__SITE_HEVC_DCLK__SHIFT 0x15 3258 #define UVD_SUVD_CGC_STATUS__SITE_HEVC_ENC_DCLK__SHIFT 0x16 3259 #define UVD_SUVD_CGC_STATUS__SRE_VP9_VCLK__SHIFT 0x17 3260 #define UVD_SUVD_CGC_STATUS__SCM_VP9_VCLK__SHIFT 0x18 3261 #define UVD_SUVD_CGC_STATUS__SIT_VP9_DEC_DCLK__SHIFT 0x19 3262 #define UVD_SUVD_CGC_STATUS__SDB_VP9_DCLK__SHIFT 0x1a 3263 #define UVD_SUVD_CGC_STATUS__IME_HEVC_DCLK__SHIFT 0x1b 3264 #define UVD_SUVD_CGC_STATUS__EFC_DCLK__SHIFT 0x1c 3265 #define UVD_SUVD_CGC_STATUS__SRE_VCLK_MASK 0x00000001L 3266 #define UVD_SUVD_CGC_STATUS__SRE_DCLK_MASK 0x00000002L 3267 #define UVD_SUVD_CGC_STATUS__SIT_DCLK_MASK 0x00000004L 3268 #define UVD_SUVD_CGC_STATUS__SMP_DCLK_MASK 0x00000008L 3269 #define UVD_SUVD_CGC_STATUS__SCM_DCLK_MASK 0x00000010L 3270 #define UVD_SUVD_CGC_STATUS__SDB_DCLK_MASK 0x00000020L 3271 #define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK_MASK 0x00000040L 3272 #define UVD_SUVD_CGC_STATUS__SRE_HEVC_VCLK_MASK 0x00000080L 3273 #define UVD_SUVD_CGC_STATUS__SIT_H264_DCLK_MASK 0x00000100L 3274 #define UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK_MASK 0x00000200L 3275 #define UVD_SUVD_CGC_STATUS__SCM_H264_DCLK_MASK 0x00000400L 3276 #define UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK_MASK 0x00000800L 3277 #define UVD_SUVD_CGC_STATUS__SDB_H264_DCLK_MASK 0x00001000L 3278 #define UVD_SUVD_CGC_STATUS__SDB_HEVC_DCLK_MASK 0x00002000L 3279 #define UVD_SUVD_CGC_STATUS__SCLR_DCLK_MASK 0x00004000L 3280 #define UVD_SUVD_CGC_STATUS__UVD_SC_MASK 0x00008000L 3281 #define UVD_SUVD_CGC_STATUS__ENT_DCLK_MASK 0x00010000L 3282 #define UVD_SUVD_CGC_STATUS__IME_DCLK_MASK 0x00020000L 3283 #define UVD_SUVD_CGC_STATUS__SIT_HEVC_DEC_DCLK_MASK 0x00040000L 3284 #define UVD_SUVD_CGC_STATUS__SIT_HEVC_ENC_DCLK_MASK 0x00080000L 3285 #define UVD_SUVD_CGC_STATUS__SITE_DCLK_MASK 0x00100000L 3286 #define UVD_SUVD_CGC_STATUS__SITE_HEVC_DCLK_MASK 0x00200000L 3287 #define UVD_SUVD_CGC_STATUS__SITE_HEVC_ENC_DCLK_MASK 0x00400000L 3288 #define UVD_SUVD_CGC_STATUS__SRE_VP9_VCLK_MASK 0x00800000L 3289 #define UVD_SUVD_CGC_STATUS__SCM_VP9_VCLK_MASK 0x01000000L 3290 #define UVD_SUVD_CGC_STATUS__SIT_VP9_DEC_DCLK_MASK 0x02000000L 3291 #define UVD_SUVD_CGC_STATUS__SDB_VP9_DCLK_MASK 0x04000000L 3292 #define UVD_SUVD_CGC_STATUS__IME_HEVC_DCLK_MASK 0x08000000L 3293 #define UVD_SUVD_CGC_STATUS__EFC_DCLK_MASK 0x10000000L 3294 //UVD_SUVD_CGC_CTRL 3295 #define UVD_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 3296 #define UVD_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 3297 #define UVD_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 3298 #define UVD_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 3299 #define UVD_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 3300 #define UVD_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 3301 #define UVD_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 3302 #define UVD_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 3303 #define UVD_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 3304 #define UVD_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9 3305 #define UVD_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa 3306 #define UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L 3307 #define UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L 3308 #define UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L 3309 #define UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L 3310 #define UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L 3311 #define UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L 3312 #define UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L 3313 #define UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L 3314 #define UVD_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L 3315 #define UVD_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L 3316 #define UVD_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L 3317 //UVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW 3318 #define UVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3319 #define UVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3320 //UVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH 3321 #define UVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3322 #define UVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3323 //UVD_LMI_VCPU_CACHE8_64BIT_BAR_LOW 3324 #define UVD_LMI_VCPU_CACHE8_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3325 #define UVD_LMI_VCPU_CACHE8_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3326 //UVD_LMI_VCPU_CACHE8_64BIT_BAR_HIGH 3327 #define UVD_LMI_VCPU_CACHE8_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3328 #define UVD_LMI_VCPU_CACHE8_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3329 //UVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW 3330 #define UVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3331 #define UVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3332 //UVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH 3333 #define UVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3334 #define UVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3335 //UVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW 3336 #define UVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3337 #define UVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3338 //UVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH 3339 #define UVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3340 #define UVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3341 //UVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW 3342 #define UVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3343 #define UVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3344 //UVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH 3345 #define UVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3346 #define UVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3347 //UVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW 3348 #define UVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3349 #define UVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3350 //UVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH 3351 #define UVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3352 #define UVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3353 //UVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW 3354 #define UVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3355 #define UVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3356 //UVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH 3357 #define UVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3358 #define UVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3359 //UVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW 3360 #define UVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3361 #define UVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3362 //UVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH 3363 #define UVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3364 #define UVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3365 //UVD_SCRATCH_NP 3366 #define UVD_SCRATCH_NP__DATA__SHIFT 0x0 3367 #define UVD_SCRATCH_NP__DATA_MASK 0xFFFFFFFFL 3368 //UVD_NO_OP 3369 #define UVD_NO_OP__NO_OP__SHIFT 0x0 3370 #define UVD_NO_OP__NO_OP_MASK 0xFFFFFFFFL 3371 //MDM_DMA_CMD 3372 #define MDM_DMA_CMD__MDM_DMA_CMD__SHIFT 0x0 3373 #define MDM_DMA_CMD__MDM_DMA_CMD_MASK 0xFFFFFFFFL 3374 //MDM_DMA_STATUS 3375 #define MDM_DMA_STATUS__SDB_DMA_WR_BUSY__SHIFT 0x0 3376 #define MDM_DMA_STATUS__SCM_DMA_WR_BUSY__SHIFT 0x1 3377 #define MDM_DMA_STATUS__SCM_DMA_RD_BUSY__SHIFT 0x2 3378 #define MDM_DMA_STATUS__RB_DMA_WR_BUSY__SHIFT 0x3 3379 #define MDM_DMA_STATUS__RB_DMA_RD_BUSY__SHIFT 0x4 3380 #define MDM_DMA_STATUS__SDB_DMA_RD_BUSY__SHIFT 0x5 3381 #define MDM_DMA_STATUS__SCLR_DMA_WR_BUSY__SHIFT 0x6 3382 #define MDM_DMA_STATUS__SDB_DMA_WR_BUSY_MASK 0x00000001L 3383 #define MDM_DMA_STATUS__SCM_DMA_WR_BUSY_MASK 0x00000002L 3384 #define MDM_DMA_STATUS__SCM_DMA_RD_BUSY_MASK 0x00000004L 3385 #define MDM_DMA_STATUS__RB_DMA_WR_BUSY_MASK 0x00000008L 3386 #define MDM_DMA_STATUS__RB_DMA_RD_BUSY_MASK 0x00000010L 3387 #define MDM_DMA_STATUS__SDB_DMA_RD_BUSY_MASK 0x00000020L 3388 #define MDM_DMA_STATUS__SCLR_DMA_WR_BUSY_MASK 0x00000040L 3389 //MDM_DMA_CTL 3390 #define MDM_DMA_CTL__MDM_BYPASS__SHIFT 0x0 3391 #define MDM_DMA_CTL__FOUR_CMD__SHIFT 0x1 3392 #define MDM_DMA_CTL__ENCODE_MODE__SHIFT 0x2 3393 #define MDM_DMA_CTL__VP9_DEC_MODE__SHIFT 0x3 3394 #define MDM_DMA_CTL__SW_DRST__SHIFT 0x1f 3395 #define MDM_DMA_CTL__MDM_BYPASS_MASK 0x00000001L 3396 #define MDM_DMA_CTL__FOUR_CMD_MASK 0x00000002L 3397 #define MDM_DMA_CTL__ENCODE_MODE_MASK 0x00000004L 3398 #define MDM_DMA_CTL__VP9_DEC_MODE_MASK 0x00000008L 3399 #define MDM_DMA_CTL__SW_DRST_MASK 0x80000000L 3400 //MDM_ENC_PIPE_BUSY 3401 #define MDM_ENC_PIPE_BUSY__IME_BUSY__SHIFT 0x0 3402 #define MDM_ENC_PIPE_BUSY__SMP_BUSY__SHIFT 0x1 3403 #define MDM_ENC_PIPE_BUSY__SIT_BUSY__SHIFT 0x2 3404 #define MDM_ENC_PIPE_BUSY__SDB_BUSY__SHIFT 0x3 3405 #define MDM_ENC_PIPE_BUSY__ENT_BUSY__SHIFT 0x4 3406 #define MDM_ENC_PIPE_BUSY__ENT_HEADER_BUSY__SHIFT 0x5 3407 #define MDM_ENC_PIPE_BUSY__LCM_BUSY__SHIFT 0x6 3408 #define MDM_ENC_PIPE_BUSY__MDM_RD_CUR_BUSY__SHIFT 0x7 3409 #define MDM_ENC_PIPE_BUSY__MDM_RD_REF_BUSY__SHIFT 0x8 3410 #define MDM_ENC_PIPE_BUSY__MDM_RD_GEN_BUSY__SHIFT 0x9 3411 #define MDM_ENC_PIPE_BUSY__MDM_WR_RECON_BUSY__SHIFT 0xa 3412 #define MDM_ENC_PIPE_BUSY__MDM_WR_GEN_BUSY__SHIFT 0xb 3413 #define MDM_ENC_PIPE_BUSY__MDM_EFC_BUSY__SHIFT 0xc 3414 #define MDM_ENC_PIPE_BUSY__MDM_EFC_PROGRAM_BUSY__SHIFT 0xd 3415 #define MDM_ENC_PIPE_BUSY__MIF_RD_CUR_BUSY__SHIFT 0x10 3416 #define MDM_ENC_PIPE_BUSY__MIF_RD_REF0_BUSY__SHIFT 0x11 3417 #define MDM_ENC_PIPE_BUSY__MIF_WR_GEN0_BUSY__SHIFT 0x12 3418 #define MDM_ENC_PIPE_BUSY__MIF_RD_GEN0_BUSY__SHIFT 0x13 3419 #define MDM_ENC_PIPE_BUSY__MIF_WR_GEN1_BUSY__SHIFT 0x14 3420 #define MDM_ENC_PIPE_BUSY__MIF_RD_GEN1_BUSY__SHIFT 0x15 3421 #define MDM_ENC_PIPE_BUSY__MIF_WR_BSP0_BUSY__SHIFT 0x16 3422 #define MDM_ENC_PIPE_BUSY__MIF_WR_BSP1_BUSY__SHIFT 0x17 3423 #define MDM_ENC_PIPE_BUSY__MIF_RD_BSD0_BUSY__SHIFT 0x18 3424 #define MDM_ENC_PIPE_BUSY__MIF_RD_BSD1_BUSY__SHIFT 0x19 3425 #define MDM_ENC_PIPE_BUSY__MIF_RD_BSD2_BUSY__SHIFT 0x1a 3426 #define MDM_ENC_PIPE_BUSY__MIF_RD_BSD3_BUSY__SHIFT 0x1b 3427 #define MDM_ENC_PIPE_BUSY__MIF_RD_BSD4_BUSY__SHIFT 0x1c 3428 #define MDM_ENC_PIPE_BUSY__IME_BUSY_MASK 0x00000001L 3429 #define MDM_ENC_PIPE_BUSY__SMP_BUSY_MASK 0x00000002L 3430 #define MDM_ENC_PIPE_BUSY__SIT_BUSY_MASK 0x00000004L 3431 #define MDM_ENC_PIPE_BUSY__SDB_BUSY_MASK 0x00000008L 3432 #define MDM_ENC_PIPE_BUSY__ENT_BUSY_MASK 0x00000010L 3433 #define MDM_ENC_PIPE_BUSY__ENT_HEADER_BUSY_MASK 0x00000020L 3434 #define MDM_ENC_PIPE_BUSY__LCM_BUSY_MASK 0x00000040L 3435 #define MDM_ENC_PIPE_BUSY__MDM_RD_CUR_BUSY_MASK 0x00000080L 3436 #define MDM_ENC_PIPE_BUSY__MDM_RD_REF_BUSY_MASK 0x00000100L 3437 #define MDM_ENC_PIPE_BUSY__MDM_RD_GEN_BUSY_MASK 0x00000200L 3438 #define MDM_ENC_PIPE_BUSY__MDM_WR_RECON_BUSY_MASK 0x00000400L 3439 #define MDM_ENC_PIPE_BUSY__MDM_WR_GEN_BUSY_MASK 0x00000800L 3440 #define MDM_ENC_PIPE_BUSY__MDM_EFC_BUSY_MASK 0x00001000L 3441 #define MDM_ENC_PIPE_BUSY__MDM_EFC_PROGRAM_BUSY_MASK 0x00002000L 3442 #define MDM_ENC_PIPE_BUSY__MIF_RD_CUR_BUSY_MASK 0x00010000L 3443 #define MDM_ENC_PIPE_BUSY__MIF_RD_REF0_BUSY_MASK 0x00020000L 3444 #define MDM_ENC_PIPE_BUSY__MIF_WR_GEN0_BUSY_MASK 0x00040000L 3445 #define MDM_ENC_PIPE_BUSY__MIF_RD_GEN0_BUSY_MASK 0x00080000L 3446 #define MDM_ENC_PIPE_BUSY__MIF_WR_GEN1_BUSY_MASK 0x00100000L 3447 #define MDM_ENC_PIPE_BUSY__MIF_RD_GEN1_BUSY_MASK 0x00200000L 3448 #define MDM_ENC_PIPE_BUSY__MIF_WR_BSP0_BUSY_MASK 0x00400000L 3449 #define MDM_ENC_PIPE_BUSY__MIF_WR_BSP1_BUSY_MASK 0x00800000L 3450 #define MDM_ENC_PIPE_BUSY__MIF_RD_BSD0_BUSY_MASK 0x01000000L 3451 #define MDM_ENC_PIPE_BUSY__MIF_RD_BSD1_BUSY_MASK 0x02000000L 3452 #define MDM_ENC_PIPE_BUSY__MIF_RD_BSD2_BUSY_MASK 0x04000000L 3453 #define MDM_ENC_PIPE_BUSY__MIF_RD_BSD3_BUSY_MASK 0x08000000L 3454 #define MDM_ENC_PIPE_BUSY__MIF_RD_BSD4_BUSY_MASK 0x10000000L 3455 //MDM_WIG_PIPE_BUSY 3456 #define MDM_WIG_PIPE_BUSY__WIG_TBE_BUSY__SHIFT 0x0 3457 #define MDM_WIG_PIPE_BUSY__WIG_ENT_BUSY__SHIFT 0x1 3458 #define MDM_WIG_PIPE_BUSY__WIG_ENT_HEADER_BUSY__SHIFT 0x2 3459 #define MDM_WIG_PIPE_BUSY__WIG_ENT_HEADER_FIFO_FULL__SHIFT 0x3 3460 #define MDM_WIG_PIPE_BUSY__LCM_BUSY__SHIFT 0x4 3461 #define MDM_WIG_PIPE_BUSY__MDM_RD_CUR_BUSY__SHIFT 0x5 3462 #define MDM_WIG_PIPE_BUSY__MDM_RD_REF_BUSY__SHIFT 0x6 3463 #define MDM_WIG_PIPE_BUSY__MDM_RD_GEN_BUSY__SHIFT 0x7 3464 #define MDM_WIG_PIPE_BUSY__MDM_WR_RECON_BUSY__SHIFT 0x8 3465 #define MDM_WIG_PIPE_BUSY__MDM_WR_GEN_BUSY__SHIFT 0x9 3466 #define MDM_WIG_PIPE_BUSY__MIF_RD_CUR_BUSY__SHIFT 0xa 3467 #define MDM_WIG_PIPE_BUSY__MIF_RD_REF0_BUSY__SHIFT 0xb 3468 #define MDM_WIG_PIPE_BUSY__MIF_WR_GEN0_BUSY__SHIFT 0xc 3469 #define MDM_WIG_PIPE_BUSY__MIF_RD_GEN0_BUSY__SHIFT 0xd 3470 #define MDM_WIG_PIPE_BUSY__MIF_WR_GEN1_BUSY__SHIFT 0xe 3471 #define MDM_WIG_PIPE_BUSY__MIF_RD_GEN1_BUSY__SHIFT 0xf 3472 #define MDM_WIG_PIPE_BUSY__MIF_WR_BSP0_BUSY__SHIFT 0x10 3473 #define MDM_WIG_PIPE_BUSY__MIF_WR_BSP1_BUSY__SHIFT 0x11 3474 #define MDM_WIG_PIPE_BUSY__MIF_RD_BSD0_BUSY__SHIFT 0x12 3475 #define MDM_WIG_PIPE_BUSY__MIF_RD_BSD1_BUSY__SHIFT 0x13 3476 #define MDM_WIG_PIPE_BUSY__MIF_RD_BSD2_BUSY__SHIFT 0x14 3477 #define MDM_WIG_PIPE_BUSY__MIF_RD_BSD3_BUSY__SHIFT 0x15 3478 #define MDM_WIG_PIPE_BUSY__MIF_RD_BSD4_BUSY__SHIFT 0x16 3479 #define MDM_WIG_PIPE_BUSY__MIF_RD_BSD5_BUSY__SHIFT 0x17 3480 #define MDM_WIG_PIPE_BUSY__MIF_WR_BSP2_BUSY__SHIFT 0x18 3481 #define MDM_WIG_PIPE_BUSY__MIF_WR_BSP3_BUSY__SHIFT 0x19 3482 #define MDM_WIG_PIPE_BUSY__LCM_BSP0_NOT_EMPTY__SHIFT 0x1a 3483 #define MDM_WIG_PIPE_BUSY__LCM_BSP1_NOT_EMPTY__SHIFT 0x1b 3484 #define MDM_WIG_PIPE_BUSY__LCM_BSP2_NOT_EMPTY__SHIFT 0x1c 3485 #define MDM_WIG_PIPE_BUSY__LCM_BSP3_NOT_EMPTY__SHIFT 0x1d 3486 #define MDM_WIG_PIPE_BUSY__WIG_TBE_BUSY_MASK 0x00000001L 3487 #define MDM_WIG_PIPE_BUSY__WIG_ENT_BUSY_MASK 0x00000002L 3488 #define MDM_WIG_PIPE_BUSY__WIG_ENT_HEADER_BUSY_MASK 0x00000004L 3489 #define MDM_WIG_PIPE_BUSY__WIG_ENT_HEADER_FIFO_FULL_MASK 0x00000008L 3490 #define MDM_WIG_PIPE_BUSY__LCM_BUSY_MASK 0x00000010L 3491 #define MDM_WIG_PIPE_BUSY__MDM_RD_CUR_BUSY_MASK 0x00000020L 3492 #define MDM_WIG_PIPE_BUSY__MDM_RD_REF_BUSY_MASK 0x00000040L 3493 #define MDM_WIG_PIPE_BUSY__MDM_RD_GEN_BUSY_MASK 0x00000080L 3494 #define MDM_WIG_PIPE_BUSY__MDM_WR_RECON_BUSY_MASK 0x00000100L 3495 #define MDM_WIG_PIPE_BUSY__MDM_WR_GEN_BUSY_MASK 0x00000200L 3496 #define MDM_WIG_PIPE_BUSY__MIF_RD_CUR_BUSY_MASK 0x00000400L 3497 #define MDM_WIG_PIPE_BUSY__MIF_RD_REF0_BUSY_MASK 0x00000800L 3498 #define MDM_WIG_PIPE_BUSY__MIF_WR_GEN0_BUSY_MASK 0x00001000L 3499 #define MDM_WIG_PIPE_BUSY__MIF_RD_GEN0_BUSY_MASK 0x00002000L 3500 #define MDM_WIG_PIPE_BUSY__MIF_WR_GEN1_BUSY_MASK 0x00004000L 3501 #define MDM_WIG_PIPE_BUSY__MIF_RD_GEN1_BUSY_MASK 0x00008000L 3502 #define MDM_WIG_PIPE_BUSY__MIF_WR_BSP0_BUSY_MASK 0x00010000L 3503 #define MDM_WIG_PIPE_BUSY__MIF_WR_BSP1_BUSY_MASK 0x00020000L 3504 #define MDM_WIG_PIPE_BUSY__MIF_RD_BSD0_BUSY_MASK 0x00040000L 3505 #define MDM_WIG_PIPE_BUSY__MIF_RD_BSD1_BUSY_MASK 0x00080000L 3506 #define MDM_WIG_PIPE_BUSY__MIF_RD_BSD2_BUSY_MASK 0x00100000L 3507 #define MDM_WIG_PIPE_BUSY__MIF_RD_BSD3_BUSY_MASK 0x00200000L 3508 #define MDM_WIG_PIPE_BUSY__MIF_RD_BSD4_BUSY_MASK 0x00400000L 3509 #define MDM_WIG_PIPE_BUSY__MIF_RD_BSD5_BUSY_MASK 0x00800000L 3510 #define MDM_WIG_PIPE_BUSY__MIF_WR_BSP2_BUSY_MASK 0x01000000L 3511 #define MDM_WIG_PIPE_BUSY__MIF_WR_BSP3_BUSY_MASK 0x02000000L 3512 #define MDM_WIG_PIPE_BUSY__LCM_BSP0_NOT_EMPTY_MASK 0x04000000L 3513 #define MDM_WIG_PIPE_BUSY__LCM_BSP1_NOT_EMPTY_MASK 0x08000000L 3514 #define MDM_WIG_PIPE_BUSY__LCM_BSP2_NOT_EMPTY_MASK 0x10000000L 3515 #define MDM_WIG_PIPE_BUSY__LCM_BSP3_NOT_EMPTY_MASK 0x20000000L 3516 //UVD_VERSION 3517 #define UVD_VERSION__MINOR_VERSION__SHIFT 0x0 3518 #define UVD_VERSION__MAJOR_VERSION__SHIFT 0x10 3519 #define UVD_VERSION__MINOR_VERSION_MASK 0x0000FFFFL 3520 #define UVD_VERSION__MAJOR_VERSION_MASK 0xFFFF0000L 3521 //UVD_GP_SCRATCH8 3522 #define UVD_GP_SCRATCH8__DATA__SHIFT 0x0 3523 #define UVD_GP_SCRATCH8__DATA_MASK 0xFFFFFFFFL 3524 //UVD_GP_SCRATCH9 3525 #define UVD_GP_SCRATCH9__DATA__SHIFT 0x0 3526 #define UVD_GP_SCRATCH9__DATA_MASK 0xFFFFFFFFL 3527 //UVD_GP_SCRATCH10 3528 #define UVD_GP_SCRATCH10__DATA__SHIFT 0x0 3529 #define UVD_GP_SCRATCH10__DATA_MASK 0xFFFFFFFFL 3530 //UVD_GP_SCRATCH11 3531 #define UVD_GP_SCRATCH11__DATA__SHIFT 0x0 3532 #define UVD_GP_SCRATCH11__DATA_MASK 0xFFFFFFFFL 3533 //UVD_GP_SCRATCH12 3534 #define UVD_GP_SCRATCH12__DATA__SHIFT 0x0 3535 #define UVD_GP_SCRATCH12__DATA_MASK 0xFFFFFFFFL 3536 //UVD_GP_SCRATCH13 3537 #define UVD_GP_SCRATCH13__DATA__SHIFT 0x0 3538 #define UVD_GP_SCRATCH13__DATA_MASK 0xFFFFFFFFL 3539 //UVD_GP_SCRATCH14 3540 #define UVD_GP_SCRATCH14__DATA__SHIFT 0x0 3541 #define UVD_GP_SCRATCH14__DATA_MASK 0xFFFFFFFFL 3542 //UVD_GP_SCRATCH15 3543 #define UVD_GP_SCRATCH15__DATA__SHIFT 0x0 3544 #define UVD_GP_SCRATCH15__DATA_MASK 0xFFFFFFFFL 3545 //UVD_GP_SCRATCH16 3546 #define UVD_GP_SCRATCH16__DATA__SHIFT 0x0 3547 #define UVD_GP_SCRATCH16__DATA_MASK 0xFFFFFFFFL 3548 //UVD_GP_SCRATCH17 3549 #define UVD_GP_SCRATCH17__DATA__SHIFT 0x0 3550 #define UVD_GP_SCRATCH17__DATA_MASK 0xFFFFFFFFL 3551 //UVD_GP_SCRATCH18 3552 #define UVD_GP_SCRATCH18__DATA__SHIFT 0x0 3553 #define UVD_GP_SCRATCH18__DATA_MASK 0xFFFFFFFFL 3554 //UVD_GP_SCRATCH19 3555 #define UVD_GP_SCRATCH19__DATA__SHIFT 0x0 3556 #define UVD_GP_SCRATCH19__DATA_MASK 0xFFFFFFFFL 3557 //UVD_GP_SCRATCH20 3558 #define UVD_GP_SCRATCH20__DATA__SHIFT 0x0 3559 #define UVD_GP_SCRATCH20__DATA_MASK 0xFFFFFFFFL 3560 //UVD_GP_SCRATCH21 3561 #define UVD_GP_SCRATCH21__DATA__SHIFT 0x0 3562 #define UVD_GP_SCRATCH21__DATA_MASK 0xFFFFFFFFL 3563 //UVD_GP_SCRATCH22 3564 #define UVD_GP_SCRATCH22__DATA__SHIFT 0x0 3565 #define UVD_GP_SCRATCH22__DATA_MASK 0xFFFFFFFFL 3566 //UVD_GP_SCRATCH23 3567 #define UVD_GP_SCRATCH23__DATA__SHIFT 0x0 3568 #define UVD_GP_SCRATCH23__DATA_MASK 0xFFFFFFFFL 3569 //UVD_ENC_REG_INDEX 3570 #define UVD_ENC_REG_INDEX__INDEX__SHIFT 0x0 3571 #define UVD_ENC_REG_INDEX__INDEX_MASK 0x00001FFFL 3572 //UVD_ENC_REG_DATA 3573 #define UVD_ENC_REG_DATA__DATA__SHIFT 0x0 3574 #define UVD_ENC_REG_DATA__DATA_MASK 0xFFFFFFFFL 3575 //UVD_OUT_RB_BASE_LO 3576 #define UVD_OUT_RB_BASE_LO__RB_BASE_LO__SHIFT 0x6 3577 #define UVD_OUT_RB_BASE_LO__RB_BASE_LO_MASK 0xFFFFFFC0L 3578 //UVD_OUT_RB_BASE_HI 3579 #define UVD_OUT_RB_BASE_HI__RB_BASE_HI__SHIFT 0x0 3580 #define UVD_OUT_RB_BASE_HI__RB_BASE_HI_MASK 0xFFFFFFFFL 3581 //UVD_OUT_RB_SIZE 3582 #define UVD_OUT_RB_SIZE__RB_SIZE__SHIFT 0x4 3583 #define UVD_OUT_RB_SIZE__RB_SIZE_MASK 0x007FFFF0L 3584 //UVD_OUT_RB_RPTR 3585 #define UVD_OUT_RB_RPTR__RB_RPTR__SHIFT 0x4 3586 #define UVD_OUT_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L 3587 //UVD_OUT_RB_WPTR 3588 #define UVD_OUT_RB_WPTR__RB_WPTR__SHIFT 0x4 3589 #define UVD_OUT_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L 3590 //UVD_RB_BASE_LO2 3591 #define UVD_RB_BASE_LO2__RB_BASE_LO__SHIFT 0x6 3592 #define UVD_RB_BASE_LO2__RB_BASE_LO_MASK 0xFFFFFFC0L 3593 //UVD_RB_BASE_HI2 3594 #define UVD_RB_BASE_HI2__RB_BASE_HI__SHIFT 0x0 3595 #define UVD_RB_BASE_HI2__RB_BASE_HI_MASK 0xFFFFFFFFL 3596 //UVD_RB_SIZE2 3597 #define UVD_RB_SIZE2__RB_SIZE__SHIFT 0x4 3598 #define UVD_RB_SIZE2__RB_SIZE_MASK 0x007FFFF0L 3599 //UVD_RB_RPTR2 3600 #define UVD_RB_RPTR2__RB_RPTR__SHIFT 0x4 3601 #define UVD_RB_RPTR2__RB_RPTR_MASK 0x007FFFF0L 3602 //UVD_RB_WPTR2 3603 #define UVD_RB_WPTR2__RB_WPTR__SHIFT 0x4 3604 #define UVD_RB_WPTR2__RB_WPTR_MASK 0x007FFFF0L 3605 //UVD_RB_BASE_LO 3606 #define UVD_RB_BASE_LO__RB_BASE_LO__SHIFT 0x6 3607 #define UVD_RB_BASE_LO__RB_BASE_LO_MASK 0xFFFFFFC0L 3608 //UVD_RB_BASE_HI 3609 #define UVD_RB_BASE_HI__RB_BASE_HI__SHIFT 0x0 3610 #define UVD_RB_BASE_HI__RB_BASE_HI_MASK 0xFFFFFFFFL 3611 //UVD_RB_SIZE 3612 #define UVD_RB_SIZE__RB_SIZE__SHIFT 0x4 3613 #define UVD_RB_SIZE__RB_SIZE_MASK 0x007FFFF0L 3614 //UVD_RB_RPTR 3615 #define UVD_RB_RPTR__RB_RPTR__SHIFT 0x4 3616 #define UVD_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L 3617 //UVD_RB_WPTR 3618 #define UVD_RB_WPTR__RB_WPTR__SHIFT 0x4 3619 #define UVD_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L 3620 //UVD_ENC_PIPE_BUSY 3621 #define UVD_ENC_PIPE_BUSY__IME_BUSY__SHIFT 0x0 3622 #define UVD_ENC_PIPE_BUSY__SMP_BUSY__SHIFT 0x1 3623 #define UVD_ENC_PIPE_BUSY__SIT_BUSY__SHIFT 0x2 3624 #define UVD_ENC_PIPE_BUSY__SDB_BUSY__SHIFT 0x3 3625 #define UVD_ENC_PIPE_BUSY__ENT_BUSY__SHIFT 0x4 3626 #define UVD_ENC_PIPE_BUSY__ENT_HEADER_BUSY__SHIFT 0x5 3627 #define UVD_ENC_PIPE_BUSY__LCM_BUSY__SHIFT 0x6 3628 #define UVD_ENC_PIPE_BUSY__MDM_RD_CUR_BUSY__SHIFT 0x7 3629 #define UVD_ENC_PIPE_BUSY__MDM_RD_REF_BUSY__SHIFT 0x8 3630 #define UVD_ENC_PIPE_BUSY__MDM_RD_GEN_BUSY__SHIFT 0x9 3631 #define UVD_ENC_PIPE_BUSY__MDM_WR_RECON_BUSY__SHIFT 0xa 3632 #define UVD_ENC_PIPE_BUSY__MDM_WR_GEN_BUSY__SHIFT 0xb 3633 #define UVD_ENC_PIPE_BUSY__MIF_RD_CUR_BUSY__SHIFT 0x10 3634 #define UVD_ENC_PIPE_BUSY__MIF_RD_REF0_BUSY__SHIFT 0x11 3635 #define UVD_ENC_PIPE_BUSY__MIF_WR_GEN0_BUSY__SHIFT 0x12 3636 #define UVD_ENC_PIPE_BUSY__MIF_RD_GEN0_BUSY__SHIFT 0x13 3637 #define UVD_ENC_PIPE_BUSY__MIF_WR_GEN1_BUSY__SHIFT 0x14 3638 #define UVD_ENC_PIPE_BUSY__MIF_RD_GEN1_BUSY__SHIFT 0x15 3639 #define UVD_ENC_PIPE_BUSY__MIF_WR_BSP0_BUSY__SHIFT 0x16 3640 #define UVD_ENC_PIPE_BUSY__MIF_WR_BSP1_BUSY__SHIFT 0x17 3641 #define UVD_ENC_PIPE_BUSY__MIF_RD_BSD0_BUSY__SHIFT 0x18 3642 #define UVD_ENC_PIPE_BUSY__MIF_RD_BSD1_BUSY__SHIFT 0x19 3643 #define UVD_ENC_PIPE_BUSY__MIF_RD_BSD2_BUSY__SHIFT 0x1a 3644 #define UVD_ENC_PIPE_BUSY__MIF_RD_BSD3_BUSY__SHIFT 0x1b 3645 #define UVD_ENC_PIPE_BUSY__MIF_RD_BSD4_BUSY__SHIFT 0x1c 3646 #define UVD_ENC_PIPE_BUSY__MIF_WR_BSP2_BUSY__SHIFT 0x1d 3647 #define UVD_ENC_PIPE_BUSY__MIF_WR_BSP3_BUSY__SHIFT 0x1e 3648 #define UVD_ENC_PIPE_BUSY__IME_BUSY_MASK 0x00000001L 3649 #define UVD_ENC_PIPE_BUSY__SMP_BUSY_MASK 0x00000002L 3650 #define UVD_ENC_PIPE_BUSY__SIT_BUSY_MASK 0x00000004L 3651 #define UVD_ENC_PIPE_BUSY__SDB_BUSY_MASK 0x00000008L 3652 #define UVD_ENC_PIPE_BUSY__ENT_BUSY_MASK 0x00000010L 3653 #define UVD_ENC_PIPE_BUSY__ENT_HEADER_BUSY_MASK 0x00000020L 3654 #define UVD_ENC_PIPE_BUSY__LCM_BUSY_MASK 0x00000040L 3655 #define UVD_ENC_PIPE_BUSY__MDM_RD_CUR_BUSY_MASK 0x00000080L 3656 #define UVD_ENC_PIPE_BUSY__MDM_RD_REF_BUSY_MASK 0x00000100L 3657 #define UVD_ENC_PIPE_BUSY__MDM_RD_GEN_BUSY_MASK 0x00000200L 3658 #define UVD_ENC_PIPE_BUSY__MDM_WR_RECON_BUSY_MASK 0x00000400L 3659 #define UVD_ENC_PIPE_BUSY__MDM_WR_GEN_BUSY_MASK 0x00000800L 3660 #define UVD_ENC_PIPE_BUSY__MIF_RD_CUR_BUSY_MASK 0x00010000L 3661 #define UVD_ENC_PIPE_BUSY__MIF_RD_REF0_BUSY_MASK 0x00020000L 3662 #define UVD_ENC_PIPE_BUSY__MIF_WR_GEN0_BUSY_MASK 0x00040000L 3663 #define UVD_ENC_PIPE_BUSY__MIF_RD_GEN0_BUSY_MASK 0x00080000L 3664 #define UVD_ENC_PIPE_BUSY__MIF_WR_GEN1_BUSY_MASK 0x00100000L 3665 #define UVD_ENC_PIPE_BUSY__MIF_RD_GEN1_BUSY_MASK 0x00200000L 3666 #define UVD_ENC_PIPE_BUSY__MIF_WR_BSP0_BUSY_MASK 0x00400000L 3667 #define UVD_ENC_PIPE_BUSY__MIF_WR_BSP1_BUSY_MASK 0x00800000L 3668 #define UVD_ENC_PIPE_BUSY__MIF_RD_BSD0_BUSY_MASK 0x01000000L 3669 #define UVD_ENC_PIPE_BUSY__MIF_RD_BSD1_BUSY_MASK 0x02000000L 3670 #define UVD_ENC_PIPE_BUSY__MIF_RD_BSD2_BUSY_MASK 0x04000000L 3671 #define UVD_ENC_PIPE_BUSY__MIF_RD_BSD3_BUSY_MASK 0x08000000L 3672 #define UVD_ENC_PIPE_BUSY__MIF_RD_BSD4_BUSY_MASK 0x10000000L 3673 #define UVD_ENC_PIPE_BUSY__MIF_WR_BSP2_BUSY_MASK 0x20000000L 3674 #define UVD_ENC_PIPE_BUSY__MIF_WR_BSP3_BUSY_MASK 0x40000000L 3675 //UVD_RB_WPTR4 3676 #define UVD_RB_WPTR4__RB_WPTR__SHIFT 0x4 3677 #define UVD_RB_WPTR4__RB_WPTR_MASK 0x007FFFF0L 3678 //UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH 3679 #define UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3680 #define UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3681 //UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW 3682 #define UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3683 #define UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3684 //UVD_LMI_VCPU_NC1_64BIT_BAR_HIGH 3685 #define UVD_LMI_VCPU_NC1_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3686 #define UVD_LMI_VCPU_NC1_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3687 //UVD_LMI_VCPU_NC1_64BIT_BAR_LOW 3688 #define UVD_LMI_VCPU_NC1_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3689 #define UVD_LMI_VCPU_NC1_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3690 //UVD_LMI_VCPU_NC0_64BIT_BAR_HIGH 3691 #define UVD_LMI_VCPU_NC0_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3692 #define UVD_LMI_VCPU_NC0_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3693 //UVD_LMI_VCPU_NC0_64BIT_BAR_LOW 3694 #define UVD_LMI_VCPU_NC0_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3695 #define UVD_LMI_VCPU_NC0_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3696 //UVD_LMI_RBC_IB_64BIT_BAR_HIGH 3697 #define UVD_LMI_RBC_IB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3698 #define UVD_LMI_RBC_IB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3699 //UVD_LMI_RBC_IB_64BIT_BAR_LOW 3700 #define UVD_LMI_RBC_IB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3701 #define UVD_LMI_RBC_IB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3702 //UVD_LMI_RBC_RB_64BIT_BAR_HIGH 3703 #define UVD_LMI_RBC_RB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3704 #define UVD_LMI_RBC_RB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3705 //UVD_LMI_RBC_RB_64BIT_BAR_LOW 3706 #define UVD_LMI_RBC_RB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3707 #define UVD_LMI_RBC_RB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3708 3709 3710 // addressBlock: uvd0_uvdnp2dec 3711 //UVD_LMI_MMSCH_NC0_64BIT_BAR_LOW 3712 #define UVD_LMI_MMSCH_NC0_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3713 #define UVD_LMI_MMSCH_NC0_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3714 //UVD_LMI_MMSCH_NC0_64BIT_BAR_HIGH 3715 #define UVD_LMI_MMSCH_NC0_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3716 #define UVD_LMI_MMSCH_NC0_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3717 //UVD_LMI_MMSCH_NC1_64BIT_BAR_LOW 3718 #define UVD_LMI_MMSCH_NC1_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3719 #define UVD_LMI_MMSCH_NC1_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3720 //UVD_LMI_MMSCH_NC1_64BIT_BAR_HIGH 3721 #define UVD_LMI_MMSCH_NC1_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3722 #define UVD_LMI_MMSCH_NC1_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3723 //UVD_LMI_MMSCH_NC2_64BIT_BAR_LOW 3724 #define UVD_LMI_MMSCH_NC2_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3725 #define UVD_LMI_MMSCH_NC2_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3726 //UVD_LMI_MMSCH_NC2_64BIT_BAR_HIGH 3727 #define UVD_LMI_MMSCH_NC2_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3728 #define UVD_LMI_MMSCH_NC2_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3729 //UVD_LMI_MMSCH_NC3_64BIT_BAR_LOW 3730 #define UVD_LMI_MMSCH_NC3_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3731 #define UVD_LMI_MMSCH_NC3_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3732 //UVD_LMI_MMSCH_NC3_64BIT_BAR_HIGH 3733 #define UVD_LMI_MMSCH_NC3_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3734 #define UVD_LMI_MMSCH_NC3_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3735 //UVD_LMI_MMSCH_NC4_64BIT_BAR_LOW 3736 #define UVD_LMI_MMSCH_NC4_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3737 #define UVD_LMI_MMSCH_NC4_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3738 //UVD_LMI_MMSCH_NC4_64BIT_BAR_HIGH 3739 #define UVD_LMI_MMSCH_NC4_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3740 #define UVD_LMI_MMSCH_NC4_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3741 //UVD_LMI_MMSCH_NC5_64BIT_BAR_LOW 3742 #define UVD_LMI_MMSCH_NC5_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3743 #define UVD_LMI_MMSCH_NC5_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3744 //UVD_LMI_MMSCH_NC5_64BIT_BAR_HIGH 3745 #define UVD_LMI_MMSCH_NC5_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3746 #define UVD_LMI_MMSCH_NC5_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3747 //UVD_LMI_MMSCH_NC6_64BIT_BAR_LOW 3748 #define UVD_LMI_MMSCH_NC6_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3749 #define UVD_LMI_MMSCH_NC6_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3750 //UVD_LMI_MMSCH_NC6_64BIT_BAR_HIGH 3751 #define UVD_LMI_MMSCH_NC6_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3752 #define UVD_LMI_MMSCH_NC6_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3753 //UVD_LMI_MMSCH_NC7_64BIT_BAR_LOW 3754 #define UVD_LMI_MMSCH_NC7_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3755 #define UVD_LMI_MMSCH_NC7_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3756 //UVD_LMI_MMSCH_NC7_64BIT_BAR_HIGH 3757 #define UVD_LMI_MMSCH_NC7_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3758 #define UVD_LMI_MMSCH_NC7_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3759 //UVD_LMI_MMSCH_NC_VMID 3760 #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC0_VMID__SHIFT 0x0 3761 #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC1_VMID__SHIFT 0x4 3762 #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC2_VMID__SHIFT 0x8 3763 #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC3_VMID__SHIFT 0xc 3764 #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC4_VMID__SHIFT 0x10 3765 #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC5_VMID__SHIFT 0x14 3766 #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC6_VMID__SHIFT 0x18 3767 #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC7_VMID__SHIFT 0x1c 3768 #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC0_VMID_MASK 0x0000000FL 3769 #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC1_VMID_MASK 0x000000F0L 3770 #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC2_VMID_MASK 0x00000F00L 3771 #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC3_VMID_MASK 0x0000F000L 3772 #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC4_VMID_MASK 0x000F0000L 3773 #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC5_VMID_MASK 0x00F00000L 3774 #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC6_VMID_MASK 0x0F000000L 3775 #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC7_VMID_MASK 0xF0000000L 3776 //UVD_LMI_MMSCH_CTRL 3777 #define UVD_LMI_MMSCH_CTRL__MMSCH_DATA_COHERENCY_EN__SHIFT 0x0 3778 #define UVD_LMI_MMSCH_CTRL__MMSCH_VM__SHIFT 0x1 3779 #define UVD_LMI_MMSCH_CTRL__MMSCH_R_MC_SWAP__SHIFT 0x3 3780 #define UVD_LMI_MMSCH_CTRL__MMSCH_W_MC_SWAP__SHIFT 0x5 3781 #define UVD_LMI_MMSCH_CTRL__MMSCH_RD__SHIFT 0x7 3782 #define UVD_LMI_MMSCH_CTRL__MMSCH_WR__SHIFT 0x9 3783 #define UVD_LMI_MMSCH_CTRL__MMSCH_RD_DROP__SHIFT 0xb 3784 #define UVD_LMI_MMSCH_CTRL__MMSCH_WR_DROP__SHIFT 0xc 3785 #define UVD_LMI_MMSCH_CTRL__MMSCH_DATA_COHERENCY_EN_MASK 0x00000001L 3786 #define UVD_LMI_MMSCH_CTRL__MMSCH_VM_MASK 0x00000002L 3787 #define UVD_LMI_MMSCH_CTRL__MMSCH_R_MC_SWAP_MASK 0x00000018L 3788 #define UVD_LMI_MMSCH_CTRL__MMSCH_W_MC_SWAP_MASK 0x00000060L 3789 #define UVD_LMI_MMSCH_CTRL__MMSCH_RD_MASK 0x00000180L 3790 #define UVD_LMI_MMSCH_CTRL__MMSCH_WR_MASK 0x00000600L 3791 #define UVD_LMI_MMSCH_CTRL__MMSCH_RD_DROP_MASK 0x00000800L 3792 #define UVD_LMI_MMSCH_CTRL__MMSCH_WR_DROP_MASK 0x00001000L 3793 //UVD_MMSCH_SOFT_RESET 3794 #define UVD_MMSCH_SOFT_RESET__MMSCH_RESET__SHIFT 0x0 3795 #define UVD_MMSCH_SOFT_RESET__TAP_SOFT_RESET__SHIFT 0x1 3796 #define UVD_MMSCH_SOFT_RESET__MMSCH_LOCK__SHIFT 0x1f 3797 #define UVD_MMSCH_SOFT_RESET__MMSCH_RESET_MASK 0x00000001L 3798 #define UVD_MMSCH_SOFT_RESET__TAP_SOFT_RESET_MASK 0x00000002L 3799 #define UVD_MMSCH_SOFT_RESET__MMSCH_LOCK_MASK 0x80000000L 3800 //UVD_LMI_ARB_CTRL2 3801 #define UVD_LMI_ARB_CTRL2__CENC_RD_WAIT_EN__SHIFT 0x0 3802 #define UVD_LMI_ARB_CTRL2__ATOMIC_WR_WAIT_EN__SHIFT 0x1 3803 #define UVD_LMI_ARB_CTRL2__CENC_RD_MAX_BURST__SHIFT 0x2 3804 #define UVD_LMI_ARB_CTRL2__ATOMIC_WR_MAX_BURST__SHIFT 0x6 3805 #define UVD_LMI_ARB_CTRL2__MIF_RD_REQ_RET_MAX__SHIFT 0xa 3806 #define UVD_LMI_ARB_CTRL2__MIF_WR_REQ_RET_MAX__SHIFT 0x14 3807 #define UVD_LMI_ARB_CTRL2__CENC_RD_WAIT_EN_MASK 0x00000001L 3808 #define UVD_LMI_ARB_CTRL2__ATOMIC_WR_WAIT_EN_MASK 0x00000002L 3809 #define UVD_LMI_ARB_CTRL2__CENC_RD_MAX_BURST_MASK 0x0000003CL 3810 #define UVD_LMI_ARB_CTRL2__ATOMIC_WR_MAX_BURST_MASK 0x000003C0L 3811 #define UVD_LMI_ARB_CTRL2__MIF_RD_REQ_RET_MAX_MASK 0x000FFC00L 3812 #define UVD_LMI_ARB_CTRL2__MIF_WR_REQ_RET_MAX_MASK 0xFFF00000L 3813 3814 3815 #endif 3816