1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2013 4 * Texas Instruments Incorporated. 5 * Sricharan R <r.sricharan@ti.com> 6 * 7 * Derived from OMAP4 done by: 8 * Aneesh V <aneesh@ti.com> 9 * 10 * TI OMAP5 AND DRA7XX common configuration settings 11 * 12 * For more details, please see the technical documents listed at 13 * http://www.ti.com/product/omap5432 14 */ 15 16 #ifndef __CONFIG_TI_OMAP5_COMMON_H 17 #define __CONFIG_TI_OMAP5_COMMON_H 18 19 /* Use General purpose timer 1 */ 20 #define CONFIG_SYS_TIMERBASE GPT2_BASE 21 22 /* 23 * For the DDR timing information we can either dynamically determine 24 * the timings to use or use pre-determined timings (based on using the 25 * dynamic method. Default to the static timing infomation. 26 */ 27 #define CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS 28 #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS 29 #define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION 30 #define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS 31 #endif 32 33 #define CONFIG_PALMAS_POWER 34 35 #include <asm/arch/cpu.h> 36 #include <asm/arch/omap.h> 37 38 #include <configs/ti_armv7_omap.h> 39 40 /* 41 * Hardware drivers 42 */ 43 #define CONFIG_SYS_NS16550_CLK 48000000 44 #if !defined(CONFIG_DM_SERIAL) 45 #define CONFIG_SYS_NS16550_SERIAL 46 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 47 #endif 48 49 /* 50 * Environment setup 51 */ 52 53 #ifndef DFUARGS 54 #define DFUARGS 55 #endif 56 57 #include <environment/ti/boot.h> 58 #include <environment/ti/mmc.h> 59 60 #define CONFIG_EXTRA_ENV_SETTINGS \ 61 DEFAULT_LINUX_BOOT_ENV \ 62 DEFAULT_MMC_TI_ARGS \ 63 DEFAULT_FIT_TI_ARGS \ 64 DEFAULT_COMMON_BOOT_TI_ARGS \ 65 DEFAULT_FDT_TI_ARGS \ 66 DFUARGS \ 67 NETARGS \ 68 69 /* 70 * SPL related defines. The Public RAM memory map the ROM defines the 71 * area between 0x40300000 and 0x4031E000 as a download area for OMAP5. 72 * On DRA7xx/AM57XX the download area is between 0x40300000 and 0x4037E000. 73 * We set CONFIG_SPL_DISPLAY_PRINT to have omap_rev_string() called and 74 * print some information. 75 */ 76 #ifdef CONFIG_TI_SECURE_DEVICE 77 /* 78 * For memory booting on HS parts, the first 4KB of the internal RAM is 79 * reserved for secure world use and the flash loader image is 80 * preceded by a secure certificate. The SPL will therefore run in internal 81 * RAM from address 0x40301350 (0x40300000+0x1000(reserved)+0x350(cert)). 82 */ 83 #define TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ 0x1000 84 #define CONFIG_SPL_TEXT_BASE CONFIG_ISW_ENTRY_ADDR 85 /* If no specific start address is specified then the secure EMIF 86 * region will be placed at the end of the DDR space. In order to prevent 87 * the main u-boot relocation from clobbering that memory and causing a 88 * firewall violation, we tell u-boot that memory is protected RAM (PRAM) 89 */ 90 #if (CONFIG_TI_SECURE_EMIF_REGION_START == 0) 91 #define CONFIG_PRAM (CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE) >> 10 92 #endif 93 #else 94 /* 95 * For all booting on GP parts, the flash loader image is 96 * downloaded into internal RAM at address 0x40300000. 97 */ 98 #define CONFIG_SPL_TEXT_BASE 0x40300000 99 #endif 100 101 #define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \ 102 (128 << 20)) 103 104 #ifdef CONFIG_SPL_BUILD 105 #undef CONFIG_TIMER 106 #endif 107 108 #endif /* __CONFIG_TI_OMAP5_COMMON_H */ 109