1 /*
2 * QEMU ARM CPU -- syndrome functions and types
3 *
4 * Copyright (c) 2014 Linaro Ltd
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see
18 * <http://www.gnu.org/licenses/gpl-2.0.html>
19 *
20 * This header defines functions, types, etc which need to be shared
21 * between different source files within target/arm/ but which are
22 * private to it and not required by the rest of QEMU.
23 */
24
25 #ifndef TARGET_ARM_SYNDROME_H
26 #define TARGET_ARM_SYNDROME_H
27
28 #include "qemu/bitops.h"
29
30 /* Valid Syndrome Register EC field values */
31 enum arm_exception_class {
32 EC_UNCATEGORIZED = 0x00,
33 EC_WFX_TRAP = 0x01,
34 EC_CP15RTTRAP = 0x03,
35 EC_CP15RRTTRAP = 0x04,
36 EC_CP14RTTRAP = 0x05,
37 EC_CP14DTTRAP = 0x06,
38 EC_ADVSIMDFPACCESSTRAP = 0x07,
39 EC_FPIDTRAP = 0x08,
40 EC_PACTRAP = 0x09,
41 EC_BXJTRAP = 0x0a,
42 EC_CP14RRTTRAP = 0x0c,
43 EC_BTITRAP = 0x0d,
44 EC_ILLEGALSTATE = 0x0e,
45 EC_AA32_SVC = 0x11,
46 EC_AA32_HVC = 0x12,
47 EC_AA32_SMC = 0x13,
48 EC_AA64_SVC = 0x15,
49 EC_AA64_HVC = 0x16,
50 EC_AA64_SMC = 0x17,
51 EC_SYSTEMREGISTERTRAP = 0x18,
52 EC_SVEACCESSTRAP = 0x19,
53 EC_ERETTRAP = 0x1a,
54 EC_PACFAIL = 0x1c,
55 EC_SMETRAP = 0x1d,
56 EC_GPC = 0x1e,
57 EC_INSNABORT = 0x20,
58 EC_INSNABORT_SAME_EL = 0x21,
59 EC_PCALIGNMENT = 0x22,
60 EC_DATAABORT = 0x24,
61 EC_DATAABORT_SAME_EL = 0x25,
62 EC_SPALIGNMENT = 0x26,
63 EC_MOP = 0x27,
64 EC_AA32_FPTRAP = 0x28,
65 EC_AA64_FPTRAP = 0x2c,
66 EC_SERROR = 0x2f,
67 EC_BREAKPOINT = 0x30,
68 EC_BREAKPOINT_SAME_EL = 0x31,
69 EC_SOFTWARESTEP = 0x32,
70 EC_SOFTWARESTEP_SAME_EL = 0x33,
71 EC_WATCHPOINT = 0x34,
72 EC_WATCHPOINT_SAME_EL = 0x35,
73 EC_AA32_BKPT = 0x38,
74 EC_VECTORCATCH = 0x3a,
75 EC_AA64_BKPT = 0x3c,
76 };
77
78 typedef enum {
79 SME_ET_AccessTrap,
80 SME_ET_Streaming,
81 SME_ET_NotStreaming,
82 SME_ET_InactiveZA,
83 } SMEExceptionType;
84
85 #define ARM_EL_EC_LENGTH 6
86 #define ARM_EL_EC_SHIFT 26
87 #define ARM_EL_IL_SHIFT 25
88 #define ARM_EL_ISV_SHIFT 24
89 #define ARM_EL_IL (1 << ARM_EL_IL_SHIFT)
90 #define ARM_EL_ISV (1 << ARM_EL_ISV_SHIFT)
91
syn_get_ec(uint32_t syn)92 static inline uint32_t syn_get_ec(uint32_t syn)
93 {
94 return syn >> ARM_EL_EC_SHIFT;
95 }
96
syn_set_ec(uint32_t syn,uint32_t ec)97 static inline uint32_t syn_set_ec(uint32_t syn, uint32_t ec)
98 {
99 return deposit32(syn, ARM_EL_EC_SHIFT, ARM_EL_EC_LENGTH, ec);
100 }
101
102 /*
103 * Utility functions for constructing various kinds of syndrome value.
104 * Note that in general we follow the AArch64 syndrome values; in a
105 * few cases the value in HSR for exceptions taken to AArch32 Hyp
106 * mode differs slightly, and we fix this up when populating HSR in
107 * arm_cpu_do_interrupt_aarch32_hyp().
108 * The exception is FP/SIMD access traps -- these report extra information
109 * when taking an exception to AArch32. For those we include the extra coproc
110 * and TA fields, and mask them out when taking the exception to AArch64.
111 */
syn_uncategorized(void)112 static inline uint32_t syn_uncategorized(void)
113 {
114 return (EC_UNCATEGORIZED << ARM_EL_EC_SHIFT) | ARM_EL_IL;
115 }
116
syn_aa64_svc(uint32_t imm16)117 static inline uint32_t syn_aa64_svc(uint32_t imm16)
118 {
119 return (EC_AA64_SVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);
120 }
121
syn_aa64_hvc(uint32_t imm16)122 static inline uint32_t syn_aa64_hvc(uint32_t imm16)
123 {
124 return (EC_AA64_HVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);
125 }
126
syn_aa64_smc(uint32_t imm16)127 static inline uint32_t syn_aa64_smc(uint32_t imm16)
128 {
129 return (EC_AA64_SMC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);
130 }
131
syn_aa32_svc(uint32_t imm16,bool is_16bit)132 static inline uint32_t syn_aa32_svc(uint32_t imm16, bool is_16bit)
133 {
134 return (EC_AA32_SVC << ARM_EL_EC_SHIFT) | (imm16 & 0xffff)
135 | (is_16bit ? 0 : ARM_EL_IL);
136 }
137
syn_aa32_hvc(uint32_t imm16)138 static inline uint32_t syn_aa32_hvc(uint32_t imm16)
139 {
140 return (EC_AA32_HVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);
141 }
142
syn_aa32_smc(void)143 static inline uint32_t syn_aa32_smc(void)
144 {
145 return (EC_AA32_SMC << ARM_EL_EC_SHIFT) | ARM_EL_IL;
146 }
147
syn_aa64_bkpt(uint32_t imm16)148 static inline uint32_t syn_aa64_bkpt(uint32_t imm16)
149 {
150 return (EC_AA64_BKPT << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);
151 }
152
syn_aa32_bkpt(uint32_t imm16,bool is_16bit)153 static inline uint32_t syn_aa32_bkpt(uint32_t imm16, bool is_16bit)
154 {
155 return (EC_AA32_BKPT << ARM_EL_EC_SHIFT) | (imm16 & 0xffff)
156 | (is_16bit ? 0 : ARM_EL_IL);
157 }
158
syn_aa64_sysregtrap(int op0,int op1,int op2,int crn,int crm,int rt,int isread)159 static inline uint32_t syn_aa64_sysregtrap(int op0, int op1, int op2,
160 int crn, int crm, int rt,
161 int isread)
162 {
163 return (EC_SYSTEMREGISTERTRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL
164 | (op0 << 20) | (op2 << 17) | (op1 << 14) | (crn << 10) | (rt << 5)
165 | (crm << 1) | isread;
166 }
167
syn_cp14_rt_trap(int cv,int cond,int opc1,int opc2,int crn,int crm,int rt,int isread,bool is_16bit)168 static inline uint32_t syn_cp14_rt_trap(int cv, int cond, int opc1, int opc2,
169 int crn, int crm, int rt, int isread,
170 bool is_16bit)
171 {
172 return (EC_CP14RTTRAP << ARM_EL_EC_SHIFT)
173 | (is_16bit ? 0 : ARM_EL_IL)
174 | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14)
175 | (crn << 10) | (rt << 5) | (crm << 1) | isread;
176 }
177
syn_cp15_rt_trap(int cv,int cond,int opc1,int opc2,int crn,int crm,int rt,int isread,bool is_16bit)178 static inline uint32_t syn_cp15_rt_trap(int cv, int cond, int opc1, int opc2,
179 int crn, int crm, int rt, int isread,
180 bool is_16bit)
181 {
182 return (EC_CP15RTTRAP << ARM_EL_EC_SHIFT)
183 | (is_16bit ? 0 : ARM_EL_IL)
184 | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14)
185 | (crn << 10) | (rt << 5) | (crm << 1) | isread;
186 }
187
syn_cp14_rrt_trap(int cv,int cond,int opc1,int crm,int rt,int rt2,int isread,bool is_16bit)188 static inline uint32_t syn_cp14_rrt_trap(int cv, int cond, int opc1, int crm,
189 int rt, int rt2, int isread,
190 bool is_16bit)
191 {
192 return (EC_CP14RRTTRAP << ARM_EL_EC_SHIFT)
193 | (is_16bit ? 0 : ARM_EL_IL)
194 | (cv << 24) | (cond << 20) | (opc1 << 16)
195 | (rt2 << 10) | (rt << 5) | (crm << 1) | isread;
196 }
197
syn_cp15_rrt_trap(int cv,int cond,int opc1,int crm,int rt,int rt2,int isread,bool is_16bit)198 static inline uint32_t syn_cp15_rrt_trap(int cv, int cond, int opc1, int crm,
199 int rt, int rt2, int isread,
200 bool is_16bit)
201 {
202 return (EC_CP15RRTTRAP << ARM_EL_EC_SHIFT)
203 | (is_16bit ? 0 : ARM_EL_IL)
204 | (cv << 24) | (cond << 20) | (opc1 << 16)
205 | (rt2 << 10) | (rt << 5) | (crm << 1) | isread;
206 }
207
syn_fp_access_trap(int cv,int cond,bool is_16bit,int coproc)208 static inline uint32_t syn_fp_access_trap(int cv, int cond, bool is_16bit,
209 int coproc)
210 {
211 /* AArch32 FP trap or any AArch64 FP/SIMD trap: TA == 0 */
212 return (EC_ADVSIMDFPACCESSTRAP << ARM_EL_EC_SHIFT)
213 | (is_16bit ? 0 : ARM_EL_IL)
214 | (cv << 24) | (cond << 20) | coproc;
215 }
216
syn_simd_access_trap(int cv,int cond,bool is_16bit)217 static inline uint32_t syn_simd_access_trap(int cv, int cond, bool is_16bit)
218 {
219 /* AArch32 SIMD trap: TA == 1 coproc == 0 */
220 return (EC_ADVSIMDFPACCESSTRAP << ARM_EL_EC_SHIFT)
221 | (is_16bit ? 0 : ARM_EL_IL)
222 | (cv << 24) | (cond << 20) | (1 << 5);
223 }
224
syn_sve_access_trap(void)225 static inline uint32_t syn_sve_access_trap(void)
226 {
227 return (EC_SVEACCESSTRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL;
228 }
229
230 /*
231 * eret_op is bits [1:0] of the ERET instruction, so:
232 * 0 for ERET, 2 for ERETAA, 3 for ERETAB.
233 */
syn_erettrap(int eret_op)234 static inline uint32_t syn_erettrap(int eret_op)
235 {
236 return (EC_ERETTRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL | eret_op;
237 }
238
syn_smetrap(SMEExceptionType etype,bool is_16bit)239 static inline uint32_t syn_smetrap(SMEExceptionType etype, bool is_16bit)
240 {
241 return (EC_SMETRAP << ARM_EL_EC_SHIFT)
242 | (is_16bit ? 0 : ARM_EL_IL) | etype;
243 }
244
syn_pacfail(bool data,int keynumber)245 static inline uint32_t syn_pacfail(bool data, int keynumber)
246 {
247 int error_code = (data << 1) | keynumber;
248 return (EC_PACFAIL << ARM_EL_EC_SHIFT) | ARM_EL_IL | error_code;
249 }
250
syn_pactrap(void)251 static inline uint32_t syn_pactrap(void)
252 {
253 return (EC_PACTRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL;
254 }
255
syn_btitrap(int btype)256 static inline uint32_t syn_btitrap(int btype)
257 {
258 return (EC_BTITRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL | btype;
259 }
260
syn_bxjtrap(int cv,int cond,int rm)261 static inline uint32_t syn_bxjtrap(int cv, int cond, int rm)
262 {
263 return (EC_BXJTRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL |
264 (cv << 24) | (cond << 20) | rm;
265 }
266
syn_gpc(int s2ptw,int ind,int gpcsc,int cm,int s1ptw,int wnr,int fsc)267 static inline uint32_t syn_gpc(int s2ptw, int ind, int gpcsc,
268 int cm, int s1ptw, int wnr, int fsc)
269 {
270 /* TODO: FEAT_NV2 adds VNCR */
271 return (EC_GPC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (s2ptw << 21)
272 | (ind << 20) | (gpcsc << 14) | (cm << 8) | (s1ptw << 7)
273 | (wnr << 6) | fsc;
274 }
275
syn_insn_abort(int same_el,int ea,int s1ptw,int fsc)276 static inline uint32_t syn_insn_abort(int same_el, int ea, int s1ptw, int fsc)
277 {
278 return (EC_INSNABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
279 | ARM_EL_IL | (ea << 9) | (s1ptw << 7) | fsc;
280 }
281
syn_data_abort_no_iss(int same_el,int fnv,int ea,int cm,int s1ptw,int wnr,int fsc)282 static inline uint32_t syn_data_abort_no_iss(int same_el, int fnv,
283 int ea, int cm, int s1ptw,
284 int wnr, int fsc)
285 {
286 return (EC_DATAABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
287 | ARM_EL_IL
288 | (fnv << 10) | (ea << 9) | (cm << 8) | (s1ptw << 7)
289 | (wnr << 6) | fsc;
290 }
291
syn_data_abort_with_iss(int same_el,int sas,int sse,int srt,int sf,int ar,int ea,int cm,int s1ptw,int wnr,int fsc,bool is_16bit)292 static inline uint32_t syn_data_abort_with_iss(int same_el,
293 int sas, int sse, int srt,
294 int sf, int ar,
295 int ea, int cm, int s1ptw,
296 int wnr, int fsc,
297 bool is_16bit)
298 {
299 return (EC_DATAABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
300 | (is_16bit ? 0 : ARM_EL_IL)
301 | ARM_EL_ISV | (sas << 22) | (sse << 21) | (srt << 16)
302 | (sf << 15) | (ar << 14)
303 | (ea << 9) | (cm << 8) | (s1ptw << 7) | (wnr << 6) | fsc;
304 }
305
syn_swstep(int same_el,int isv,int ex)306 static inline uint32_t syn_swstep(int same_el, int isv, int ex)
307 {
308 return (EC_SOFTWARESTEP << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
309 | ARM_EL_IL | (isv << 24) | (ex << 6) | 0x22;
310 }
311
syn_watchpoint(int same_el,int cm,int wnr)312 static inline uint32_t syn_watchpoint(int same_el, int cm, int wnr)
313 {
314 return (EC_WATCHPOINT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
315 | ARM_EL_IL | (cm << 8) | (wnr << 6) | 0x22;
316 }
317
syn_breakpoint(int same_el)318 static inline uint32_t syn_breakpoint(int same_el)
319 {
320 return (EC_BREAKPOINT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
321 | ARM_EL_IL | 0x22;
322 }
323
syn_wfx(int cv,int cond,int ti,bool is_16bit)324 static inline uint32_t syn_wfx(int cv, int cond, int ti, bool is_16bit)
325 {
326 return (EC_WFX_TRAP << ARM_EL_EC_SHIFT) |
327 (is_16bit ? 0 : (1 << ARM_EL_IL_SHIFT)) |
328 (cv << 24) | (cond << 20) | ti;
329 }
330
syn_illegalstate(void)331 static inline uint32_t syn_illegalstate(void)
332 {
333 return (EC_ILLEGALSTATE << ARM_EL_EC_SHIFT) | ARM_EL_IL;
334 }
335
syn_pcalignment(void)336 static inline uint32_t syn_pcalignment(void)
337 {
338 return (EC_PCALIGNMENT << ARM_EL_EC_SHIFT) | ARM_EL_IL;
339 }
340
syn_serror(uint32_t extra)341 static inline uint32_t syn_serror(uint32_t extra)
342 {
343 return (EC_SERROR << ARM_EL_EC_SHIFT) | ARM_EL_IL | extra;
344 }
345
syn_mop(bool is_set,bool is_setg,int options,bool epilogue,bool wrong_option,bool option_a,int destreg,int srcreg,int sizereg)346 static inline uint32_t syn_mop(bool is_set, bool is_setg, int options,
347 bool epilogue, bool wrong_option, bool option_a,
348 int destreg, int srcreg, int sizereg)
349 {
350 return (EC_MOP << ARM_EL_EC_SHIFT) | ARM_EL_IL |
351 (is_set << 24) | (is_setg << 23) | (options << 19) |
352 (epilogue << 18) | (wrong_option << 17) | (option_a << 16) |
353 (destreg << 10) | (srcreg << 5) | sizereg;
354 }
355
356
357 #endif /* TARGET_ARM_SYNDROME_H */
358