1# AArch64 SVE instruction descriptions 2# 3# Copyright (c) 2017 Linaro, Ltd 4# 5# This library is free software; you can redistribute it and/or 6# modify it under the terms of the GNU Lesser General Public 7# License as published by the Free Software Foundation; either 8# version 2.1 of the License, or (at your option) any later version. 9# 10# This library is distributed in the hope that it will be useful, 11# but WITHOUT ANY WARRANTY; without even the implied warranty of 12# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13# Lesser General Public License for more details. 14# 15# You should have received a copy of the GNU Lesser General Public 16# License along with this library; if not, see <http://www.gnu.org/licenses/>. 17 18# 19# This file is processed by scripts/decodetree.py 20# 21 22########################################################################### 23# Named fields. These are primarily for disjoint fields. 24 25%imm4_16_p1 16:4 !function=plus_1 26%imm6_22_5 22:1 5:5 27%imm7_22_16 22:2 16:5 28%imm8_16_10 16:5 10:3 29%imm9_16_10 16:s6 10:3 30%size_23 23:2 31%dtype_23_13 23:2 13:2 32%index3_22_19 22:1 19:2 33%index3_22_17 22:1 17:2 34%index3_19_11 19:2 11:1 35%index2_20_11 20:1 11:1 36 37# A combination of tsz:imm3 -- extract esize. 38%tszimm_esz 22:2 5:5 !function=tszimm_esz 39# A combination of tsz:imm3 -- extract (2 * esize) - (tsz:imm3) 40%tszimm_shr 22:2 5:5 !function=tszimm_shr 41# A combination of tsz:imm3 -- extract (tsz:imm3) - esize 42%tszimm_shl 22:2 5:5 !function=tszimm_shl 43 44# Similarly for the tszh/tszl pair at 22/16 for zzi 45%tszimm16_esz 22:2 16:5 !function=tszimm_esz 46%tszimm16_shr 22:2 16:5 !function=tszimm_shr 47%tszimm16_shl 22:2 16:5 !function=tszimm_shl 48 49# Signed 8-bit immediate, optionally shifted left by 8. 50%sh8_i8s 5:9 !function=expand_imm_sh8s 51# Unsigned 8-bit immediate, optionally shifted left by 8. 52%sh8_i8u 5:9 !function=expand_imm_sh8u 53 54# Unsigned load of msz into esz=2, represented as a dtype. 55%msz_dtype 23:2 !function=msz_dtype 56 57# Either a copy of rd (at bit 0), or a different source 58# as propagated via the MOVPRFX instruction. 59%reg_movprfx 0:5 60 61%rn_ax2 6:4 !function=times_2 62 63%pnd 0:3 !function=plus_8 64%pnn 5:3 !function=plus_8 65 66########################################################################### 67# Named attribute sets. These are used to make nice(er) names 68# when creating helpers common to those for the individual 69# instruction patterns. 70 71&rr_esz rd rn esz 72&rri rd rn imm 73&rr_dbm rd rn dbm 74&rrri rd rn rm imm 75&rri_esz rd rn imm esz 76&rrri_esz rd rn rm imm esz 77&rrr_esz rd rn rm esz 78&rrx_esz rd rn rm index esz 79&rpr_esz rd pg rn esz 80&rpr_s rd pg rn s 81&rprr_s rd pg rn rm s 82&rprr_esz rd pg rn rm esz 83&rrrr_esz rd ra rn rm esz 84&rrxr_esz rd rn rm ra index esz 85&rprrr_esz rd pg rn rm ra esz 86&rpri_esz rd pg rn imm esz 87&ptrue rd esz pat s 88&incdec_cnt rd pat esz imm d u 89&incdec2_cnt rd rn pat esz imm d u 90&incdec_pred rd pg esz d u 91&incdec2_pred rd rn pg esz d u 92&rprr_load rd pg rn rm dtype nreg 93&rpri_load rd pg rn imm dtype nreg 94&rprr_store rd pg rn rm msz esz nreg 95&rpri_store rd pg rn imm msz esz nreg 96&rprr_gather_load rd pg rn rm esz msz u ff xs scale 97&rpri_gather_load rd pg rn imm esz msz u ff 98&rprr_scatter_store rd pg rn rm esz msz xs scale 99&rpri_scatter_store rd pg rn imm esz msz 100 101########################################################################### 102# Named instruction formats. These are generally used to 103# reduce the amount of duplication between instruction patterns. 104 105# Two operand with unused vector element size 106@pd_pn_e0 ........ ........ ....... rn:4 . rd:4 &rr_esz esz=0 107 108# Two operand 109@pd_pn ........ esz:2 .. .... ....... rn:4 . rd:4 &rr_esz 110@rd_rn ........ esz:2 ...... ...... rn:5 rd:5 &rr_esz 111@rd_rnx2 ........ ... ..... ...... ..... rd:5 &rr_esz rn=%rn_ax2 112 113# Two operand with governing predicate, flags setting 114@pd_pg_pn_s ........ . s:1 ...... .. pg:4 . rn:4 . rd:4 &rpr_s 115@pd_pg_pn_s0 ........ . . ...... .. pg:4 . rn:4 . rd:4 &rpr_s s=0 116 117# Three operand with unused vector element size 118@rd_rn_rm_e0 ........ ... rm:5 ... ... rn:5 rd:5 &rrr_esz esz=0 119 120# Three predicate operand, with governing predicate, flag setting 121@pd_pg_pn_pm_s ........ . s:1 .. rm:4 .. pg:4 . rn:4 . rd:4 &rprr_s 122 123# Three operand, vector element size 124@rd_rn_rm ........ esz:2 . rm:5 ... ... rn:5 rd:5 &rrr_esz 125@pd_pn_pm ........ esz:2 .. rm:4 ....... rn:4 . rd:4 &rrr_esz 126@rdn_rm ........ esz:2 ...... ...... rm:5 rd:5 \ 127 &rrr_esz rn=%reg_movprfx 128@rdn_rm_e0 ........ .. ...... ...... rm:5 rd:5 \ 129 &rrr_esz rn=%reg_movprfx esz=0 130@rdn_sh_i8u ........ esz:2 ...... ...... ..... rd:5 \ 131 &rri_esz rn=%reg_movprfx imm=%sh8_i8u 132@rdn_i8u ........ esz:2 ...... ... imm:8 rd:5 \ 133 &rri_esz rn=%reg_movprfx 134@rdn_i8s ........ esz:2 ...... ... imm:s8 rd:5 \ 135 &rri_esz rn=%reg_movprfx 136 137# Four operand, vector element size 138@rda_rn_rm ........ esz:2 . rm:5 ... ... rn:5 rd:5 \ 139 &rrrr_esz ra=%reg_movprfx 140 141# Four operand with explicit vector element size 142@rda_rn_rm_ex ........ ... rm:5 ... ... rn:5 rd:5 \ 143 &rrrr_esz ra=%reg_movprfx 144@rdn_ra_rm_ex ........ ... rm:5 ... ... ra:5 rd:5 \ 145 &rrrr_esz rn=%reg_movprfx 146 147# Three operand with "memory" size, aka immediate left shift 148@rd_rn_msz_rm ........ ... rm:5 .... imm:2 rn:5 rd:5 &rrri 149 150# Two register operand, with governing predicate, vector element size 151@rdn_pg_rm ........ esz:2 ... ... ... pg:3 rm:5 rd:5 \ 152 &rprr_esz rn=%reg_movprfx 153@rdm_pg_rn ........ esz:2 ... ... ... pg:3 rn:5 rd:5 \ 154 &rprr_esz rm=%reg_movprfx 155@rd_pg4_rn_rm ........ esz:2 . rm:5 .. pg:4 rn:5 rd:5 &rprr_esz 156@pd_pg_rn_rm ........ esz:2 . rm:5 ... pg:3 rn:5 . rd:4 &rprr_esz 157 158# Three register operand, with governing predicate, vector element size 159@rda_pg_rn_rm ........ esz:2 . rm:5 ... pg:3 rn:5 rd:5 \ 160 &rprrr_esz ra=%reg_movprfx 161@rdn_pg_ra_rm ........ esz:2 . rm:5 ... pg:3 ra:5 rd:5 \ 162 &rprrr_esz rn=%reg_movprfx 163@rdn_pg_rm_ra ........ esz:2 . ra:5 ... pg:3 rm:5 rd:5 \ 164 &rprrr_esz rn=%reg_movprfx 165@rd_pg_rn_rm ........ esz:2 . rm:5 ... pg:3 rn:5 rd:5 &rprr_esz 166 167# One register operand, with governing predicate, vector element size 168@rd_pg_rn ........ esz:2 ... ... ... pg:3 rn:5 rd:5 &rpr_esz 169@rd_pg4_pn ........ esz:2 ... ... .. pg:4 . rn:4 rd:5 &rpr_esz 170@pd_pg_rn ........ esz:2 ... ... ... pg:3 rn:5 . rd:4 &rpr_esz 171 172# One register operand, with governing predicate, no vector element size 173@rd_pg_rn_e0 ........ .. ... ... ... pg:3 rn:5 rd:5 &rpr_esz esz=0 174 175# Two register operands with a 6-bit signed immediate. 176@rd_rn_i6 ........ ... rn:5 ..... imm:s6 rd:5 &rri 177 178# Two register operand, one immediate operand, with predicate, 179# element size encoded as TSZHL. 180@rdn_pg_tszimm_shl ........ .. ... ... ... pg:3 ..... rd:5 \ 181 &rpri_esz rn=%reg_movprfx esz=%tszimm_esz imm=%tszimm_shl 182@rdn_pg_tszimm_shr ........ .. ... ... ... pg:3 ..... rd:5 \ 183 &rpri_esz rn=%reg_movprfx esz=%tszimm_esz imm=%tszimm_shr 184 185# Similarly without predicate. 186@rd_rn_tszimm_shl ........ .. ... ... ...... rn:5 rd:5 \ 187 &rri_esz esz=%tszimm16_esz imm=%tszimm16_shl 188@rd_rn_tszimm_shr ........ .. ... ... ...... rn:5 rd:5 \ 189 &rri_esz esz=%tszimm16_esz imm=%tszimm16_shr 190 191# Two register operand, one immediate operand, with 4-bit predicate. 192# User must fill in imm. 193@rdn_pg4 ........ esz:2 .. pg:4 ... ........ rd:5 \ 194 &rpri_esz rn=%reg_movprfx 195 196# Two register operand, one one-bit floating-point operand. 197@rdn_i1 ........ esz:2 ......... pg:3 .... imm:1 rd:5 \ 198 &rpri_esz rn=%reg_movprfx 199 200# Two register operand, one encoded bitmask. 201@rdn_dbm ........ .. .... dbm:13 rd:5 \ 202 &rr_dbm rn=%reg_movprfx 203 204# Predicate output, vector and immediate input, 205# controlling predicate, element size. 206@pd_pg_rn_i7 ........ esz:2 . imm:7 . pg:3 rn:5 . rd:4 &rpri_esz 207@pd_pg_rn_i5 ........ esz:2 . imm:s5 ... pg:3 rn:5 . rd:4 &rpri_esz 208 209# Basic Load/Store with 9-bit immediate offset 210@pd_rn_i9 ........ ........ ...... rn:5 . rd:4 \ 211 &rri imm=%imm9_16_10 212@rd_rn_i9 ........ ........ ...... rn:5 rd:5 \ 213 &rri imm=%imm9_16_10 214 215# One register, pattern, and uint4+1. 216# User must fill in U and D. 217@incdec_cnt ........ esz:2 .. .... ...... pat:5 rd:5 \ 218 &incdec_cnt imm=%imm4_16_p1 219@incdec2_cnt ........ esz:2 .. .... ...... pat:5 rd:5 \ 220 &incdec2_cnt imm=%imm4_16_p1 rn=%reg_movprfx 221 222# One register, predicate. 223# User must fill in U and D. 224@incdec_pred ........ esz:2 .... .. ..... .. pg:4 rd:5 &incdec_pred 225@incdec2_pred ........ esz:2 .... .. ..... .. pg:4 rd:5 \ 226 &incdec2_pred rn=%reg_movprfx 227 228# Loads; user must fill in NREG. 229@rprr_load_dt ....... dtype:4 rm:5 ... pg:3 rn:5 rd:5 &rprr_load 230@rpri_load_dt ....... dtype:4 . imm:s4 ... pg:3 rn:5 rd:5 &rpri_load 231 232@rprr_load ....... .... rm:5 ... pg:3 rn:5 rd:5 &rprr_load 233@rpri_load ....... .... . imm:s4 ... pg:3 rn:5 rd:5 &rpri_load 234 235@rprr_load_msz ....... .... rm:5 ... pg:3 rn:5 rd:5 \ 236 &rprr_load dtype=%msz_dtype 237@rpri_load_msz ....... .... . imm:s4 ... pg:3 rn:5 rd:5 \ 238 &rpri_load dtype=%msz_dtype 239 240# Gather Loads. 241@rprr_g_load_u ....... .. . . rm:5 . u:1 ff:1 pg:3 rn:5 rd:5 \ 242 &rprr_gather_load xs=2 243@rprr_g_load_xs_u ....... .. xs:1 . rm:5 . u:1 ff:1 pg:3 rn:5 rd:5 \ 244 &rprr_gather_load 245@rprr_g_load_xs_u_sc ....... .. xs:1 scale:1 rm:5 . u:1 ff:1 pg:3 rn:5 rd:5 \ 246 &rprr_gather_load 247@rprr_g_load_xs_sc ....... .. xs:1 scale:1 rm:5 . . ff:1 pg:3 rn:5 rd:5 \ 248 &rprr_gather_load 249@rprr_g_load_u_sc ....... .. . scale:1 rm:5 . u:1 ff:1 pg:3 rn:5 rd:5 \ 250 &rprr_gather_load xs=2 251@rprr_g_load_sc ....... .. . scale:1 rm:5 . . ff:1 pg:3 rn:5 rd:5 \ 252 &rprr_gather_load xs=2 253@rpri_g_load ....... msz:2 .. imm:5 . u:1 ff:1 pg:3 rn:5 rd:5 \ 254 &rpri_gather_load 255 256# Stores; user must fill in ESZ, MSZ, NREG as needed. 257@rprr_store ....... .. .. rm:5 ... pg:3 rn:5 rd:5 &rprr_store 258@rpri_store ....... .. .. . imm:s4 ... pg:3 rn:5 rd:5 &rpri_store 259@rprr_store_esz_n0 ....... .. esz:2 rm:5 ... pg:3 rn:5 rd:5 \ 260 &rprr_store nreg=0 261@rprr_scatter_store ....... msz:2 .. rm:5 ... pg:3 rn:5 rd:5 \ 262 &rprr_scatter_store 263@rpri_scatter_store ....... msz:2 .. imm:5 ... pg:3 rn:5 rd:5 \ 264 &rpri_scatter_store 265 266# Two registers and a scalar by N-bit index 267@rrx_3 ........ .. . .. rm:3 ...... rn:5 rd:5 \ 268 &rrx_esz index=%index3_22_19 269@rrx_2 ........ .. . index:2 rm:3 ...... rn:5 rd:5 &rrx_esz 270@rrx_1 ........ .. . index:1 rm:4 ...... rn:5 rd:5 &rrx_esz 271 272# Two registers and a scalar by N-bit index, alternate 273@rrx_3a ........ .. . .. rm:3 ...... rn:5 rd:5 \ 274 &rrx_esz index=%index3_19_11 275@rrx_2a ........ .. . . rm:4 ...... rn:5 rd:5 \ 276 &rrx_esz index=%index2_20_11 277 278# Three registers and a scalar by N-bit index 279@rrxr_3 ........ .. . .. rm:3 ...... rn:5 rd:5 \ 280 &rrxr_esz ra=%reg_movprfx index=%index3_22_19 281@rrxr_2 ........ .. . index:2 rm:3 ...... rn:5 rd:5 \ 282 &rrxr_esz ra=%reg_movprfx 283@rrxr_1 ........ .. . index:1 rm:4 ...... rn:5 rd:5 \ 284 &rrxr_esz ra=%reg_movprfx 285 286# Three registers and a scalar by N-bit index, alternate 287@rrxr_3a ........ .. ... rm:3 ...... rn:5 rd:5 \ 288 &rrxr_esz ra=%reg_movprfx index=%index3_19_11 289@rrxr_2a ........ .. .. rm:4 ...... rn:5 rd:5 \ 290 &rrxr_esz ra=%reg_movprfx index=%index2_20_11 291 292########################################################################### 293# Instruction patterns. Grouped according to the SVE encodingindex.xhtml. 294 295### SVE Integer Arithmetic - Binary Predicated Group 296 297# SVE bitwise logical vector operations (predicated) 298ORR_zpzz 00000100 .. 011 000 000 ... ..... ..... @rdn_pg_rm 299EOR_zpzz 00000100 .. 011 001 000 ... ..... ..... @rdn_pg_rm 300AND_zpzz 00000100 .. 011 010 000 ... ..... ..... @rdn_pg_rm 301BIC_zpzz 00000100 .. 011 011 000 ... ..... ..... @rdn_pg_rm 302 303# SVE integer add/subtract vectors (predicated) 304ADD_zpzz 00000100 .. 000 000 000 ... ..... ..... @rdn_pg_rm 305SUB_zpzz 00000100 .. 000 001 000 ... ..... ..... @rdn_pg_rm 306SUB_zpzz 00000100 .. 000 011 000 ... ..... ..... @rdm_pg_rn # SUBR 307 308# SVE integer min/max/difference (predicated) 309SMAX_zpzz 00000100 .. 001 000 000 ... ..... ..... @rdn_pg_rm 310UMAX_zpzz 00000100 .. 001 001 000 ... ..... ..... @rdn_pg_rm 311SMIN_zpzz 00000100 .. 001 010 000 ... ..... ..... @rdn_pg_rm 312UMIN_zpzz 00000100 .. 001 011 000 ... ..... ..... @rdn_pg_rm 313SABD_zpzz 00000100 .. 001 100 000 ... ..... ..... @rdn_pg_rm 314UABD_zpzz 00000100 .. 001 101 000 ... ..... ..... @rdn_pg_rm 315 316# SVE integer multiply/divide (predicated) 317MUL_zpzz 00000100 .. 010 000 000 ... ..... ..... @rdn_pg_rm 318SMULH_zpzz 00000100 .. 010 010 000 ... ..... ..... @rdn_pg_rm 319UMULH_zpzz 00000100 .. 010 011 000 ... ..... ..... @rdn_pg_rm 320# Note that divide requires size >= 2; below 2 is unallocated. 321SDIV_zpzz 00000100 .. 010 100 000 ... ..... ..... @rdn_pg_rm 322UDIV_zpzz 00000100 .. 010 101 000 ... ..... ..... @rdn_pg_rm 323SDIV_zpzz 00000100 .. 010 110 000 ... ..... ..... @rdm_pg_rn # SDIVR 324UDIV_zpzz 00000100 .. 010 111 000 ... ..... ..... @rdm_pg_rn # UDIVR 325 326### SVE Integer Reduction Group 327 328# SVE bitwise logical reduction (predicated) 329ORV 00000100 .. 011 000 001 ... ..... ..... @rd_pg_rn 330EORV 00000100 .. 011 001 001 ... ..... ..... @rd_pg_rn 331ANDV 00000100 .. 011 010 001 ... ..... ..... @rd_pg_rn 332 333# SVE2.1 bitwise logical reduction (quadwords) 334ORQV 00000100 .. 011 100 001 ... ..... ..... @rd_pg_rn 335EORQV 00000100 .. 011 101 001 ... ..... ..... @rd_pg_rn 336ANDQV 00000100 .. 011 110 001 ... ..... ..... @rd_pg_rn 337 338# SVE constructive prefix (predicated) 339MOVPRFX_z 00000100 .. 010 000 001 ... ..... ..... @rd_pg_rn 340MOVPRFX_m 00000100 .. 010 001 001 ... ..... ..... @rd_pg_rn 341 342# SVE integer add reduction (predicated) 343# Note that saddv requires size != 3. 344UADDV 00000100 .. 000 001 001 ... ..... ..... @rd_pg_rn 345SADDV 00000100 .. 000 000 001 ... ..... ..... @rd_pg_rn 346 347# SVE integer min/max reduction (predicated) 348SMAXV 00000100 .. 001 000 001 ... ..... ..... @rd_pg_rn 349UMAXV 00000100 .. 001 001 001 ... ..... ..... @rd_pg_rn 350SMINV 00000100 .. 001 010 001 ... ..... ..... @rd_pg_rn 351UMINV 00000100 .. 001 011 001 ... ..... ..... @rd_pg_rn 352 353# SVE2.1 segment reduction 354ADDQV 00000100 .. 000 101 001 ... ..... ..... @rd_pg_rn 355SMAXQV 00000100 .. 001 100 001 ... ..... ..... @rd_pg_rn 356SMINQV 00000100 .. 001 110 001 ... ..... ..... @rd_pg_rn 357UMAXQV 00000100 .. 001 101 001 ... ..... ..... @rd_pg_rn 358UMINQV 00000100 .. 001 111 001 ... ..... ..... @rd_pg_rn 359 360### SVE Shift by Immediate - Predicated Group 361 362# SVE bitwise shift by immediate (predicated) 363ASR_zpzi 00000100 .. 000 000 100 ... .. ... ..... @rdn_pg_tszimm_shr 364LSR_zpzi 00000100 .. 000 001 100 ... .. ... ..... @rdn_pg_tszimm_shr 365LSL_zpzi 00000100 .. 000 011 100 ... .. ... ..... @rdn_pg_tszimm_shl 366ASRD 00000100 .. 000 100 100 ... .. ... ..... @rdn_pg_tszimm_shr 367SQSHL_zpzi 00000100 .. 000 110 100 ... .. ... ..... @rdn_pg_tszimm_shl 368UQSHL_zpzi 00000100 .. 000 111 100 ... .. ... ..... @rdn_pg_tszimm_shl 369SRSHR 00000100 .. 001 100 100 ... .. ... ..... @rdn_pg_tszimm_shr 370URSHR 00000100 .. 001 101 100 ... .. ... ..... @rdn_pg_tszimm_shr 371SQSHLU 00000100 .. 001 111 100 ... .. ... ..... @rdn_pg_tszimm_shl 372 373# SVE bitwise shift by vector (predicated) 374ASR_zpzz 00000100 .. 010 000 100 ... ..... ..... @rdn_pg_rm 375LSR_zpzz 00000100 .. 010 001 100 ... ..... ..... @rdn_pg_rm 376LSL_zpzz 00000100 .. 010 011 100 ... ..... ..... @rdn_pg_rm 377ASR_zpzz 00000100 .. 010 100 100 ... ..... ..... @rdm_pg_rn # ASRR 378LSR_zpzz 00000100 .. 010 101 100 ... ..... ..... @rdm_pg_rn # LSRR 379LSL_zpzz 00000100 .. 010 111 100 ... ..... ..... @rdm_pg_rn # LSLR 380 381# SVE bitwise shift by wide elements (predicated) 382# Note these require size != 3. 383ASR_zpzw 00000100 .. 011 000 100 ... ..... ..... @rdn_pg_rm 384LSR_zpzw 00000100 .. 011 001 100 ... ..... ..... @rdn_pg_rm 385LSL_zpzw 00000100 .. 011 011 100 ... ..... ..... @rdn_pg_rm 386 387### SVE Integer Arithmetic - Unary Predicated Group 388 389# SVE unary bit operations (predicated) 390# Note esz != 0 for FABS and FNEG. 391CLS 00000100 .. 011 000 101 ... ..... ..... @rd_pg_rn 392CLZ 00000100 .. 011 001 101 ... ..... ..... @rd_pg_rn 393CNT_zpz 00000100 .. 011 010 101 ... ..... ..... @rd_pg_rn 394CNOT 00000100 .. 011 011 101 ... ..... ..... @rd_pg_rn 395NOT_zpz 00000100 .. 011 110 101 ... ..... ..... @rd_pg_rn 396FABS 00000100 .. 011 100 101 ... ..... ..... @rd_pg_rn 397FNEG 00000100 .. 011 101 101 ... ..... ..... @rd_pg_rn 398 399# SVE integer unary operations (predicated) 400# Note esz > original size for extensions. 401ABS 00000100 .. 010 110 101 ... ..... ..... @rd_pg_rn 402NEG 00000100 .. 010 111 101 ... ..... ..... @rd_pg_rn 403SXTB 00000100 .. 010 000 101 ... ..... ..... @rd_pg_rn 404UXTB 00000100 .. 010 001 101 ... ..... ..... @rd_pg_rn 405SXTH 00000100 .. 010 010 101 ... ..... ..... @rd_pg_rn 406UXTH 00000100 .. 010 011 101 ... ..... ..... @rd_pg_rn 407SXTW 00000100 .. 010 100 101 ... ..... ..... @rd_pg_rn 408UXTW 00000100 .. 010 101 101 ... ..... ..... @rd_pg_rn 409 410### SVE Floating Point Compare - Vectors Group 411 412# SVE floating-point compare vectors 413FCMGE_ppzz 01100101 .. 0 ..... 010 ... ..... 0 .... @pd_pg_rn_rm 414FCMGT_ppzz 01100101 .. 0 ..... 010 ... ..... 1 .... @pd_pg_rn_rm 415FCMEQ_ppzz 01100101 .. 0 ..... 011 ... ..... 0 .... @pd_pg_rn_rm 416FCMNE_ppzz 01100101 .. 0 ..... 011 ... ..... 1 .... @pd_pg_rn_rm 417FCMUO_ppzz 01100101 .. 0 ..... 110 ... ..... 0 .... @pd_pg_rn_rm 418FACGE_ppzz 01100101 .. 0 ..... 110 ... ..... 1 .... @pd_pg_rn_rm 419FACGT_ppzz 01100101 .. 0 ..... 111 ... ..... 1 .... @pd_pg_rn_rm 420 421### SVE Integer Multiply-Add Group 422 423# SVE integer multiply-add writing addend (predicated) 424MLA 00000100 .. 0 ..... 010 ... ..... ..... @rda_pg_rn_rm 425MLS 00000100 .. 0 ..... 011 ... ..... ..... @rda_pg_rn_rm 426 427# SVE integer multiply-add writing multiplicand (predicated) 428MLA 00000100 .. 0 ..... 110 ... ..... ..... @rdn_pg_ra_rm # MAD 429MLS 00000100 .. 0 ..... 111 ... ..... ..... @rdn_pg_ra_rm # MSB 430 431### SVE Integer Arithmetic - Unpredicated Group 432 433# SVE integer add/subtract vectors (unpredicated) 434ADD_zzz 00000100 .. 1 ..... 000 000 ..... ..... @rd_rn_rm 435SUB_zzz 00000100 .. 1 ..... 000 001 ..... ..... @rd_rn_rm 436SQADD_zzz 00000100 .. 1 ..... 000 100 ..... ..... @rd_rn_rm 437UQADD_zzz 00000100 .. 1 ..... 000 101 ..... ..... @rd_rn_rm 438SQSUB_zzz 00000100 .. 1 ..... 000 110 ..... ..... @rd_rn_rm 439UQSUB_zzz 00000100 .. 1 ..... 000 111 ..... ..... @rd_rn_rm 440 441### SVE Logical - Unpredicated Group 442 443# SVE bitwise logical operations (unpredicated) 444AND_zzz 00000100 00 1 ..... 001 100 ..... ..... @rd_rn_rm_e0 445ORR_zzz 00000100 01 1 ..... 001 100 ..... ..... @rd_rn_rm_e0 446EOR_zzz 00000100 10 1 ..... 001 100 ..... ..... @rd_rn_rm_e0 447BIC_zzz 00000100 11 1 ..... 001 100 ..... ..... @rd_rn_rm_e0 448 449XAR 00000100 .. 1 ..... 001 101 rm:5 rd:5 &rrri_esz \ 450 rn=%reg_movprfx esz=%tszimm16_esz imm=%tszimm16_shr 451 452# SVE2 bitwise ternary operations 453EOR3 00000100 00 1 ..... 001 110 ..... ..... @rdn_ra_rm_ex esz=0 454BSL 00000100 00 1 ..... 001 111 ..... ..... @rdn_ra_rm_ex esz=0 455BCAX 00000100 01 1 ..... 001 110 ..... ..... @rdn_ra_rm_ex esz=0 456BSL1N 00000100 01 1 ..... 001 111 ..... ..... @rdn_ra_rm_ex esz=0 457BSL2N 00000100 10 1 ..... 001 111 ..... ..... @rdn_ra_rm_ex esz=0 458NBSL 00000100 11 1 ..... 001 111 ..... ..... @rdn_ra_rm_ex esz=0 459 460### SVE Index Generation Group 461 462# SVE index generation (immediate start, immediate increment) 463INDEX_ii 00000100 esz:2 1 imm2:s5 010000 imm1:s5 rd:5 464 465# SVE index generation (immediate start, register increment) 466INDEX_ir 00000100 esz:2 1 rm:5 010010 imm:s5 rd:5 467 468# SVE index generation (register start, immediate increment) 469INDEX_ri 00000100 esz:2 1 imm:s5 010001 rn:5 rd:5 470 471# SVE index generation (register start, register increment) 472INDEX_rr 00000100 .. 1 ..... 010011 ..... ..... @rd_rn_rm 473 474### SVE / Streaming SVE Stack Allocation Group 475 476# SVE stack frame adjustment 477ADDVL 00000100 001 ..... 01010 ...... ..... @rd_rn_i6 478ADDSVL 00000100 001 ..... 01011 ...... ..... @rd_rn_i6 479ADDPL 00000100 011 ..... 01010 ...... ..... @rd_rn_i6 480ADDSPL 00000100 011 ..... 01011 ...... ..... @rd_rn_i6 481 482# SVE stack frame size 483RDVL 00000100 101 11111 01010 imm:s6 rd:5 484RDSVL 00000100 101 11111 01011 imm:s6 rd:5 485 486### SVE Bitwise Shift - Unpredicated Group 487 488# SVE bitwise shift by immediate (unpredicated) 489ASR_zzi 00000100 .. 1 ..... 1001 00 ..... ..... @rd_rn_tszimm_shr 490LSR_zzi 00000100 .. 1 ..... 1001 01 ..... ..... @rd_rn_tszimm_shr 491LSL_zzi 00000100 .. 1 ..... 1001 11 ..... ..... @rd_rn_tszimm_shl 492 493# SVE bitwise shift by wide elements (unpredicated) 494# Note esz != 3 495ASR_zzw 00000100 .. 1 ..... 1000 00 ..... ..... @rd_rn_rm 496LSR_zzw 00000100 .. 1 ..... 1000 01 ..... ..... @rd_rn_rm 497LSL_zzw 00000100 .. 1 ..... 1000 11 ..... ..... @rd_rn_rm 498 499### SVE Compute Vector Address Group 500 501# SVE vector address generation 502ADR_s32 00000100 00 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm 503ADR_u32 00000100 01 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm 504ADR_p32 00000100 10 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm 505ADR_p64 00000100 11 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm 506 507### SVE Integer Misc - Unpredicated Group 508 509# SVE constructive prefix (unpredicated) 510MOVPRFX 00000100 00 1 00000 101111 rn:5 rd:5 511 512# SVE floating-point exponential accelerator 513# Note esz != 0 514FEXPA 00000100 .. 1 00000 101110 ..... ..... @rd_rn 515 516# SVE floating-point trig select coefficient 517# Note esz != 0 518FTSSEL 00000100 .. 1 ..... 101100 ..... ..... @rd_rn_rm 519 520### SVE Element Count Group 521 522# SVE element count 523CNT_r 00000100 .. 10 .... 1110 0 0 ..... ..... @incdec_cnt d=0 u=1 524 525# SVE inc/dec register by element count 526INCDEC_r 00000100 .. 11 .... 1110 0 d:1 ..... ..... @incdec_cnt u=1 527 528# SVE saturating inc/dec register by element count 529SINCDEC_r_32 00000100 .. 10 .... 1111 d:1 u:1 ..... ..... @incdec_cnt 530SINCDEC_r_64 00000100 .. 11 .... 1111 d:1 u:1 ..... ..... @incdec_cnt 531 532# SVE inc/dec vector by element count 533# Note this requires esz != 0. 534INCDEC_v 00000100 .. 1 1 .... 1100 0 d:1 ..... ..... @incdec2_cnt u=1 535 536# SVE saturating inc/dec vector by element count 537# Note these require esz != 0. 538SINCDEC_v 00000100 .. 1 0 .... 1100 d:1 u:1 ..... ..... @incdec2_cnt 539 540### SVE Bitwise Immediate Group 541 542# SVE bitwise logical with immediate (unpredicated) 543ORR_zzi 00000101 00 0000 ............. ..... @rdn_dbm 544EOR_zzi 00000101 01 0000 ............. ..... @rdn_dbm 545AND_zzi 00000101 10 0000 ............. ..... @rdn_dbm 546 547# SVE broadcast bitmask immediate 548DUPM 00000101 11 0000 dbm:13 rd:5 549 550### SVE Integer Wide Immediate - Predicated Group 551 552# SVE copy floating-point immediate (predicated) 553FCPY 00000101 .. 01 .... 110 imm:8 ..... @rdn_pg4 554 555# SVE copy integer immediate (predicated) 556{ 557 INVALID 00000101 00 01 ---- 01 1 -------- ----- 558 CPY_m_i 00000101 .. 01 .... 01 . ........ ..... @rdn_pg4 imm=%sh8_i8s 559} 560{ 561 INVALID 00000101 00 01 ---- 00 1 -------- ----- 562 CPY_z_i 00000101 .. 01 .... 00 . ........ ..... @rdn_pg4 imm=%sh8_i8s 563} 564 565### SVE Permute - Extract Group 566 567# SVE extract vector (destructive) 568EXT 00000101 001 ..... 000 ... rm:5 rd:5 \ 569 &rrri rn=%reg_movprfx imm=%imm8_16_10 570 571# SVE2 extract vector (constructive) 572EXT_sve2 00000101 011 ..... 000 ... rn:5 rd:5 \ 573 &rri imm=%imm8_16_10 574 575### SVE Permute - Unpredicated Group 576 577# SVE broadcast general register 578DUP_s 00000101 .. 1 00000 001110 ..... ..... @rd_rn 579 580# SVE broadcast indexed element 581DUP_x 00000101 .. 1 ..... 001000 rn:5 rd:5 \ 582 &rri imm=%imm7_22_16 583 584# SVE Permute Vector - one source quadwords 585DUPQ 00000101 001 imm:4 1 001001 rn:5 rd:5 &rri_esz esz=0 586DUPQ 00000101 001 imm:3 10 001001 rn:5 rd:5 &rri_esz esz=1 587DUPQ 00000101 001 imm:2 100 001001 rn:5 rd:5 &rri_esz esz=2 588DUPQ 00000101 001 imm:1 1000 001001 rn:5 rd:5 &rri_esz esz=3 589 590EXTQ 00000101 0110 imm:4 001001 rn:5 rd:5 &rri 591 592# SVE insert SIMD&FP scalar register 593INSR_f 00000101 .. 1 10100 001110 ..... ..... @rdn_rm 594 595# SVE insert general register 596INSR_r 00000101 .. 1 00100 001110 ..... ..... @rdn_rm 597 598# SVE reverse vector elements 599REV_v 00000101 .. 1 11000 001110 ..... ..... @rd_rn 600 601# SVE move predicate to/from vector 602 603PMOV_pv 00000101 00 101 01 0001110 rn:5 0 rd:4 \ 604 &rri_esz esz=0 imm=0 605PMOV_pv 00000101 00 101 1 imm:1 0001110 rn:5 0 rd:4 &rri_esz esz=1 606PMOV_pv 00000101 01 101 imm:2 0001110 rn:5 0 rd:4 &rri_esz esz=2 607PMOV_pv 00000101 1. 101 .. 0001110 rn:5 0 rd:4 \ 608 &rri_esz esz=3 imm=%index3_22_17 609 610PMOV_vp 00000101 00 101 01 1001110 0 rn:4 rd:5 \ 611 &rri_esz esz=0 imm=0 612PMOV_vp 00000101 00 101 1 imm:1 1001110 0 rn:4 rd:5 &rri_esz esz=1 613PMOV_vp 00000101 01 101 imm:2 1001110 0 rn:4 rd:5 &rri_esz esz=2 614PMOV_vp 00000101 1. 101 .. 1001110 0 rn:4 rd:5 \ 615 &rri_esz esz=3 imm=%index3_22_17 616 617# SVE vector table lookup 618TBL 00000101 .. 1 ..... 001100 ..... ..... @rd_rn_rm 619 620# SVE unpack vector elements 621UNPK 00000101 esz:2 1100 u:1 h:1 001110 rn:5 rd:5 622 623# SVE2 Table Lookup (three sources) 624 625TBL_sve2 00000101 .. 1 ..... 001010 ..... ..... @rd_rn_rm 626TBX 00000101 .. 1 ..... 001011 ..... ..... @rd_rn_rm 627 628### SVE Permute - Predicates Group 629 630# SVE permute predicate elements 631ZIP1_p 00000101 .. 10 .... 010 000 0 .... 0 .... @pd_pn_pm 632ZIP2_p 00000101 .. 10 .... 010 001 0 .... 0 .... @pd_pn_pm 633UZP1_p 00000101 .. 10 .... 010 010 0 .... 0 .... @pd_pn_pm 634UZP2_p 00000101 .. 10 .... 010 011 0 .... 0 .... @pd_pn_pm 635TRN1_p 00000101 .. 10 .... 010 100 0 .... 0 .... @pd_pn_pm 636TRN2_p 00000101 .. 10 .... 010 101 0 .... 0 .... @pd_pn_pm 637 638# SVE reverse predicate elements 639REV_p 00000101 .. 11 0100 010 000 0 .... 0 .... @pd_pn 640 641# SVE unpack predicate elements 642PUNPKLO 00000101 00 11 0000 010 000 0 .... 0 .... @pd_pn_e0 643PUNPKHI 00000101 00 11 0001 010 000 0 .... 0 .... @pd_pn_e0 644 645### SVE Permute - Interleaving Group 646 647# SVE permute vector elements 648ZIP1_z 00000101 .. 1 ..... 011 000 ..... ..... @rd_rn_rm 649ZIP2_z 00000101 .. 1 ..... 011 001 ..... ..... @rd_rn_rm 650UZP1_z 00000101 .. 1 ..... 011 010 ..... ..... @rd_rn_rm 651UZP2_z 00000101 .. 1 ..... 011 011 ..... ..... @rd_rn_rm 652TRN1_z 00000101 .. 1 ..... 011 100 ..... ..... @rd_rn_rm 653TRN2_z 00000101 .. 1 ..... 011 101 ..... ..... @rd_rn_rm 654 655# SVE2 permute vector segments 656ZIP1_q 00000101 10 1 ..... 000 000 ..... ..... @rd_rn_rm_e0 657ZIP2_q 00000101 10 1 ..... 000 001 ..... ..... @rd_rn_rm_e0 658UZP1_q 00000101 10 1 ..... 000 010 ..... ..... @rd_rn_rm_e0 659UZP2_q 00000101 10 1 ..... 000 011 ..... ..... @rd_rn_rm_e0 660TRN1_q 00000101 10 1 ..... 000 110 ..... ..... @rd_rn_rm_e0 661TRN2_q 00000101 10 1 ..... 000 111 ..... ..... @rd_rn_rm_e0 662 663# SVE2.1 permute vector elements (quadwords) 664ZIPQ1 01000100 .. 0 ..... 111 000 ..... ..... @rd_rn_rm 665ZIPQ2 01000100 .. 0 ..... 111 001 ..... ..... @rd_rn_rm 666UZPQ1 01000100 .. 0 ..... 111 010 ..... ..... @rd_rn_rm 667UZPQ2 01000100 .. 0 ..... 111 011 ..... ..... @rd_rn_rm 668 669TBLQ 01000100 .. 0 ..... 111 110 ..... ..... @rd_rn_rm 670TBXQ 00000101 .. 1 ..... 001 101 ..... ..... @rd_rn_rm 671 672### SVE Permute - Predicated Group 673 674# SVE compress active elements 675# Note esz >= 2 676COMPACT 00000101 .. 100001 100 ... ..... ..... @rd_pg_rn 677 678# SVE conditionally broadcast element to vector 679CLASTA_z 00000101 .. 10100 0 100 ... ..... ..... @rdn_pg_rm 680CLASTB_z 00000101 .. 10100 1 100 ... ..... ..... @rdn_pg_rm 681 682# SVE conditionally copy element to SIMD&FP scalar 683CLASTA_v 00000101 .. 10101 0 100 ... ..... ..... @rd_pg_rn 684CLASTB_v 00000101 .. 10101 1 100 ... ..... ..... @rd_pg_rn 685 686# SVE conditionally copy element to general register 687CLASTA_r 00000101 .. 11000 0 101 ... ..... ..... @rd_pg_rn 688CLASTB_r 00000101 .. 11000 1 101 ... ..... ..... @rd_pg_rn 689 690# SVE copy element to SIMD&FP scalar register 691LASTA_v 00000101 .. 10001 0 100 ... ..... ..... @rd_pg_rn 692LASTB_v 00000101 .. 10001 1 100 ... ..... ..... @rd_pg_rn 693 694# SVE copy element to general register 695LASTA_r 00000101 .. 10000 0 101 ... ..... ..... @rd_pg_rn 696LASTB_r 00000101 .. 10000 1 101 ... ..... ..... @rd_pg_rn 697 698# SVE copy element from SIMD&FP scalar register 699CPY_m_v 00000101 .. 100000 100 ... ..... ..... @rd_pg_rn 700 701# SVE copy element from general register to vector (predicated) 702CPY_m_r 00000101 .. 101000 101 ... ..... ..... @rd_pg_rn 703 704# SVE reverse within elements 705# Note esz >= operation size 706REVB 00000101 .. 1001 00 100 ... ..... ..... @rd_pg_rn 707REVH 00000101 .. 1001 01 100 ... ..... ..... @rd_pg_rn 708REVW 00000101 .. 1001 10 100 ... ..... ..... @rd_pg_rn 709RBIT 00000101 .. 1001 11 100 ... ..... ..... @rd_pg_rn 710REVD 00000101 00 1011 10 100 ... ..... ..... @rd_pg_rn_e0 711 712# SVE vector splice (predicated, destructive) 713SPLICE 00000101 .. 101 100 100 ... ..... ..... @rdn_pg_rm 714 715# SVE2 vector splice (predicated, constructive) 716SPLICE_sve2 00000101 .. 101 101 100 ... ..... ..... @rd_pg_rn 717 718### SVE Select Vectors Group 719 720# SVE select vector elements (predicated) 721SEL_zpzz 00000101 .. 1 ..... 11 .... ..... ..... @rd_pg4_rn_rm 722 723### SVE Integer Compare - Vectors Group 724 725# SVE integer compare_vectors 726CMPHS_ppzz 00100100 .. 0 ..... 000 ... ..... 0 .... @pd_pg_rn_rm 727CMPHI_ppzz 00100100 .. 0 ..... 000 ... ..... 1 .... @pd_pg_rn_rm 728CMPGE_ppzz 00100100 .. 0 ..... 100 ... ..... 0 .... @pd_pg_rn_rm 729CMPGT_ppzz 00100100 .. 0 ..... 100 ... ..... 1 .... @pd_pg_rn_rm 730CMPEQ_ppzz 00100100 .. 0 ..... 101 ... ..... 0 .... @pd_pg_rn_rm 731CMPNE_ppzz 00100100 .. 0 ..... 101 ... ..... 1 .... @pd_pg_rn_rm 732 733# SVE integer compare with wide elements 734# Note these require esz != 3. 735CMPEQ_ppzw 00100100 .. 0 ..... 001 ... ..... 0 .... @pd_pg_rn_rm 736CMPNE_ppzw 00100100 .. 0 ..... 001 ... ..... 1 .... @pd_pg_rn_rm 737CMPGE_ppzw 00100100 .. 0 ..... 010 ... ..... 0 .... @pd_pg_rn_rm 738CMPGT_ppzw 00100100 .. 0 ..... 010 ... ..... 1 .... @pd_pg_rn_rm 739CMPLT_ppzw 00100100 .. 0 ..... 011 ... ..... 0 .... @pd_pg_rn_rm 740CMPLE_ppzw 00100100 .. 0 ..... 011 ... ..... 1 .... @pd_pg_rn_rm 741CMPHS_ppzw 00100100 .. 0 ..... 110 ... ..... 0 .... @pd_pg_rn_rm 742CMPHI_ppzw 00100100 .. 0 ..... 110 ... ..... 1 .... @pd_pg_rn_rm 743CMPLO_ppzw 00100100 .. 0 ..... 111 ... ..... 0 .... @pd_pg_rn_rm 744CMPLS_ppzw 00100100 .. 0 ..... 111 ... ..... 1 .... @pd_pg_rn_rm 745 746### SVE Integer Compare - Unsigned Immediate Group 747 748# SVE integer compare with unsigned immediate 749CMPHS_ppzi 00100100 .. 1 ....... 0 ... ..... 0 .... @pd_pg_rn_i7 750CMPHI_ppzi 00100100 .. 1 ....... 0 ... ..... 1 .... @pd_pg_rn_i7 751CMPLO_ppzi 00100100 .. 1 ....... 1 ... ..... 0 .... @pd_pg_rn_i7 752CMPLS_ppzi 00100100 .. 1 ....... 1 ... ..... 1 .... @pd_pg_rn_i7 753 754### SVE Integer Compare - Signed Immediate Group 755 756# SVE integer compare with signed immediate 757CMPGE_ppzi 00100101 .. 0 ..... 000 ... ..... 0 .... @pd_pg_rn_i5 758CMPGT_ppzi 00100101 .. 0 ..... 000 ... ..... 1 .... @pd_pg_rn_i5 759CMPLT_ppzi 00100101 .. 0 ..... 001 ... ..... 0 .... @pd_pg_rn_i5 760CMPLE_ppzi 00100101 .. 0 ..... 001 ... ..... 1 .... @pd_pg_rn_i5 761CMPEQ_ppzi 00100101 .. 0 ..... 100 ... ..... 0 .... @pd_pg_rn_i5 762CMPNE_ppzi 00100101 .. 0 ..... 100 ... ..... 1 .... @pd_pg_rn_i5 763 764### SVE Predicate Logical Operations Group 765 766# SVE predicate logical operations 767AND_pppp 00100101 0. 00 .... 01 .... 0 .... 0 .... @pd_pg_pn_pm_s 768BIC_pppp 00100101 0. 00 .... 01 .... 0 .... 1 .... @pd_pg_pn_pm_s 769EOR_pppp 00100101 0. 00 .... 01 .... 1 .... 0 .... @pd_pg_pn_pm_s 770SEL_pppp 00100101 0. 00 .... 01 .... 1 .... 1 .... @pd_pg_pn_pm_s 771ORR_pppp 00100101 1. 00 .... 01 .... 0 .... 0 .... @pd_pg_pn_pm_s 772ORN_pppp 00100101 1. 00 .... 01 .... 0 .... 1 .... @pd_pg_pn_pm_s 773NOR_pppp 00100101 1. 00 .... 01 .... 1 .... 0 .... @pd_pg_pn_pm_s 774NAND_pppp 00100101 1. 00 .... 01 .... 1 .... 1 .... @pd_pg_pn_pm_s 775 776### SVE Predicate Misc Group 777 778# SVE predicate test 779PTEST 00100101 01 010000 11 pg:4 0 rn:4 0 0000 780 781# SVE predicate initialize 782PTRUE 00100101 esz:2 01100 s:1 111000 pat:5 0 rd:4 783PTRUE_cnt 00100101 esz:2 1000000111100000010 ... rd=%pnd 784 785# SVE initialize FFR 786SETFFR 00100101 0010 1100 1001 0000 0000 0000 787 788# SVE zero predicate register 789PFALSE 00100101 0001 1000 1110 0100 0000 rd:4 790 791# SVE predicate read from FFR (predicated) 792RDFFR_p 00100101 0 s:1 0110001111000 pg:4 0 rd:4 793 794# SVE predicate read from FFR (unpredicated) 795RDFFR 00100101 0001 1001 1111 0000 0000 rd:4 796 797# SVE FFR write from predicate (WRFFR) 798WRFFR 00100101 0010 1000 1001 000 rn:4 00000 799 800# SVE predicate first active 801PFIRST 00100101 01 011 000 11000 00 .... 0 .... @pd_pn_e0 802 803# SVE predicate next active 804PNEXT 00100101 .. 011 001 11000 10 .... 0 .... @pd_pn 805 806### SVE Partition Break Group 807 808# SVE propagate break from previous partition 809BRKPA 00100101 0. 00 .... 11 .... 0 .... 0 .... @pd_pg_pn_pm_s 810BRKPB 00100101 0. 00 .... 11 .... 0 .... 1 .... @pd_pg_pn_pm_s 811 812# SVE partition break condition 813BRKA_z 00100101 0. 01000001 .... 0 .... 0 .... @pd_pg_pn_s 814BRKB_z 00100101 1. 01000001 .... 0 .... 0 .... @pd_pg_pn_s 815BRKA_m 00100101 00 01000001 .... 0 .... 1 .... @pd_pg_pn_s0 816BRKB_m 00100101 10 01000001 .... 0 .... 1 .... @pd_pg_pn_s0 817 818# SVE propagate break to next partition 819BRKN 00100101 0. 01100001 .... 0 .... 0 .... @pd_pg_pn_s 820 821### SVE Predicate Count Group 822 823# SVE predicate count 824CNTP 00100101 .. 100 000 10 .... 0 .... ..... @rd_pg4_pn 825CNTP_c 00100101 esz:2 100 000 10 000 vl:1 1 rn:4 rd:5 826 827# SVE inc/dec register by predicate count 828INCDECP_r 00100101 .. 10110 d:1 10001 00 .... ..... @incdec_pred u=1 829 830# SVE inc/dec vector by predicate count 831INCDECP_z 00100101 .. 10110 d:1 10000 00 .... ..... @incdec2_pred u=1 832 833# SVE saturating inc/dec register by predicate count 834SINCDECP_r_32 00100101 .. 1010 d:1 u:1 10001 00 .... ..... @incdec_pred 835SINCDECP_r_64 00100101 .. 1010 d:1 u:1 10001 10 .... ..... @incdec_pred 836 837# SVE saturating inc/dec vector by predicate count 838SINCDECP_z 00100101 .. 1010 d:1 u:1 10000 00 .... ..... @incdec2_pred 839 840### SVE Integer Compare - Scalars Group 841 842# SVE conditionally terminate scalars 843CTERM 00100101 1 sf:1 1 rm:5 001000 rn:5 ne:1 0000 844 845# SVE integer compare scalar count and limit 846&while esz rd rn rm sf u eq 847WHILE_lt 00100101 esz:2 1 rm:5 000 sf:1 u:1 1 rn:5 eq:1 rd:4 &while 848WHILE_gt 00100101 esz:2 1 rm:5 000 sf:1 u:1 0 rn:5 eq:1 rd:4 &while 849 850# SVE2 pointer conflict compare 851WHILE_ptr 00100101 esz:2 1 rm:5 001 100 rn:5 rw:1 rd:4 852 853# SVE2.1 predicate pair 854%pd_pair 1:3 !function=times_2 855@while_pair ........ esz:2 . rm:5 .... u:1 . rn:5 . ... eq:1 \ 856 &while rd=%pd_pair sf=1 857 858WHILE_lt_pair 00100101 .. 1 ..... 0101 . 1 ..... 1 ... . @while_pair 859WHILE_gt_pair 00100101 .. 1 ..... 0101 . 0 ..... 1 ... . @while_pair 860 861# SVE2.1 predicate as count 862@while_cnt ........ esz:2 . rm:5 .... u:1 . rn:5 . eq:1 ... \ 863 &while rd=%pnd sf=1 864 865WHILE_lt_cnt2 00100101 .. 1 ..... 0100 . 1 ..... 1 . ... @while_cnt 866WHILE_lt_cnt4 00100101 .. 1 ..... 0110 . 1 ..... 1 . ... @while_cnt 867WHILE_gt_cnt2 00100101 .. 1 ..... 0100 . 0 ..... 1 . ... @while_cnt 868WHILE_gt_cnt4 00100101 .. 1 ..... 0110 . 0 ..... 1 . ... @while_cnt 869 870# SVE2.1 extract mask predicate from predicate-as-counter 871&pext rd rn esz imm 872PEXT_1 00100101 esz:2 1 00000 0111 00 imm:2 ... 1 rd:4 &pext rn=%pnn 873PEXT_2 00100101 esz:2 1 00000 0111 010 imm:1 ... 1 rd:4 &pext rn=%pnn 874 875### SVE Integer Wide Immediate - Unpredicated Group 876 877# SVE broadcast floating-point immediate (unpredicated) 878FDUP 00100101 esz:2 111 00 1110 imm:8 rd:5 879 880# SVE broadcast integer immediate (unpredicated) 881{ 882 INVALID 00100101 00 111 00 011 1 -------- ----- 883 DUP_i 00100101 esz:2 111 00 011 . ........ rd:5 imm=%sh8_i8s 884} 885 886# SVE integer add/subtract immediate (unpredicated) 887{ 888 INVALID 00100101 00 100 000 11 1 -------- ----- 889 ADD_zzi 00100101 .. 100 000 11 . ........ ..... @rdn_sh_i8u 890} 891{ 892 INVALID 00100101 00 100 001 11 1 -------- ----- 893 SUB_zzi 00100101 .. 100 001 11 . ........ ..... @rdn_sh_i8u 894} 895{ 896 INVALID 00100101 00 100 011 11 1 -------- ----- 897 SUBR_zzi 00100101 .. 100 011 11 . ........ ..... @rdn_sh_i8u 898} 899{ 900 INVALID 00100101 00 100 100 11 1 -------- ----- 901 SQADD_zzi 00100101 .. 100 100 11 . ........ ..... @rdn_sh_i8u 902} 903{ 904 INVALID 00100101 00 100 101 11 1 -------- ----- 905 UQADD_zzi 00100101 .. 100 101 11 . ........ ..... @rdn_sh_i8u 906} 907{ 908 INVALID 00100101 00 100 110 11 1 -------- ----- 909 SQSUB_zzi 00100101 .. 100 110 11 . ........ ..... @rdn_sh_i8u 910} 911{ 912 INVALID 00100101 00 100 111 11 1 -------- ----- 913 UQSUB_zzi 00100101 .. 100 111 11 . ........ ..... @rdn_sh_i8u 914} 915 916# SVE integer min/max immediate (unpredicated) 917SMAX_zzi 00100101 .. 101 000 110 ........ ..... @rdn_i8s 918UMAX_zzi 00100101 .. 101 001 110 ........ ..... @rdn_i8u 919SMIN_zzi 00100101 .. 101 010 110 ........ ..... @rdn_i8s 920UMIN_zzi 00100101 .. 101 011 110 ........ ..... @rdn_i8u 921 922# SVE integer multiply immediate (unpredicated) 923MUL_zzi 00100101 .. 110 000 110 ........ ..... @rdn_i8s 924 925# SVE integer dot product (unpredicated) 926DOT_zzzz 01000100 1 sz:1 0 rm:5 00000 u:1 rn:5 rd:5 \ 927 ra=%reg_movprfx 928 929# SVE2 complex dot product (vectors) 930CDOT_zzzz 01000100 esz:2 0 rm:5 0001 rot:2 rn:5 rd:5 ra=%reg_movprfx 931 932#### SVE Multiply - Indexed 933 934# SVE integer dot product (indexed) 935SDOT_zzxw_4s 01000100 10 1 ..... 000000 ..... ..... @rrxr_2 esz=2 936SDOT_zzxw_4d 01000100 11 1 ..... 000000 ..... ..... @rrxr_1 esz=3 937UDOT_zzxw_4s 01000100 10 1 ..... 000001 ..... ..... @rrxr_2 esz=2 938UDOT_zzxw_4d 01000100 11 1 ..... 000001 ..... ..... @rrxr_1 esz=3 939 940SDOT_zzxw_2s 01000100 10 0 ..... 110010 ..... ..... @rrxr_2 esz=2 941UDOT_zzxw_2s 01000100 10 0 ..... 110011 ..... ..... @rrxr_2 esz=2 942 943# SVE2 integer multiply-add (indexed) 944MLA_zzxz_h 01000100 0. 1 ..... 000010 ..... ..... @rrxr_3 esz=1 945MLA_zzxz_s 01000100 10 1 ..... 000010 ..... ..... @rrxr_2 esz=2 946MLA_zzxz_d 01000100 11 1 ..... 000010 ..... ..... @rrxr_1 esz=3 947MLS_zzxz_h 01000100 0. 1 ..... 000011 ..... ..... @rrxr_3 esz=1 948MLS_zzxz_s 01000100 10 1 ..... 000011 ..... ..... @rrxr_2 esz=2 949MLS_zzxz_d 01000100 11 1 ..... 000011 ..... ..... @rrxr_1 esz=3 950 951# SVE2 saturating multiply-add high (indexed) 952SQRDMLAH_zzxz_h 01000100 0. 1 ..... 000100 ..... ..... @rrxr_3 esz=1 953SQRDMLAH_zzxz_s 01000100 10 1 ..... 000100 ..... ..... @rrxr_2 esz=2 954SQRDMLAH_zzxz_d 01000100 11 1 ..... 000100 ..... ..... @rrxr_1 esz=3 955SQRDMLSH_zzxz_h 01000100 0. 1 ..... 000101 ..... ..... @rrxr_3 esz=1 956SQRDMLSH_zzxz_s 01000100 10 1 ..... 000101 ..... ..... @rrxr_2 esz=2 957SQRDMLSH_zzxz_d 01000100 11 1 ..... 000101 ..... ..... @rrxr_1 esz=3 958 959# SVE mixed sign dot product (indexed) 960USDOT_zzxw_4s 01000100 10 1 ..... 000110 ..... ..... @rrxr_2 esz=2 961SUDOT_zzxw_4s 01000100 10 1 ..... 000111 ..... ..... @rrxr_2 esz=2 962 963# SVE2 saturating multiply-add (indexed) 964SQDMLALB_zzxw_s 01000100 10 1 ..... 0010.0 ..... ..... @rrxr_3a esz=2 965SQDMLALB_zzxw_d 01000100 11 1 ..... 0010.0 ..... ..... @rrxr_2a esz=3 966SQDMLALT_zzxw_s 01000100 10 1 ..... 0010.1 ..... ..... @rrxr_3a esz=2 967SQDMLALT_zzxw_d 01000100 11 1 ..... 0010.1 ..... ..... @rrxr_2a esz=3 968SQDMLSLB_zzxw_s 01000100 10 1 ..... 0011.0 ..... ..... @rrxr_3a esz=2 969SQDMLSLB_zzxw_d 01000100 11 1 ..... 0011.0 ..... ..... @rrxr_2a esz=3 970SQDMLSLT_zzxw_s 01000100 10 1 ..... 0011.1 ..... ..... @rrxr_3a esz=2 971SQDMLSLT_zzxw_d 01000100 11 1 ..... 0011.1 ..... ..... @rrxr_2a esz=3 972 973# SVE2 complex integer dot product (indexed) 974CDOT_zzxw_s 01000100 10 1 index:2 rm:3 0100 rot:2 rn:5 rd:5 \ 975 ra=%reg_movprfx 976CDOT_zzxw_d 01000100 11 1 index:1 rm:4 0100 rot:2 rn:5 rd:5 \ 977 ra=%reg_movprfx 978 979# SVE2 complex integer multiply-add (indexed) 980CMLA_zzxz_h 01000100 10 1 index:2 rm:3 0110 rot:2 rn:5 rd:5 \ 981 ra=%reg_movprfx 982CMLA_zzxz_s 01000100 11 1 index:1 rm:4 0110 rot:2 rn:5 rd:5 \ 983 ra=%reg_movprfx 984 985# SVE2 complex saturating integer multiply-add (indexed) 986SQRDCMLAH_zzxz_h 01000100 10 1 index:2 rm:3 0111 rot:2 rn:5 rd:5 \ 987 ra=%reg_movprfx 988SQRDCMLAH_zzxz_s 01000100 11 1 index:1 rm:4 0111 rot:2 rn:5 rd:5 \ 989 ra=%reg_movprfx 990 991# SVE2 multiply-add long (indexed) 992SMLALB_zzxw_s 01000100 10 1 ..... 1000.0 ..... ..... @rrxr_3a esz=2 993SMLALB_zzxw_d 01000100 11 1 ..... 1000.0 ..... ..... @rrxr_2a esz=3 994SMLALT_zzxw_s 01000100 10 1 ..... 1000.1 ..... ..... @rrxr_3a esz=2 995SMLALT_zzxw_d 01000100 11 1 ..... 1000.1 ..... ..... @rrxr_2a esz=3 996UMLALB_zzxw_s 01000100 10 1 ..... 1001.0 ..... ..... @rrxr_3a esz=2 997UMLALB_zzxw_d 01000100 11 1 ..... 1001.0 ..... ..... @rrxr_2a esz=3 998UMLALT_zzxw_s 01000100 10 1 ..... 1001.1 ..... ..... @rrxr_3a esz=2 999UMLALT_zzxw_d 01000100 11 1 ..... 1001.1 ..... ..... @rrxr_2a esz=3 1000SMLSLB_zzxw_s 01000100 10 1 ..... 1010.0 ..... ..... @rrxr_3a esz=2 1001SMLSLB_zzxw_d 01000100 11 1 ..... 1010.0 ..... ..... @rrxr_2a esz=3 1002SMLSLT_zzxw_s 01000100 10 1 ..... 1010.1 ..... ..... @rrxr_3a esz=2 1003SMLSLT_zzxw_d 01000100 11 1 ..... 1010.1 ..... ..... @rrxr_2a esz=3 1004UMLSLB_zzxw_s 01000100 10 1 ..... 1011.0 ..... ..... @rrxr_3a esz=2 1005UMLSLB_zzxw_d 01000100 11 1 ..... 1011.0 ..... ..... @rrxr_2a esz=3 1006UMLSLT_zzxw_s 01000100 10 1 ..... 1011.1 ..... ..... @rrxr_3a esz=2 1007UMLSLT_zzxw_d 01000100 11 1 ..... 1011.1 ..... ..... @rrxr_2a esz=3 1008 1009# SVE2 integer multiply long (indexed) 1010SMULLB_zzx_s 01000100 10 1 ..... 1100.0 ..... ..... @rrx_3a esz=2 1011SMULLB_zzx_d 01000100 11 1 ..... 1100.0 ..... ..... @rrx_2a esz=3 1012SMULLT_zzx_s 01000100 10 1 ..... 1100.1 ..... ..... @rrx_3a esz=2 1013SMULLT_zzx_d 01000100 11 1 ..... 1100.1 ..... ..... @rrx_2a esz=3 1014UMULLB_zzx_s 01000100 10 1 ..... 1101.0 ..... ..... @rrx_3a esz=2 1015UMULLB_zzx_d 01000100 11 1 ..... 1101.0 ..... ..... @rrx_2a esz=3 1016UMULLT_zzx_s 01000100 10 1 ..... 1101.1 ..... ..... @rrx_3a esz=2 1017UMULLT_zzx_d 01000100 11 1 ..... 1101.1 ..... ..... @rrx_2a esz=3 1018 1019# SVE2 saturating multiply (indexed) 1020SQDMULLB_zzx_s 01000100 10 1 ..... 1110.0 ..... ..... @rrx_3a esz=2 1021SQDMULLB_zzx_d 01000100 11 1 ..... 1110.0 ..... ..... @rrx_2a esz=3 1022SQDMULLT_zzx_s 01000100 10 1 ..... 1110.1 ..... ..... @rrx_3a esz=2 1023SQDMULLT_zzx_d 01000100 11 1 ..... 1110.1 ..... ..... @rrx_2a esz=3 1024 1025# SVE2 saturating multiply high (indexed) 1026SQDMULH_zzx_h 01000100 0. 1 ..... 111100 ..... ..... @rrx_3 esz=1 1027SQDMULH_zzx_s 01000100 10 1 ..... 111100 ..... ..... @rrx_2 esz=2 1028SQDMULH_zzx_d 01000100 11 1 ..... 111100 ..... ..... @rrx_1 esz=3 1029SQRDMULH_zzx_h 01000100 0. 1 ..... 111101 ..... ..... @rrx_3 esz=1 1030SQRDMULH_zzx_s 01000100 10 1 ..... 111101 ..... ..... @rrx_2 esz=2 1031SQRDMULH_zzx_d 01000100 11 1 ..... 111101 ..... ..... @rrx_1 esz=3 1032 1033# SVE2 integer multiply (indexed) 1034MUL_zzx_h 01000100 0. 1 ..... 111110 ..... ..... @rrx_3 esz=1 1035MUL_zzx_s 01000100 10 1 ..... 111110 ..... ..... @rrx_2 esz=2 1036MUL_zzx_d 01000100 11 1 ..... 111110 ..... ..... @rrx_1 esz=3 1037 1038# SVE floating-point complex add (predicated) 1039FCADD 01100100 esz:2 00000 rot:1 100 pg:3 rm:5 rd:5 \ 1040 rn=%reg_movprfx 1041 1042# SVE floating-point complex multiply-add (predicated) 1043FCMLA_zpzzz 01100100 esz:2 0 rm:5 0 rot:2 pg:3 rn:5 rd:5 \ 1044 ra=%reg_movprfx 1045 1046# SVE floating-point complex multiply-add (indexed) 1047FCMLA_zzxz 01100100 10 1 index:2 rm:3 0001 rot:2 rn:5 rd:5 \ 1048 ra=%reg_movprfx esz=1 1049FCMLA_zzxz 01100100 11 1 index:1 rm:4 0001 rot:2 rn:5 rd:5 \ 1050 ra=%reg_movprfx esz=2 1051 1052### SVE FP Multiply-Add Indexed Group 1053 1054# SVE floating-point multiply-add (indexed) 1055FMLA_zzxz 01100100 0. 1 ..... 000010 ..... ..... @rrxr_3 esz=0 1056FMLA_zzxz 01100100 0. 1 ..... 000000 ..... ..... @rrxr_3 esz=1 1057FMLA_zzxz 01100100 10 1 ..... 000000 ..... ..... @rrxr_2 esz=2 1058FMLA_zzxz 01100100 11 1 ..... 000000 ..... ..... @rrxr_1 esz=3 1059FMLS_zzxz 01100100 0. 1 ..... 000011 ..... ..... @rrxr_3 esz=0 1060FMLS_zzxz 01100100 0. 1 ..... 000001 ..... ..... @rrxr_3 esz=1 1061FMLS_zzxz 01100100 10 1 ..... 000001 ..... ..... @rrxr_2 esz=2 1062FMLS_zzxz 01100100 11 1 ..... 000001 ..... ..... @rrxr_1 esz=3 1063 1064### SVE FP Multiply Indexed Group 1065 1066# SVE floating-point multiply (indexed) 1067FMUL_zzx 01100100 0. 1 ..... 001010 ..... ..... @rrx_3 esz=0 1068FMUL_zzx 01100100 0. 1 ..... 001000 ..... ..... @rrx_3 esz=1 1069FMUL_zzx 01100100 10 1 ..... 001000 ..... ..... @rrx_2 esz=2 1070FMUL_zzx 01100100 11 1 ..... 001000 ..... ..... @rrx_1 esz=3 1071 1072### SVE FP Fast Reduction Group 1073 1074FADDV 01100101 .. 000 000 001 ... ..... ..... @rd_pg_rn 1075FMAXNMV 01100101 .. 000 100 001 ... ..... ..... @rd_pg_rn 1076FMINNMV 01100101 .. 000 101 001 ... ..... ..... @rd_pg_rn 1077FMAXV 01100101 .. 000 110 001 ... ..... ..... @rd_pg_rn 1078FMINV 01100101 .. 000 111 001 ... ..... ..... @rd_pg_rn 1079 1080### SVE FP recursive reduction (quadwords) 1081 1082FADDQV 01100100 .. 010 000 101 ... ..... ..... @rd_pg_rn 1083FMAXNMQV 01100100 .. 010 100 101 ... ..... ..... @rd_pg_rn 1084FMINNMQV 01100100 .. 010 101 101 ... ..... ..... @rd_pg_rn 1085FMAXQV 01100100 .. 010 110 101 ... ..... ..... @rd_pg_rn 1086FMINQV 01100100 .. 010 111 101 ... ..... ..... @rd_pg_rn 1087 1088## SVE Floating Point Unary Operations - Unpredicated Group 1089 1090FRECPE 01100101 .. 001 110 001100 ..... ..... @rd_rn 1091FRSQRTE 01100101 .. 001 111 001100 ..... ..... @rd_rn 1092 1093### SVE FP Compare with Zero Group 1094 1095FCMGE_ppz0 01100101 .. 0100 00 001 ... ..... 0 .... @pd_pg_rn 1096FCMGT_ppz0 01100101 .. 0100 00 001 ... ..... 1 .... @pd_pg_rn 1097FCMLT_ppz0 01100101 .. 0100 01 001 ... ..... 0 .... @pd_pg_rn 1098FCMLE_ppz0 01100101 .. 0100 01 001 ... ..... 1 .... @pd_pg_rn 1099FCMEQ_ppz0 01100101 .. 0100 10 001 ... ..... 0 .... @pd_pg_rn 1100FCMNE_ppz0 01100101 .. 0100 11 001 ... ..... 0 .... @pd_pg_rn 1101 1102### SVE FP Accumulating Reduction Group 1103 1104# SVE floating-point serial reduction (predicated) 1105FADDA 01100101 .. 011 000 001 ... ..... ..... @rdn_pg_rm 1106 1107### SVE Floating Point Arithmetic - Unpredicated Group 1108 1109# SVE floating-point arithmetic (unpredicated) 1110FADD_zzz 01100101 .. 0 ..... 000 000 ..... ..... @rd_rn_rm 1111FSUB_zzz 01100101 .. 0 ..... 000 001 ..... ..... @rd_rn_rm 1112FMUL_zzz 01100101 .. 0 ..... 000 010 ..... ..... @rd_rn_rm 1113FTSMUL 01100101 .. 0 ..... 000 011 ..... ..... @rd_rn_rm 1114FRECPS 01100101 .. 0 ..... 000 110 ..... ..... @rd_rn_rm 1115FRSQRTS 01100101 .. 0 ..... 000 111 ..... ..... @rd_rn_rm 1116 1117### SVE FP Arithmetic Predicated Group 1118 1119# SVE floating-point arithmetic (predicated) 1120FADD_zpzz 01100101 .. 00 0000 100 ... ..... ..... @rdn_pg_rm 1121FSUB_zpzz 01100101 .. 00 0001 100 ... ..... ..... @rdn_pg_rm 1122FMUL_zpzz 01100101 .. 00 0010 100 ... ..... ..... @rdn_pg_rm 1123FSUB_zpzz 01100101 .. 00 0011 100 ... ..... ..... @rdm_pg_rn # FSUBR 1124FMAXNM_zpzz 01100101 .. 00 0100 100 ... ..... ..... @rdn_pg_rm 1125FMINNM_zpzz 01100101 .. 00 0101 100 ... ..... ..... @rdn_pg_rm 1126FMAX_zpzz 01100101 .. 00 0110 100 ... ..... ..... @rdn_pg_rm 1127FMIN_zpzz 01100101 .. 00 0111 100 ... ..... ..... @rdn_pg_rm 1128FABD 01100101 .. 00 1000 100 ... ..... ..... @rdn_pg_rm 1129FSCALE 01100101 .. 00 1001 100 ... ..... ..... @rdn_pg_rm 1130FMULX 01100101 .. 00 1010 100 ... ..... ..... @rdn_pg_rm 1131FDIV 01100101 .. 00 1100 100 ... ..... ..... @rdm_pg_rn # FDIVR 1132FDIV 01100101 .. 00 1101 100 ... ..... ..... @rdn_pg_rm 1133 1134# SVE floating-point arithmetic with immediate (predicated) 1135FADD_zpzi 01100101 .. 011 000 100 ... 0000 . ..... @rdn_i1 1136FSUB_zpzi 01100101 .. 011 001 100 ... 0000 . ..... @rdn_i1 1137FMUL_zpzi 01100101 .. 011 010 100 ... 0000 . ..... @rdn_i1 1138FSUBR_zpzi 01100101 .. 011 011 100 ... 0000 . ..... @rdn_i1 1139FMAXNM_zpzi 01100101 .. 011 100 100 ... 0000 . ..... @rdn_i1 1140FMINNM_zpzi 01100101 .. 011 101 100 ... 0000 . ..... @rdn_i1 1141FMAX_zpzi 01100101 .. 011 110 100 ... 0000 . ..... @rdn_i1 1142FMIN_zpzi 01100101 .. 011 111 100 ... 0000 . ..... @rdn_i1 1143 1144# SVE floating-point trig multiply-add coefficient 1145FTMAD 01100101 esz:2 010 imm:3 100000 rm:5 rd:5 rn=%reg_movprfx 1146 1147### SVE FP Multiply-Add Group 1148 1149# SVE floating-point multiply-accumulate writing addend 1150FMLA_zpzzz 01100101 .. 1 ..... 000 ... ..... ..... @rda_pg_rn_rm 1151FMLS_zpzzz 01100101 .. 1 ..... 001 ... ..... ..... @rda_pg_rn_rm 1152FNMLA_zpzzz 01100101 .. 1 ..... 010 ... ..... ..... @rda_pg_rn_rm 1153FNMLS_zpzzz 01100101 .. 1 ..... 011 ... ..... ..... @rda_pg_rn_rm 1154 1155# SVE floating-point multiply-accumulate writing multiplicand 1156# Alter the operand extraction order and reuse the helpers from above. 1157# FMAD, FMSB, FNMAD, FNMS 1158FMLA_zpzzz 01100101 .. 1 ..... 100 ... ..... ..... @rdn_pg_rm_ra 1159FMLS_zpzzz 01100101 .. 1 ..... 101 ... ..... ..... @rdn_pg_rm_ra 1160FNMLA_zpzzz 01100101 .. 1 ..... 110 ... ..... ..... @rdn_pg_rm_ra 1161FNMLS_zpzzz 01100101 .. 1 ..... 111 ... ..... ..... @rdn_pg_rm_ra 1162 1163### SVE FP Unary Operations Predicated Group 1164 1165# SVE floating-point convert precision 1166FCVT_sh 01100101 10 0010 00 101 ... ..... ..... @rd_pg_rn_e0 1167FCVT_hs 01100101 10 0010 01 101 ... ..... ..... @rd_pg_rn_e0 1168BFCVT 01100101 10 0010 10 101 ... ..... ..... @rd_pg_rn_e0 1169FCVT_dh 01100101 11 0010 00 101 ... ..... ..... @rd_pg_rn_e0 1170FCVT_hd 01100101 11 0010 01 101 ... ..... ..... @rd_pg_rn_e0 1171FCVT_ds 01100101 11 0010 10 101 ... ..... ..... @rd_pg_rn_e0 1172FCVT_sd 01100101 11 0010 11 101 ... ..... ..... @rd_pg_rn_e0 1173 1174# SVE floating-point convert to integer 1175FCVTZS_hh 01100101 01 011 01 0 101 ... ..... ..... @rd_pg_rn_e0 1176FCVTZU_hh 01100101 01 011 01 1 101 ... ..... ..... @rd_pg_rn_e0 1177FCVTZS_hs 01100101 01 011 10 0 101 ... ..... ..... @rd_pg_rn_e0 1178FCVTZU_hs 01100101 01 011 10 1 101 ... ..... ..... @rd_pg_rn_e0 1179FCVTZS_hd 01100101 01 011 11 0 101 ... ..... ..... @rd_pg_rn_e0 1180FCVTZU_hd 01100101 01 011 11 1 101 ... ..... ..... @rd_pg_rn_e0 1181FCVTZS_ss 01100101 10 011 10 0 101 ... ..... ..... @rd_pg_rn_e0 1182FCVTZU_ss 01100101 10 011 10 1 101 ... ..... ..... @rd_pg_rn_e0 1183FCVTZS_ds 01100101 11 011 00 0 101 ... ..... ..... @rd_pg_rn_e0 1184FCVTZU_ds 01100101 11 011 00 1 101 ... ..... ..... @rd_pg_rn_e0 1185FCVTZS_sd 01100101 11 011 10 0 101 ... ..... ..... @rd_pg_rn_e0 1186FCVTZU_sd 01100101 11 011 10 1 101 ... ..... ..... @rd_pg_rn_e0 1187FCVTZS_dd 01100101 11 011 11 0 101 ... ..... ..... @rd_pg_rn_e0 1188FCVTZU_dd 01100101 11 011 11 1 101 ... ..... ..... @rd_pg_rn_e0 1189 1190# SVE floating-point round to integral value 1191FRINTN 01100101 .. 000 000 101 ... ..... ..... @rd_pg_rn 1192FRINTP 01100101 .. 000 001 101 ... ..... ..... @rd_pg_rn 1193FRINTM 01100101 .. 000 010 101 ... ..... ..... @rd_pg_rn 1194FRINTZ 01100101 .. 000 011 101 ... ..... ..... @rd_pg_rn 1195FRINTA 01100101 .. 000 100 101 ... ..... ..... @rd_pg_rn 1196FRINTX 01100101 .. 000 110 101 ... ..... ..... @rd_pg_rn 1197FRINTI 01100101 .. 000 111 101 ... ..... ..... @rd_pg_rn 1198 1199# SVE floating-point unary operations 1200FRECPX 01100101 .. 001 100 101 ... ..... ..... @rd_pg_rn 1201FSQRT 01100101 .. 001 101 101 ... ..... ..... @rd_pg_rn 1202 1203# SVE integer convert to floating-point 1204SCVTF_hh 01100101 01 010 01 0 101 ... ..... ..... @rd_pg_rn_e0 1205SCVTF_sh 01100101 01 010 10 0 101 ... ..... ..... @rd_pg_rn_e0 1206SCVTF_dh 01100101 01 010 11 0 101 ... ..... ..... @rd_pg_rn_e0 1207SCVTF_ss 01100101 10 010 10 0 101 ... ..... ..... @rd_pg_rn_e0 1208SCVTF_sd 01100101 11 010 00 0 101 ... ..... ..... @rd_pg_rn_e0 1209SCVTF_ds 01100101 11 010 10 0 101 ... ..... ..... @rd_pg_rn_e0 1210SCVTF_dd 01100101 11 010 11 0 101 ... ..... ..... @rd_pg_rn_e0 1211 1212UCVTF_hh 01100101 01 010 01 1 101 ... ..... ..... @rd_pg_rn_e0 1213UCVTF_sh 01100101 01 010 10 1 101 ... ..... ..... @rd_pg_rn_e0 1214UCVTF_dh 01100101 01 010 11 1 101 ... ..... ..... @rd_pg_rn_e0 1215UCVTF_ss 01100101 10 010 10 1 101 ... ..... ..... @rd_pg_rn_e0 1216UCVTF_sd 01100101 11 010 00 1 101 ... ..... ..... @rd_pg_rn_e0 1217UCVTF_ds 01100101 11 010 10 1 101 ... ..... ..... @rd_pg_rn_e0 1218UCVTF_dd 01100101 11 010 11 1 101 ... ..... ..... @rd_pg_rn_e0 1219 1220### SVE Memory - 32-bit Gather and Unsized Contiguous Group 1221 1222# SVE load predicate register 1223LDR_pri 10000101 10 ...... 000 ... ..... 0 .... @pd_rn_i9 1224 1225# SVE load vector register 1226LDR_zri 10000101 10 ...... 010 ... ..... ..... @rd_rn_i9 1227 1228# SVE load and broadcast element 1229LD1R_zpri 1000010 .. 1 imm:6 1.. pg:3 rn:5 rd:5 \ 1230 &rpri_load dtype=%dtype_23_13 nreg=0 1231 1232# SVE 32-bit gather load (scalar plus 32-bit unscaled offsets) 1233# SVE 32-bit gather load (scalar plus 32-bit scaled offsets) 1234LD1_zprz 1000010 00 .0 ..... 0.. ... ..... ..... \ 1235 @rprr_g_load_xs_u esz=2 msz=0 scale=0 1236LD1_zprz 1000010 01 .. ..... 0.. ... ..... ..... \ 1237 @rprr_g_load_xs_u_sc esz=2 msz=1 1238LD1_zprz 1000010 10 .. ..... 01. ... ..... ..... \ 1239 @rprr_g_load_xs_sc esz=2 msz=2 u=1 1240 1241# SVE 32-bit gather load (vector plus immediate) 1242LD1_zpiz 1000010 .. 01 ..... 1.. ... ..... ..... \ 1243 @rpri_g_load esz=2 1244 1245### SVE Memory Contiguous Load Group 1246 1247# SVE contiguous load (scalar plus scalar) 1248LD_zprr 1010010 .... ..... 010 ... ..... ..... @rprr_load_dt nreg=0 1249# LD1W (128-bit element) 1250LD_zprr 1010010 1000 rm:5 100 pg:3 rn:5 rd:5 \ 1251 &rprr_load dtype=16 nreg=0 1252# LD1D (128-bit element) 1253LD_zprr 1010010 1100 rm:5 100 pg:3 rn:5 rd:5 \ 1254 &rprr_load dtype=17 nreg=0 1255 1256# SVE contiguous first-fault load (scalar plus scalar) 1257LDFF1_zprr 1010010 .... ..... 011 ... ..... ..... @rprr_load_dt nreg=0 1258 1259# SVE contiguous load (scalar plus immediate) 1260LD_zpri 1010010 .... 0.... 101 ... ..... ..... @rpri_load_dt nreg=0 1261# LD1W (128-bit element) 1262LD_zpri 1010010 1000 1 imm:s4 001 pg:3 rn:5 rd:5 \ 1263 &rpri_load dtype=16 nreg=0 1264# LD1D (128-bit element) 1265LD_zpri 1010010 1100 1 imm:s4 001 pg:3 rn:5 rd:5 \ 1266 &rpri_load dtype=17 nreg=0 1267 1268# SVE contiguous non-fault load (scalar plus immediate) 1269LDNF1_zpri 1010010 .... 1.... 101 ... ..... ..... @rpri_load_dt nreg=0 1270 1271# SVE contiguous non-temporal load (scalar plus scalar) 1272# LDNT1B, LDNT1H, LDNT1W, LDNT1D 1273# SVE load multiple structures (scalar plus scalar) 1274# LD2B, LD2H, LD2W, LD2D; etc. 1275LD_zprr 1010010 .. nreg:2 ..... 110 ... ..... ..... @rprr_load_msz 1276# LD[234]Q 1277LD_zprr 1010010 01 01 ..... 100 ... ..... ..... \ 1278 @rprr_load dtype=18 nreg=1 1279LD_zprr 1010010 10 01 ..... 100 ... ..... ..... \ 1280 @rprr_load dtype=18 nreg=2 1281LD_zprr 1010010 11 01 ..... 100 ... ..... ..... \ 1282 @rprr_load dtype=18 nreg=3 1283 1284# SVE contiguous non-temporal load (scalar plus immediate) 1285# LDNT1B, LDNT1H, LDNT1W, LDNT1D 1286# SVE load multiple structures (scalar plus immediate) 1287# LD2B, LD2H, LD2W, LD2D; etc. 1288LD_zpri 1010010 .. nreg:2 0.... 111 ... ..... ..... @rpri_load_msz 1289# LD[234]Q 1290LD_zpri 1010010 01 001 .... 111 ... ..... ..... \ 1291 @rpri_load dtype=18 nreg=1 1292LD_zpri 1010010 10 001 .... 111 ... ..... ..... \ 1293 @rpri_load dtype=18 nreg=2 1294LD_zpri 1010010 11 001 .... 111 ... ..... ..... \ 1295 @rpri_load dtype=18 nreg=3 1296 1297# SVE load and broadcast quadword (scalar plus scalar) 1298LD1RQ_zprr 1010010 .. 00 ..... 000 ... ..... ..... \ 1299 @rprr_load_msz nreg=0 1300LD1RO_zprr 1010010 .. 01 ..... 000 ... ..... ..... \ 1301 @rprr_load_msz nreg=0 1302 1303# SVE load and broadcast quadword (scalar plus immediate) 1304# LD1RQB, LD1RQH, LD1RQS, LD1RQD 1305LD1RQ_zpri 1010010 .. 00 0.... 001 ... ..... ..... \ 1306 @rpri_load_msz nreg=0 1307LD1RO_zpri 1010010 .. 01 0.... 001 ... ..... ..... \ 1308 @rpri_load_msz nreg=0 1309 1310# SVE 32-bit gather prefetch (scalar plus 32-bit scaled offsets) 1311PRF_ns 1000010 00 -1 ----- 0-- --- ----- 0 ---- 1312 1313# SVE 32-bit gather prefetch (vector plus immediate) 1314PRF_ns 1000010 -- 00 ----- 111 --- ----- 0 ---- 1315 1316# SVE contiguous prefetch (scalar plus immediate) 1317PRF 1000010 11 1- ----- 0-- --- ----- 0 ---- 1318 1319# SVE contiguous prefetch (scalar plus scalar) 1320PRF_rr 1000010 -- 00 rm:5 110 --- ----- 0 ---- 1321 1322### SVE Memory 64-bit Gather Group 1323 1324# SVE 64-bit gather load (scalar plus 32-bit unpacked unscaled offsets) 1325# SVE 64-bit gather load (scalar plus 32-bit unpacked scaled offsets) 1326LD1_zprz 1100010 00 .0 ..... 0.. ... ..... ..... \ 1327 @rprr_g_load_xs_u esz=3 msz=0 scale=0 1328LD1_zprz 1100010 01 .. ..... 0.. ... ..... ..... \ 1329 @rprr_g_load_xs_u_sc esz=3 msz=1 1330LD1_zprz 1100010 10 .. ..... 0.. ... ..... ..... \ 1331 @rprr_g_load_xs_u_sc esz=3 msz=2 1332LD1_zprz 1100010 11 .. ..... 01. ... ..... ..... \ 1333 @rprr_g_load_xs_sc esz=3 msz=3 u=1 1334 1335# SVE 64-bit gather load (scalar plus 64-bit unscaled offsets) 1336# SVE 64-bit gather load (scalar plus 64-bit scaled offsets) 1337LD1_zprz 1100010 00 10 ..... 1.. ... ..... ..... \ 1338 @rprr_g_load_u esz=3 msz=0 scale=0 1339LD1_zprz 1100010 01 1. ..... 1.. ... ..... ..... \ 1340 @rprr_g_load_u_sc esz=3 msz=1 1341LD1_zprz 1100010 10 1. ..... 1.. ... ..... ..... \ 1342 @rprr_g_load_u_sc esz=3 msz=2 1343LD1_zprz 1100010 11 1. ..... 11. ... ..... ..... \ 1344 @rprr_g_load_sc esz=3 msz=3 u=1 1345 1346# LD1Q. Note that this is subtly different from LD1_zprz because 1347# it is vector + scalar, not scalar + vector. 1348LD1Q 1100 0100 000 rm:5 101 pg:3 rn:5 rd:5 1349 1350# SVE 64-bit gather load (vector plus immediate) 1351LD1_zpiz 1100010 .. 01 ..... 1.. ... ..... ..... \ 1352 @rpri_g_load esz=3 1353 1354# SVE 64-bit gather prefetch (scalar plus 64-bit scaled offsets) 1355PRF_ns 1100010 00 11 ----- 1-- --- ----- 0 ---- 1356 1357# SVE 64-bit gather prefetch (scalar plus unpacked 32-bit scaled offsets) 1358PRF_ns 1100010 00 -1 ----- 0-- --- ----- 0 ---- 1359 1360# SVE 64-bit gather prefetch (vector plus immediate) 1361PRF_ns 1100010 -- 00 ----- 111 --- ----- 0 ---- 1362 1363### SVE Memory Store Group 1364 1365# SVE store predicate register 1366STR_pri 1110010 11 0. ..... 000 ... ..... 0 .... @pd_rn_i9 1367 1368# SVE store vector register 1369STR_zri 1110010 11 0. ..... 010 ... ..... ..... @rd_rn_i9 1370 1371# SVE contiguous store (scalar plus immediate) 1372# ST1B, ST1H, ST1W, ST1D; require msz <= esz 1373ST_zpri 1110010 00 esz:2 0.... 111 ... ..... ..... \ 1374 @rpri_store msz=0 nreg=0 1375ST_zpri 1110010 01 esz:2 0.... 111 ... ..... ..... \ 1376 @rpri_store msz=1 nreg=0 1377ST_zpri 1110010 10 10 0.... 111 ... ..... ..... \ 1378 @rpri_store msz=2 esz=2 nreg=0 1379ST_zpri 1110010 10 11 0.... 111 ... ..... ..... \ 1380 @rpri_store msz=2 esz=3 nreg=0 1381ST_zpri 1110010 11 11 0.... 111 ... ..... ..... \ 1382 @rpri_store msz=3 esz=3 nreg=0 1383ST_zpri 1110010 10 00 0.... 111 ... ..... ..... \ 1384 @rpri_store msz=2 esz=4 nreg=0 1385ST_zpri 1110010 11 10 0.... 111 ... ..... ..... \ 1386 @rpri_store msz=3 esz=4 nreg=0 1387 1388# SVE contiguous store (scalar plus scalar) 1389# ST1B, ST1H, ST1W, ST1D; require msz <= esz 1390# Enumerate msz lest we conflict with STR_zri. 1391ST_zprr 1110010 00 .. ..... 010 ... ..... ..... \ 1392 @rprr_store_esz_n0 msz=0 1393ST_zprr 1110010 01 .. ..... 010 ... ..... ..... \ 1394 @rprr_store_esz_n0 msz=1 1395ST_zprr 1110010 10 10 ..... 010 ... ..... ..... \ 1396 @rprr_store msz=2 esz=2 nreg=0 1397ST_zprr 1110010 10 11 ..... 010 ... ..... ..... \ 1398 @rprr_store msz=2 esz=3 nreg=0 1399ST_zprr 1110010 11 11 ..... 010 ... ..... ..... \ 1400 @rprr_store msz=3 esz=3 nreg=0 1401ST_zprr 1110010 10 00 ..... 010 ... ..... ..... \ 1402 @rprr_store msz=2 esz=4 nreg=0 1403ST_zprr 1110010 11 10 ..... 010 ... ..... ..... \ 1404 @rprr_store msz=3 esz=4 nreg=0 1405 1406# SVE contiguous non-temporal store (scalar plus immediate) (nreg == 0) 1407# SVE store multiple structures (scalar plus immediate) (nreg != 0) 1408ST_zpri 1110010 .. nreg:2 1.... 111 ... ..... ..... \ 1409 @rpri_store msz=%size_23 esz=%size_23 1410# ST[234]Q 1411ST_zpri 11100100 01 00 .... 000 ... ..... ..... \ 1412 @rpri_store msz=4 esz=4 nreg=1 1413ST_zpri 11100100 10 00 .... 000 ... ..... ..... \ 1414 @rpri_store msz=4 esz=4 nreg=2 1415ST_zpri 11100100 11 00 .... 000 ... ..... ..... \ 1416 @rpri_store msz=4 esz=4 nreg=3 1417 1418# SVE contiguous non-temporal store (scalar plus scalar) (nreg == 0) 1419# SVE store multiple structures (scalar plus scalar) (nreg != 0) 1420ST_zprr 1110010 .. nreg:2 ..... 011 ... ..... ..... \ 1421 @rprr_store msz=%size_23 esz=%size_23 1422# ST[234]Q 1423ST_zprr 11100100 01 1 ..... 000 ... ..... ..... \ 1424 @rprr_store msz=4 esz=4 nreg=1 1425ST_zprr 11100100 10 1 ..... 000 ... ..... ..... \ 1426 @rprr_store msz=4 esz=4 nreg=2 1427ST_zprr 11100100 11 1 ..... 000 ... ..... ..... \ 1428 @rprr_store msz=4 esz=4 nreg=3 1429 1430# SVE 32-bit scatter store (scalar plus 32-bit scaled offsets) 1431# Require msz > 0 && msz <= esz. 1432ST1_zprz 1110010 .. 11 ..... 100 ... ..... ..... \ 1433 @rprr_scatter_store xs=0 esz=2 scale=1 1434ST1_zprz 1110010 .. 11 ..... 110 ... ..... ..... \ 1435 @rprr_scatter_store xs=1 esz=2 scale=1 1436 1437# SVE 32-bit scatter store (scalar plus 32-bit unscaled offsets) 1438# Require msz <= esz. 1439ST1_zprz 1110010 .. 10 ..... 100 ... ..... ..... \ 1440 @rprr_scatter_store xs=0 esz=2 scale=0 1441ST1_zprz 1110010 .. 10 ..... 110 ... ..... ..... \ 1442 @rprr_scatter_store xs=1 esz=2 scale=0 1443 1444# SVE 64-bit scatter store (scalar plus 64-bit scaled offset) 1445# Require msz > 0 1446ST1_zprz 1110010 .. 01 ..... 101 ... ..... ..... \ 1447 @rprr_scatter_store xs=2 esz=3 scale=1 1448 1449# SVE 64-bit scatter store (scalar plus 64-bit unscaled offset) 1450ST1_zprz 1110010 .. 00 ..... 101 ... ..... ..... \ 1451 @rprr_scatter_store xs=2 esz=3 scale=0 1452 1453# ST1Q. Note that this is subtly different from ST1_zprz because 1454# it is vector + scalar, not scalar + vector. 1455ST1Q 1110 0100 001 rm:5 001 pg:3 rn:5 rd:5 1456 1457# SVE 64-bit scatter store (vector plus immediate) 1458ST1_zpiz 1110010 .. 10 ..... 101 ... ..... ..... \ 1459 @rpri_scatter_store esz=3 1460 1461# SVE 32-bit scatter store (vector plus immediate) 1462ST1_zpiz 1110010 .. 11 ..... 101 ... ..... ..... \ 1463 @rpri_scatter_store esz=2 1464 1465# SVE 64-bit scatter store (scalar plus unpacked 32-bit scaled offset) 1466# Require msz > 0 1467ST1_zprz 1110010 .. 01 ..... 100 ... ..... ..... \ 1468 @rprr_scatter_store xs=0 esz=3 scale=1 1469ST1_zprz 1110010 .. 01 ..... 110 ... ..... ..... \ 1470 @rprr_scatter_store xs=1 esz=3 scale=1 1471 1472# SVE 64-bit scatter store (scalar plus unpacked 32-bit unscaled offset) 1473ST1_zprz 1110010 .. 00 ..... 100 ... ..... ..... \ 1474 @rprr_scatter_store xs=0 esz=3 scale=0 1475ST1_zprz 1110010 .. 00 ..... 110 ... ..... ..... \ 1476 @rprr_scatter_store xs=1 esz=3 scale=0 1477 1478#### SVE2 Support 1479 1480### SVE2 Integer Multiply - Unpredicated 1481 1482# SVE2 integer multiply vectors (unpredicated) 1483MUL_zzz 00000100 .. 1 ..... 0110 00 ..... ..... @rd_rn_rm 1484SMULH_zzz 00000100 .. 1 ..... 0110 10 ..... ..... @rd_rn_rm 1485UMULH_zzz 00000100 .. 1 ..... 0110 11 ..... ..... @rd_rn_rm 1486PMUL_zzz 00000100 00 1 ..... 0110 01 ..... ..... @rd_rn_rm_e0 1487 1488# SVE2 signed saturating doubling multiply high (unpredicated) 1489SQDMULH_zzz 00000100 .. 1 ..... 0111 00 ..... ..... @rd_rn_rm 1490SQRDMULH_zzz 00000100 .. 1 ..... 0111 01 ..... ..... @rd_rn_rm 1491 1492### SVE2 Integer - Predicated 1493 1494SADALP_zpzz 01000100 .. 000 100 101 ... ..... ..... @rdm_pg_rn 1495UADALP_zpzz 01000100 .. 000 101 101 ... ..... ..... @rdm_pg_rn 1496 1497### SVE2 integer unary operations (predicated) 1498 1499URECPE 01000100 .. 000 000 101 ... ..... ..... @rd_pg_rn 1500URSQRTE 01000100 .. 000 001 101 ... ..... ..... @rd_pg_rn 1501SQABS 01000100 .. 001 000 101 ... ..... ..... @rd_pg_rn 1502SQNEG 01000100 .. 001 001 101 ... ..... ..... @rd_pg_rn 1503 1504### SVE2 saturating/rounding bitwise shift left (predicated) 1505 1506SRSHL 01000100 .. 000 010 100 ... ..... ..... @rdn_pg_rm 1507URSHL 01000100 .. 000 011 100 ... ..... ..... @rdn_pg_rm 1508SRSHL 01000100 .. 000 110 100 ... ..... ..... @rdm_pg_rn # SRSHLR 1509URSHL 01000100 .. 000 111 100 ... ..... ..... @rdm_pg_rn # URSHLR 1510 1511SQSHL 01000100 .. 001 000 100 ... ..... ..... @rdn_pg_rm 1512UQSHL 01000100 .. 001 001 100 ... ..... ..... @rdn_pg_rm 1513SQSHL 01000100 .. 001 100 100 ... ..... ..... @rdm_pg_rn # SQSHLR 1514UQSHL 01000100 .. 001 101 100 ... ..... ..... @rdm_pg_rn # UQSHLR 1515 1516SQRSHL 01000100 .. 001 010 100 ... ..... ..... @rdn_pg_rm 1517UQRSHL 01000100 .. 001 011 100 ... ..... ..... @rdn_pg_rm 1518SQRSHL 01000100 .. 001 110 100 ... ..... ..... @rdm_pg_rn # SQRSHLR 1519UQRSHL 01000100 .. 001 111 100 ... ..... ..... @rdm_pg_rn # UQRSHLR 1520 1521### SVE2 integer halving add/subtract (predicated) 1522 1523SHADD 01000100 .. 010 000 100 ... ..... ..... @rdn_pg_rm 1524UHADD 01000100 .. 010 001 100 ... ..... ..... @rdn_pg_rm 1525SHSUB 01000100 .. 010 010 100 ... ..... ..... @rdn_pg_rm 1526UHSUB 01000100 .. 010 011 100 ... ..... ..... @rdn_pg_rm 1527SRHADD 01000100 .. 010 100 100 ... ..... ..... @rdn_pg_rm 1528URHADD 01000100 .. 010 101 100 ... ..... ..... @rdn_pg_rm 1529SHSUB 01000100 .. 010 110 100 ... ..... ..... @rdm_pg_rn # SHSUBR 1530UHSUB 01000100 .. 010 111 100 ... ..... ..... @rdm_pg_rn # UHSUBR 1531 1532### SVE2 integer pairwise arithmetic 1533 1534ADDP 01000100 .. 010 001 101 ... ..... ..... @rdn_pg_rm 1535SMAXP 01000100 .. 010 100 101 ... ..... ..... @rdn_pg_rm 1536UMAXP 01000100 .. 010 101 101 ... ..... ..... @rdn_pg_rm 1537SMINP 01000100 .. 010 110 101 ... ..... ..... @rdn_pg_rm 1538UMINP 01000100 .. 010 111 101 ... ..... ..... @rdn_pg_rm 1539 1540### SVE2 saturating add/subtract (predicated) 1541 1542SQADD_zpzz 01000100 .. 011 000 100 ... ..... ..... @rdn_pg_rm 1543UQADD_zpzz 01000100 .. 011 001 100 ... ..... ..... @rdn_pg_rm 1544SQSUB_zpzz 01000100 .. 011 010 100 ... ..... ..... @rdn_pg_rm 1545UQSUB_zpzz 01000100 .. 011 011 100 ... ..... ..... @rdn_pg_rm 1546SUQADD 01000100 .. 011 100 100 ... ..... ..... @rdn_pg_rm 1547USQADD 01000100 .. 011 101 100 ... ..... ..... @rdn_pg_rm 1548SQSUB_zpzz 01000100 .. 011 110 100 ... ..... ..... @rdm_pg_rn # SQSUBR 1549UQSUB_zpzz 01000100 .. 011 111 100 ... ..... ..... @rdm_pg_rn # UQSUBR 1550 1551#### SVE2 Widening Integer Arithmetic 1552 1553## SVE2 integer add/subtract long 1554 1555SADDLB 01000101 .. 0 ..... 00 0000 ..... ..... @rd_rn_rm 1556SADDLT 01000101 .. 0 ..... 00 0001 ..... ..... @rd_rn_rm 1557UADDLB 01000101 .. 0 ..... 00 0010 ..... ..... @rd_rn_rm 1558UADDLT 01000101 .. 0 ..... 00 0011 ..... ..... @rd_rn_rm 1559 1560SSUBLB 01000101 .. 0 ..... 00 0100 ..... ..... @rd_rn_rm 1561SSUBLT 01000101 .. 0 ..... 00 0101 ..... ..... @rd_rn_rm 1562USUBLB 01000101 .. 0 ..... 00 0110 ..... ..... @rd_rn_rm 1563USUBLT 01000101 .. 0 ..... 00 0111 ..... ..... @rd_rn_rm 1564 1565SABDLB 01000101 .. 0 ..... 00 1100 ..... ..... @rd_rn_rm 1566SABDLT 01000101 .. 0 ..... 00 1101 ..... ..... @rd_rn_rm 1567UABDLB 01000101 .. 0 ..... 00 1110 ..... ..... @rd_rn_rm 1568UABDLT 01000101 .. 0 ..... 00 1111 ..... ..... @rd_rn_rm 1569 1570## SVE2 integer add/subtract interleaved long 1571 1572SADDLBT 01000101 .. 0 ..... 1000 00 ..... ..... @rd_rn_rm 1573SSUBLBT 01000101 .. 0 ..... 1000 10 ..... ..... @rd_rn_rm 1574SSUBLTB 01000101 .. 0 ..... 1000 11 ..... ..... @rd_rn_rm 1575 1576## SVE2 integer add/subtract wide 1577 1578SADDWB 01000101 .. 0 ..... 010 000 ..... ..... @rd_rn_rm 1579SADDWT 01000101 .. 0 ..... 010 001 ..... ..... @rd_rn_rm 1580UADDWB 01000101 .. 0 ..... 010 010 ..... ..... @rd_rn_rm 1581UADDWT 01000101 .. 0 ..... 010 011 ..... ..... @rd_rn_rm 1582 1583SSUBWB 01000101 .. 0 ..... 010 100 ..... ..... @rd_rn_rm 1584SSUBWT 01000101 .. 0 ..... 010 101 ..... ..... @rd_rn_rm 1585USUBWB 01000101 .. 0 ..... 010 110 ..... ..... @rd_rn_rm 1586USUBWT 01000101 .. 0 ..... 010 111 ..... ..... @rd_rn_rm 1587 1588## SVE2 integer multiply long 1589 1590SQDMULLB_zzz 01000101 .. 0 ..... 011 000 ..... ..... @rd_rn_rm 1591SQDMULLT_zzz 01000101 .. 0 ..... 011 001 ..... ..... @rd_rn_rm 1592PMULLB 01000101 .. 0 ..... 011 010 ..... ..... @rd_rn_rm 1593PMULLT 01000101 .. 0 ..... 011 011 ..... ..... @rd_rn_rm 1594SMULLB_zzz 01000101 .. 0 ..... 011 100 ..... ..... @rd_rn_rm 1595SMULLT_zzz 01000101 .. 0 ..... 011 101 ..... ..... @rd_rn_rm 1596UMULLB_zzz 01000101 .. 0 ..... 011 110 ..... ..... @rd_rn_rm 1597UMULLT_zzz 01000101 .. 0 ..... 011 111 ..... ..... @rd_rn_rm 1598 1599## SVE2 bitwise shift left long 1600 1601# Note bit23 == 0 is handled by esz > 0 in do_sve2_shll_tb. 1602SSHLLB 01000101 .. 0 ..... 1010 00 ..... ..... @rd_rn_tszimm_shl 1603SSHLLT 01000101 .. 0 ..... 1010 01 ..... ..... @rd_rn_tszimm_shl 1604USHLLB 01000101 .. 0 ..... 1010 10 ..... ..... @rd_rn_tszimm_shl 1605USHLLT 01000101 .. 0 ..... 1010 11 ..... ..... @rd_rn_tszimm_shl 1606 1607## SVE2 bitwise exclusive-or interleaved 1608 1609EORBT 01000101 .. 0 ..... 10010 0 ..... ..... @rd_rn_rm 1610EORTB 01000101 .. 0 ..... 10010 1 ..... ..... @rd_rn_rm 1611 1612## SVE integer matrix multiply accumulate 1613 1614SMMLA 01000101 00 0 ..... 10011 0 ..... ..... @rda_rn_rm_ex esz=2 1615USMMLA 01000101 10 0 ..... 10011 0 ..... ..... @rda_rn_rm_ex esz=2 1616UMMLA 01000101 11 0 ..... 10011 0 ..... ..... @rda_rn_rm_ex esz=2 1617 1618## SVE2 bitwise permute 1619 1620BEXT 01000101 .. 0 ..... 1011 00 ..... ..... @rd_rn_rm 1621BDEP 01000101 .. 0 ..... 1011 01 ..... ..... @rd_rn_rm 1622BGRP 01000101 .. 0 ..... 1011 10 ..... ..... @rd_rn_rm 1623 1624#### SVE2 Accumulate 1625 1626## SVE2 complex integer add 1627 1628CADD_rot90 01000101 .. 00000 0 11011 0 ..... ..... @rdn_rm 1629CADD_rot270 01000101 .. 00000 0 11011 1 ..... ..... @rdn_rm 1630SQCADD_rot90 01000101 .. 00000 1 11011 0 ..... ..... @rdn_rm 1631SQCADD_rot270 01000101 .. 00000 1 11011 1 ..... ..... @rdn_rm 1632 1633## SVE2 integer absolute difference and accumulate long 1634 1635SABALB 01000101 .. 0 ..... 1100 00 ..... ..... @rda_rn_rm 1636SABALT 01000101 .. 0 ..... 1100 01 ..... ..... @rda_rn_rm 1637UABALB 01000101 .. 0 ..... 1100 10 ..... ..... @rda_rn_rm 1638UABALT 01000101 .. 0 ..... 1100 11 ..... ..... @rda_rn_rm 1639 1640## SVE2 integer add/subtract long with carry 1641 1642# ADC and SBC decoded via size in helper dispatch. 1643ADCLB 01000101 .. 0 ..... 11010 0 ..... ..... @rda_rn_rm 1644ADCLT 01000101 .. 0 ..... 11010 1 ..... ..... @rda_rn_rm 1645 1646## SVE2 bitwise shift right and accumulate 1647 1648# TODO: Use @rda and %reg_movprfx here. 1649SSRA 01000101 .. 0 ..... 1110 00 ..... ..... @rd_rn_tszimm_shr 1650USRA 01000101 .. 0 ..... 1110 01 ..... ..... @rd_rn_tszimm_shr 1651SRSRA 01000101 .. 0 ..... 1110 10 ..... ..... @rd_rn_tszimm_shr 1652URSRA 01000101 .. 0 ..... 1110 11 ..... ..... @rd_rn_tszimm_shr 1653 1654## SVE2 bitwise shift and insert 1655 1656SRI 01000101 .. 0 ..... 11110 0 ..... ..... @rd_rn_tszimm_shr 1657SLI 01000101 .. 0 ..... 11110 1 ..... ..... @rd_rn_tszimm_shl 1658 1659## SVE2 integer absolute difference and accumulate 1660 1661# TODO: Use @rda and %reg_movprfx here. 1662SABA 01000101 .. 0 ..... 11111 0 ..... ..... @rd_rn_rm 1663UABA 01000101 .. 0 ..... 11111 1 ..... ..... @rd_rn_rm 1664 1665#### SVE2 Narrowing 1666 1667## SVE2 saturating extract narrow 1668# Bits 23, 18-16 are zero, limited in the translator via esz < 3 & imm == 0. 1669 1670{ 1671 SQCVTN_sh 01000101 00 1 10001 010 000 ....0 ..... @rd_rnx2 esz=1 1672 SQXTNB 01000101 .. 1 ..... 010 000 ..... ..... @rd_rn_tszimm_shl 1673} 1674SQXTNT 01000101 .. 1 ..... 010 001 ..... ..... @rd_rn_tszimm_shl 1675{ 1676 UQCVTN_sh 01000101 00 1 10001 010 010 ....0 ..... @rd_rnx2 esz=1 1677 UQXTNB 01000101 .. 1 ..... 010 010 ..... ..... @rd_rn_tszimm_shl 1678} 1679UQXTNT 01000101 .. 1 ..... 010 011 ..... ..... @rd_rn_tszimm_shl 1680{ 1681 SQCVTUN_sh 01000101 00 1 10001 010 100 ....0 ..... @rd_rnx2 esz=1 1682 SQXTUNB 01000101 .. 1 ..... 010 100 ..... ..... @rd_rn_tszimm_shl 1683} 1684SQXTUNT 01000101 .. 1 ..... 010 101 ..... ..... @rd_rn_tszimm_shl 1685 1686## SVE2 bitwise shift right narrow 1687 1688# Bit 23 == 0 is handled by esz > 0 in the translator. 1689SQSHRUNB 01000101 .. 1 ..... 00 0000 ..... ..... @rd_rn_tszimm_shr 1690SQSHRUNT 01000101 .. 1 ..... 00 0001 ..... ..... @rd_rn_tszimm_shr 1691SQRSHRUNB 01000101 .. 1 ..... 00 0010 ..... ..... @rd_rn_tszimm_shr 1692SQRSHRUNT 01000101 .. 1 ..... 00 0011 ..... ..... @rd_rn_tszimm_shr 1693SHRNB 01000101 .. 1 ..... 00 0100 ..... ..... @rd_rn_tszimm_shr 1694SHRNT 01000101 .. 1 ..... 00 0101 ..... ..... @rd_rn_tszimm_shr 1695RSHRNB 01000101 .. 1 ..... 00 0110 ..... ..... @rd_rn_tszimm_shr 1696RSHRNT 01000101 .. 1 ..... 00 0111 ..... ..... @rd_rn_tszimm_shr 1697SQSHRNB 01000101 .. 1 ..... 00 1000 ..... ..... @rd_rn_tszimm_shr 1698SQSHRNT 01000101 .. 1 ..... 00 1001 ..... ..... @rd_rn_tszimm_shr 1699SQRSHRNB 01000101 .. 1 ..... 00 1010 ..... ..... @rd_rn_tszimm_shr 1700SQRSHRNT 01000101 .. 1 ..... 00 1011 ..... ..... @rd_rn_tszimm_shr 1701UQSHRNB 01000101 .. 1 ..... 00 1100 ..... ..... @rd_rn_tszimm_shr 1702UQSHRNT 01000101 .. 1 ..... 00 1101 ..... ..... @rd_rn_tszimm_shr 1703UQRSHRNB 01000101 .. 1 ..... 00 1110 ..... ..... @rd_rn_tszimm_shr 1704UQRSHRNT 01000101 .. 1 ..... 00 1111 ..... ..... @rd_rn_tszimm_shr 1705 1706## SVE2 integer add/subtract narrow high part 1707 1708ADDHNB 01000101 .. 1 ..... 011 000 ..... ..... @rd_rn_rm 1709ADDHNT 01000101 .. 1 ..... 011 001 ..... ..... @rd_rn_rm 1710RADDHNB 01000101 .. 1 ..... 011 010 ..... ..... @rd_rn_rm 1711RADDHNT 01000101 .. 1 ..... 011 011 ..... ..... @rd_rn_rm 1712SUBHNB 01000101 .. 1 ..... 011 100 ..... ..... @rd_rn_rm 1713SUBHNT 01000101 .. 1 ..... 011 101 ..... ..... @rd_rn_rm 1714RSUBHNB 01000101 .. 1 ..... 011 110 ..... ..... @rd_rn_rm 1715RSUBHNT 01000101 .. 1 ..... 011 111 ..... ..... @rd_rn_rm 1716 1717### SVE2 Character Match 1718 1719MATCH 01000101 .. 1 ..... 100 ... ..... 0 .... @pd_pg_rn_rm 1720NMATCH 01000101 .. 1 ..... 100 ... ..... 1 .... @pd_pg_rn_rm 1721 1722### SVE2 Histogram Computation 1723 1724HISTCNT 01000101 .. 1 ..... 110 ... ..... ..... @rd_pg_rn_rm 1725HISTSEG 01000101 .. 1 ..... 101 000 ..... ..... @rd_rn_rm 1726 1727## SVE2 floating-point pairwise operations 1728 1729FADDP 01100100 .. 010 00 0 100 ... ..... ..... @rdn_pg_rm 1730FMAXNMP 01100100 .. 010 10 0 100 ... ..... ..... @rdn_pg_rm 1731FMINNMP 01100100 .. 010 10 1 100 ... ..... ..... @rdn_pg_rm 1732FMAXP 01100100 .. 010 11 0 100 ... ..... ..... @rdn_pg_rm 1733FMINP 01100100 .. 010 11 1 100 ... ..... ..... @rdn_pg_rm 1734 1735#### SVE Integer Multiply-Add (unpredicated) 1736 1737## SVE2 saturating multiply-add long 1738 1739SQDMLALB_zzzw 01000100 .. 0 ..... 0110 00 ..... ..... @rda_rn_rm 1740SQDMLALT_zzzw 01000100 .. 0 ..... 0110 01 ..... ..... @rda_rn_rm 1741SQDMLSLB_zzzw 01000100 .. 0 ..... 0110 10 ..... ..... @rda_rn_rm 1742SQDMLSLT_zzzw 01000100 .. 0 ..... 0110 11 ..... ..... @rda_rn_rm 1743 1744## SVE2 saturating multiply-add interleaved long 1745 1746SQDMLALBT 01000100 .. 0 ..... 00001 0 ..... ..... @rda_rn_rm 1747SQDMLSLBT 01000100 .. 0 ..... 00001 1 ..... ..... @rda_rn_rm 1748 1749## SVE2 saturating multiply-add high 1750 1751SQRDMLAH_zzzz 01000100 .. 0 ..... 01110 0 ..... ..... @rda_rn_rm 1752SQRDMLSH_zzzz 01000100 .. 0 ..... 01110 1 ..... ..... @rda_rn_rm 1753 1754## SVE2 integer multiply-add long 1755 1756SMLALB_zzzw 01000100 .. 0 ..... 010 000 ..... ..... @rda_rn_rm 1757SMLALT_zzzw 01000100 .. 0 ..... 010 001 ..... ..... @rda_rn_rm 1758UMLALB_zzzw 01000100 .. 0 ..... 010 010 ..... ..... @rda_rn_rm 1759UMLALT_zzzw 01000100 .. 0 ..... 010 011 ..... ..... @rda_rn_rm 1760SMLSLB_zzzw 01000100 .. 0 ..... 010 100 ..... ..... @rda_rn_rm 1761SMLSLT_zzzw 01000100 .. 0 ..... 010 101 ..... ..... @rda_rn_rm 1762UMLSLB_zzzw 01000100 .. 0 ..... 010 110 ..... ..... @rda_rn_rm 1763UMLSLT_zzzw 01000100 .. 0 ..... 010 111 ..... ..... @rda_rn_rm 1764 1765## SVE2 complex integer multiply-add 1766 1767CMLA_zzzz 01000100 esz:2 0 rm:5 0010 rot:2 rn:5 rd:5 ra=%reg_movprfx 1768SQRDCMLAH_zzzz 01000100 esz:2 0 rm:5 0011 rot:2 rn:5 rd:5 ra=%reg_movprfx 1769 1770## SVE dot product 1771 1772SDOT_zzzz_2s 01000100 00 0 ..... 110 010 ..... ..... @rda_rn_rm_ex esz=2 1773UDOT_zzzz_2s 01000100 00 0 ..... 110 011 ..... ..... @rda_rn_rm_ex esz=2 1774 1775USDOT_zzzz_4s 01000100 10 0 ..... 011 110 ..... ..... @rda_rn_rm_ex esz=2 1776 1777### SVE2 floating point matrix multiply accumulate 1778BFMMLA 01100100 01 1 ..... 111 001 ..... ..... @rda_rn_rm_ex esz=1 1779FMMLA_s 01100100 10 1 ..... 111 001 ..... ..... @rda_rn_rm_ex esz=2 1780FMMLA_d 01100100 11 1 ..... 111 001 ..... ..... @rda_rn_rm_ex esz=3 1781 1782### SVE2 Memory Gather Load Group 1783 1784# SVE2 64-bit gather non-temporal load (scalar plus 64-bit unscaled offsets) 1785LDNT1_zprz 1100010 msz:2 00 rm:5 1 u:1 0 pg:3 rn:5 rd:5 \ 1786 &rprr_gather_load xs=2 esz=3 scale=0 ff=0 1787 1788# SVE2 32-bit gather non-temporal load (scalar plus 32-bit unscaled offsets) 1789LDNT1_zprz 1000010 msz:2 00 rm:5 10 u:1 pg:3 rn:5 rd:5 \ 1790 &rprr_gather_load xs=0 esz=2 scale=0 ff=0 1791 1792### SVE2 Memory Store Group 1793 1794# SVE2 64-bit scatter non-temporal store (vector plus scalar) 1795STNT1_zprz 1110010 .. 00 ..... 001 ... ..... ..... \ 1796 @rprr_scatter_store xs=2 esz=3 scale=0 1797 1798# SVE2 32-bit scatter non-temporal store (vector plus scalar) 1799STNT1_zprz 1110010 .. 10 ..... 001 ... ..... ..... \ 1800 @rprr_scatter_store xs=0 esz=2 scale=0 1801 1802### SVE2 Crypto Extensions 1803 1804# SVE2 crypto unary operations 1805AESMC 01000101 00 10000011100 0 00000 rd:5 1806AESIMC 01000101 00 10000011100 1 00000 rd:5 1807 1808# SVE2 crypto destructive binary operations 1809AESE 01000101 00 10001 0 11100 0 ..... ..... @rdn_rm_e0 1810AESD 01000101 00 10001 0 11100 1 ..... ..... @rdn_rm_e0 1811SM4E 01000101 00 10001 1 11100 0 ..... ..... @rdn_rm_e0 1812 1813# SVE2 crypto constructive binary operations 1814SM4EKEY 01000101 00 1 ..... 11110 0 ..... ..... @rd_rn_rm_e0 1815RAX1 01000101 00 1 ..... 11110 1 ..... ..... @rd_rn_rm_e0 1816 1817### SVE2 floating-point convert precision odd elements 1818FCVTXNT_ds 01100100 00 0010 10 101 ... ..... ..... @rd_pg_rn_e0 1819FCVTX_ds 01100101 00 0010 10 101 ... ..... ..... @rd_pg_rn_e0 1820FCVTNT_sh 01100100 10 0010 00 101 ... ..... ..... @rd_pg_rn_e0 1821BFCVTNT 01100100 10 0010 10 101 ... ..... ..... @rd_pg_rn_e0 1822FCVTLT_hs 01100100 10 0010 01 101 ... ..... ..... @rd_pg_rn_e0 1823FCVTNT_ds 01100100 11 0010 10 101 ... ..... ..... @rd_pg_rn_e0 1824FCVTLT_sd 01100100 11 0010 11 101 ... ..... ..... @rd_pg_rn_e0 1825 1826### SVE2 floating-point convert to integer 1827FLOGB 01100101 00 011 esz:2 0101 pg:3 rn:5 rd:5 &rpr_esz 1828 1829### SVE2 floating-point multiply-add long (vectors) 1830FMLALB_zzzw 01100100 10 1 ..... 10 0 00 0 ..... ..... @rda_rn_rm_ex esz=2 1831FMLALT_zzzw 01100100 10 1 ..... 10 0 00 1 ..... ..... @rda_rn_rm_ex esz=2 1832FMLSLB_zzzw 01100100 10 1 ..... 10 1 00 0 ..... ..... @rda_rn_rm_ex esz=2 1833FMLSLT_zzzw 01100100 10 1 ..... 10 1 00 1 ..... ..... @rda_rn_rm_ex esz=2 1834 1835BFMLALB_zzzw 01100100 11 1 ..... 10 0 00 0 ..... ..... @rda_rn_rm_ex esz=2 1836BFMLALT_zzzw 01100100 11 1 ..... 10 0 00 1 ..... ..... @rda_rn_rm_ex esz=2 1837BFMLSLB_zzzw 01100100 11 1 ..... 10 1 00 0 ..... ..... @rda_rn_rm_ex esz=2 1838BFMLSLT_zzzw 01100100 11 1 ..... 10 1 00 1 ..... ..... @rda_rn_rm_ex esz=2 1839 1840### SVE2 floating-point dot-product 1841FDOT_zzzz 01100100 00 1 ..... 10 0 00 0 ..... ..... @rda_rn_rm_ex esz=2 1842BFDOT_zzzz 01100100 01 1 ..... 10 0 00 0 ..... ..... @rda_rn_rm_ex esz=2 1843 1844### SVE2 floating-point multiply-add long (indexed) 1845 1846FMLALB_zzxw 01100100 10 1 ..... 0100.0 ..... ..... @rrxr_3a esz=2 1847FMLALT_zzxw 01100100 10 1 ..... 0100.1 ..... ..... @rrxr_3a esz=2 1848FMLSLB_zzxw 01100100 10 1 ..... 0110.0 ..... ..... @rrxr_3a esz=2 1849FMLSLT_zzxw 01100100 10 1 ..... 0110.1 ..... ..... @rrxr_3a esz=2 1850 1851BFMLALB_zzxw 01100100 11 1 ..... 0100.0 ..... ..... @rrxr_3a esz=2 1852BFMLALT_zzxw 01100100 11 1 ..... 0100.1 ..... ..... @rrxr_3a esz=2 1853BFMLSLB_zzxw 01100100 11 1 ..... 0110.0 ..... ..... @rrxr_3a esz=2 1854BFMLSLT_zzxw 01100100 11 1 ..... 0110.1 ..... ..... @rrxr_3a esz=2 1855 1856### SVE2 floating-point dot-product (indexed) 1857 1858FDOT_zzxz 01100100 00 1 ..... 010000 ..... ..... @rrxr_2 esz=2 1859BFDOT_zzxz 01100100 01 1 ..... 010000 ..... ..... @rrxr_2 esz=2 1860 1861### SVE broadcast predicate element 1862 1863&psel esz pd pn pm rv imm 1864%psel_rv 16:2 !function=plus_12 1865%psel_imm_b 22:2 19:2 1866%psel_imm_h 22:2 20:1 1867%psel_imm_s 22:2 1868%psel_imm_d 23:1 1869@psel ........ .. . ... .. .. pn:4 . pm:4 . pd:4 \ 1870 &psel rv=%psel_rv 1871 1872PSEL 00100101 .. 1 ..1 .. 01 .... 0 .... 0 .... \ 1873 @psel esz=0 imm=%psel_imm_b 1874PSEL 00100101 .. 1 .10 .. 01 .... 0 .... 0 .... \ 1875 @psel esz=1 imm=%psel_imm_h 1876PSEL 00100101 .. 1 100 .. 01 .... 0 .... 0 .... \ 1877 @psel esz=2 imm=%psel_imm_s 1878PSEL 00100101 .1 1 000 .. 01 .... 0 .... 0 .... \ 1879 @psel esz=3 imm=%psel_imm_d 1880 1881### SVE clamp 1882 1883SCLAMP 01000100 .. 0 ..... 110000 ..... ..... @rda_rn_rm 1884UCLAMP 01000100 .. 0 ..... 110001 ..... ..... @rda_rn_rm 1885 1886FCLAMP 01100100 .. 1 ..... 001001 ..... ..... @rda_rn_rm 1887 1888### SVE2p1 multi-vec contiguous load 1889 1890&zcrr_ldst rd png rn rm esz nreg 1891&zcri_ldst rd png rn imm esz nreg 1892%png 10:3 !function=plus_8 1893%zd_ax2 1:4 !function=times_2 1894%zd_ax4 2:3 !function=times_4 1895 1896LD1_zcrr 10100000000 rm:5 0 esz:2 ... rn:5 .... - \ 1897 &zcrr_ldst %png rd=%zd_ax2 nreg=2 1898LD1_zcrr 10100000000 rm:5 1 esz:2 ... rn:5 ... 0- \ 1899 &zcrr_ldst %png rd=%zd_ax4 nreg=4 1900 1901ST1_zcrr 10100000001 rm:5 0 esz:2 ... rn:5 .... - \ 1902 &zcrr_ldst %png rd=%zd_ax2 nreg=2 1903ST1_zcrr 10100000001 rm:5 1 esz:2 ... rn:5 ... 0- \ 1904 &zcrr_ldst %png rd=%zd_ax4 nreg=4 1905 1906LD1_zcri 101000000100 imm:s4 0 esz:2 ... rn:5 .... - \ 1907 &zcri_ldst %png rd=%zd_ax2 nreg=2 1908LD1_zcri 101000000100 imm:s4 1 esz:2 ... rn:5 ... 0- \ 1909 &zcri_ldst %png rd=%zd_ax4 nreg=4 1910 1911ST1_zcri 101000000110 imm:s4 0 esz:2 ... rn:5 .... - \ 1912 &zcri_ldst %png rd=%zd_ax2 nreg=2 1913ST1_zcri 101000000110 imm:s4 1 esz:2 ... rn:5 ... 0- \ 1914 &zcri_ldst %png rd=%zd_ax4 nreg=4 1915 1916# Note: N bit and 0 bit (for nreg4) still mashed in rd. 1917# This is handled within gen_ldst_c(). 1918LD1_zcrr_stride 10100001000 rm:5 0 esz:2 ... rn:5 rd:5 \ 1919 &zcrr_ldst %png nreg=2 1920LD1_zcrr_stride 10100001000 rm:5 1 esz:2 ... rn:5 rd:5 \ 1921 &zcrr_ldst %png nreg=4 1922 1923ST1_zcrr_stride 10100001001 rm:5 0 esz:2 ... rn:5 rd:5 \ 1924 &zcrr_ldst %png nreg=2 1925ST1_zcrr_stride 10100001001 rm:5 1 esz:2 ... rn:5 rd:5 \ 1926 &zcrr_ldst %png nreg=4 1927 1928LD1_zcri_stride 101000010100 imm:s4 0 esz:2 ... rn:5 rd:5 \ 1929 &zcri_ldst %png nreg=2 1930LD1_zcri_stride 101000010100 imm:s4 1 esz:2 ... rn:5 rd:5 \ 1931 &zcri_ldst %png nreg=4 1932 1933ST1_zcri_stride 101000010110 imm:s4 0 esz:2 ... rn:5 rd:5 \ 1934 &zcri_ldst %png nreg=2 1935ST1_zcri_stride 101000010110 imm:s4 1 esz:2 ... rn:5 rd:5 \ 1936 &zcri_ldst %png nreg=4 1937