1 /*
2 * STM32L4X5 USART (Universal Synchronous Asynchronous Receiver Transmitter)
3 *
4 * Copyright (c) 2023 Arnaud Minier <arnaud.minier@telecom-paris.fr>
5 * Copyright (c) 2023 Inès Varhol <ines.varhol@telecom-paris.fr>
6 *
7 * SPDX-License-Identifier: GPL-2.0-or-later
8 *
9 * This work is licensed under the terms of the GNU GPL, version 2 or later.
10 * See the COPYING file in the top-level directory.
11 *
12 * The STM32L4X5 USART is heavily inspired by the stm32f2xx_usart
13 * by Alistair Francis.
14 * The reference used is the STMicroElectronics RM0351 Reference manual
15 * for STM32L4x5 and STM32L4x6 advanced Arm ® -based 32-bit MCUs.
16 */
17
18 #include "qemu/osdep.h"
19 #include "qemu/log.h"
20 #include "qemu/module.h"
21 #include "qapi/error.h"
22 #include "chardev/char-fe.h"
23 #include "chardev/char-serial.h"
24 #include "migration/vmstate.h"
25 #include "hw/char/stm32l4x5_usart.h"
26 #include "hw/clock.h"
27 #include "hw/irq.h"
28 #include "hw/qdev-clock.h"
29 #include "hw/qdev-properties.h"
30 #include "hw/qdev-properties-system.h"
31 #include "hw/registerfields.h"
32 #include "trace.h"
33
34
35 REG32(CR1, 0x00)
36 FIELD(CR1, M1, 28, 1) /* Word length (part 2, see M0) */
37 FIELD(CR1, EOBIE, 27, 1) /* End of Block interrupt enable */
38 FIELD(CR1, RTOIE, 26, 1) /* Receiver timeout interrupt enable */
39 FIELD(CR1, DEAT, 21, 5) /* Driver Enable assertion time */
40 FIELD(CR1, DEDT, 16, 5) /* Driver Enable de-assertion time */
41 FIELD(CR1, OVER8, 15, 1) /* Oversampling mode */
42 FIELD(CR1, CMIE, 14, 1) /* Character match interrupt enable */
43 FIELD(CR1, MME, 13, 1) /* Mute mode enable */
44 FIELD(CR1, M0, 12, 1) /* Word length (part 1, see M1) */
45 FIELD(CR1, WAKE, 11, 1) /* Receiver wakeup method */
46 FIELD(CR1, PCE, 10, 1) /* Parity control enable */
47 FIELD(CR1, PS, 9, 1) /* Parity selection */
48 FIELD(CR1, PEIE, 8, 1) /* PE interrupt enable */
49 FIELD(CR1, TXEIE, 7, 1) /* TXE interrupt enable */
50 FIELD(CR1, TCIE, 6, 1) /* Transmission complete interrupt enable */
51 FIELD(CR1, RXNEIE, 5, 1) /* RXNE interrupt enable */
52 FIELD(CR1, IDLEIE, 4, 1) /* IDLE interrupt enable */
53 FIELD(CR1, TE, 3, 1) /* Transmitter enable */
54 FIELD(CR1, RE, 2, 1) /* Receiver enable */
55 FIELD(CR1, UESM, 1, 1) /* USART enable in Stop mode */
56 FIELD(CR1, UE, 0, 1) /* USART enable */
57 REG32(CR2, 0x04)
58 FIELD(CR2, ADD_1, 28, 4) /* ADD[7:4] */
59 FIELD(CR2, ADD_0, 24, 4) /* ADD[3:0] */
60 FIELD(CR2, RTOEN, 23, 1) /* Receiver timeout enable */
61 FIELD(CR2, ABRMOD, 21, 2) /* Auto baud rate mode */
62 FIELD(CR2, ABREN, 20, 1) /* Auto baud rate enable */
63 FIELD(CR2, MSBFIRST, 19, 1) /* Most significant bit first */
64 FIELD(CR2, DATAINV, 18, 1) /* Binary data inversion */
65 FIELD(CR2, TXINV, 17, 1) /* TX pin active level inversion */
66 FIELD(CR2, RXINV, 16, 1) /* RX pin active level inversion */
67 FIELD(CR2, SWAP, 15, 1) /* Swap RX/TX pins */
68 FIELD(CR2, LINEN, 14, 1) /* LIN mode enable */
69 FIELD(CR2, STOP, 12, 2) /* STOP bits */
70 FIELD(CR2, CLKEN, 11, 1) /* Clock enable */
71 FIELD(CR2, CPOL, 10, 1) /* Clock polarity */
72 FIELD(CR2, CPHA, 9, 1) /* Clock phase */
73 FIELD(CR2, LBCL, 8, 1) /* Last bit clock pulse */
74 FIELD(CR2, LBDIE, 6, 1) /* LIN break detection interrupt enable */
75 FIELD(CR2, LBDL, 5, 1) /* LIN break detection length */
76 FIELD(CR2, ADDM7, 4, 1) /* 7-bit / 4-bit Address Detection */
77
78 REG32(CR3, 0x08)
79 /* TCBGTIE only on STM32L496xx/4A6xx devices */
80 FIELD(CR3, UCESM, 23, 1) /* USART Clock Enable in Stop Mode */
81 FIELD(CR3, WUFIE, 22, 1) /* Wakeup from Stop mode interrupt enable */
82 FIELD(CR3, WUS, 20, 2) /* Wakeup from Stop mode interrupt flag selection */
83 FIELD(CR3, SCARCNT, 17, 3) /* Smartcard auto-retry count */
84 FIELD(CR3, DEP, 15, 1) /* Driver enable polarity selection */
85 FIELD(CR3, DEM, 14, 1) /* Driver enable mode */
86 FIELD(CR3, DDRE, 13, 1) /* DMA Disable on Reception Error */
87 FIELD(CR3, OVRDIS, 12, 1) /* Overrun Disable */
88 FIELD(CR3, ONEBIT, 11, 1) /* One sample bit method enable */
89 FIELD(CR3, CTSIE, 10, 1) /* CTS interrupt enable */
90 FIELD(CR3, CTSE, 9, 1) /* CTS enable */
91 FIELD(CR3, RTSE, 8, 1) /* RTS enable */
92 FIELD(CR3, DMAT, 7, 1) /* DMA enable transmitter */
93 FIELD(CR3, DMAR, 6, 1) /* DMA enable receiver */
94 FIELD(CR3, SCEN, 5, 1) /* Smartcard mode enable */
95 FIELD(CR3, NACK, 4, 1) /* Smartcard NACK enable */
96 FIELD(CR3, HDSEL, 3, 1) /* Half-duplex selection */
97 FIELD(CR3, IRLP, 2, 1) /* IrDA low-power */
98 FIELD(CR3, IREN, 1, 1) /* IrDA mode enable */
99 FIELD(CR3, EIE, 0, 1) /* Error interrupt enable */
100 REG32(BRR, 0x0C)
101 FIELD(BRR, BRR, 0, 16)
102 REG32(GTPR, 0x10)
103 FIELD(GTPR, GT, 8, 8) /* Guard time value */
104 FIELD(GTPR, PSC, 0, 8) /* Prescaler value */
105 REG32(RTOR, 0x14)
106 FIELD(RTOR, BLEN, 24, 8) /* Block Length */
107 FIELD(RTOR, RTO, 0, 24) /* Receiver timeout value */
108 REG32(RQR, 0x18)
109 FIELD(RQR, TXFRQ, 4, 1) /* Transmit data flush request */
110 FIELD(RQR, RXFRQ, 3, 1) /* Receive data flush request */
111 FIELD(RQR, MMRQ, 2, 1) /* Mute mode request */
112 FIELD(RQR, SBKRQ, 1, 1) /* Send break request */
113 FIELD(RQR, ABBRRQ, 0, 1) /* Auto baud rate request */
114 REG32(ISR, 0x1C)
115 /* TCBGT only for STM32L475xx/476xx/486xx devices */
116 FIELD(ISR, REACK, 22, 1) /* Receive enable acknowledge flag */
117 FIELD(ISR, TEACK, 21, 1) /* Transmit enable acknowledge flag */
118 FIELD(ISR, WUF, 20, 1) /* Wakeup from Stop mode flag */
119 FIELD(ISR, RWU, 19, 1) /* Receiver wakeup from Mute mode */
120 FIELD(ISR, SBKF, 18, 1) /* Send break flag */
121 FIELD(ISR, CMF, 17, 1) /* Character match flag */
122 FIELD(ISR, BUSY, 16, 1) /* Busy flag */
123 FIELD(ISR, ABRF, 15, 1) /* Auto Baud rate flag */
124 FIELD(ISR, ABRE, 14, 1) /* Auto Baud rate error */
125 FIELD(ISR, EOBF, 12, 1) /* End of block flag */
126 FIELD(ISR, RTOF, 11, 1) /* Receiver timeout */
127 FIELD(ISR, CTS, 10, 1) /* CTS flag */
128 FIELD(ISR, CTSIF, 9, 1) /* CTS interrupt flag */
129 FIELD(ISR, LBDF, 8, 1) /* LIN break detection flag */
130 FIELD(ISR, TXE, 7, 1) /* Transmit data register empty */
131 FIELD(ISR, TC, 6, 1) /* Transmission complete */
132 FIELD(ISR, RXNE, 5, 1) /* Read data register not empty */
133 FIELD(ISR, IDLE, 4, 1) /* Idle line detected */
134 FIELD(ISR, ORE, 3, 1) /* Overrun error */
135 FIELD(ISR, NF, 2, 1) /* START bit Noise detection flag */
136 FIELD(ISR, FE, 1, 1) /* Framing Error */
137 FIELD(ISR, PE, 0, 1) /* Parity Error */
138 REG32(ICR, 0x20)
139 FIELD(ICR, WUCF, 20, 1) /* Wakeup from Stop mode clear flag */
140 FIELD(ICR, CMCF, 17, 1) /* Character match clear flag */
141 FIELD(ICR, EOBCF, 12, 1) /* End of block clear flag */
142 FIELD(ICR, RTOCF, 11, 1) /* Receiver timeout clear flag */
143 FIELD(ICR, CTSCF, 9, 1) /* CTS clear flag */
144 FIELD(ICR, LBDCF, 8, 1) /* LIN break detection clear flag */
145 /* TCBGTCF only on STM32L496xx/4A6xx devices */
146 FIELD(ICR, TCCF, 6, 1) /* Transmission complete clear flag */
147 FIELD(ICR, IDLECF, 4, 1) /* Idle line detected clear flag */
148 FIELD(ICR, ORECF, 3, 1) /* Overrun error clear flag */
149 FIELD(ICR, NCF, 2, 1) /* Noise detected clear flag */
150 FIELD(ICR, FECF, 1, 1) /* Framing error clear flag */
151 FIELD(ICR, PECF, 0, 1) /* Parity error clear flag */
152 REG32(RDR, 0x24)
153 FIELD(RDR, RDR, 0, 9)
154 REG32(TDR, 0x28)
155 FIELD(TDR, TDR, 0, 9)
156
stm32l4x5_update_irq(Stm32l4x5UsartBaseState * s)157 static void stm32l4x5_update_irq(Stm32l4x5UsartBaseState *s)
158 {
159 if (((s->isr & R_ISR_WUF_MASK) && (s->cr3 & R_CR3_WUFIE_MASK)) ||
160 ((s->isr & R_ISR_CMF_MASK) && (s->cr1 & R_CR1_CMIE_MASK)) ||
161 ((s->isr & R_ISR_ABRF_MASK) && (s->cr1 & R_CR1_RXNEIE_MASK)) ||
162 ((s->isr & R_ISR_EOBF_MASK) && (s->cr1 & R_CR1_EOBIE_MASK)) ||
163 ((s->isr & R_ISR_RTOF_MASK) && (s->cr1 & R_CR1_RTOIE_MASK)) ||
164 ((s->isr & R_ISR_CTSIF_MASK) && (s->cr3 & R_CR3_CTSIE_MASK)) ||
165 ((s->isr & R_ISR_LBDF_MASK) && (s->cr2 & R_CR2_LBDIE_MASK)) ||
166 ((s->isr & R_ISR_TXE_MASK) && (s->cr1 & R_CR1_TXEIE_MASK)) ||
167 ((s->isr & R_ISR_TC_MASK) && (s->cr1 & R_CR1_TCIE_MASK)) ||
168 ((s->isr & R_ISR_RXNE_MASK) && (s->cr1 & R_CR1_RXNEIE_MASK)) ||
169 ((s->isr & R_ISR_IDLE_MASK) && (s->cr1 & R_CR1_IDLEIE_MASK)) ||
170 ((s->isr & R_ISR_ORE_MASK) &&
171 ((s->cr1 & R_CR1_RXNEIE_MASK) || (s->cr3 & R_CR3_EIE_MASK))) ||
172 /* TODO: Handle NF ? */
173 ((s->isr & R_ISR_FE_MASK) && (s->cr3 & R_CR3_EIE_MASK)) ||
174 ((s->isr & R_ISR_PE_MASK) && (s->cr1 & R_CR1_PEIE_MASK))) {
175 qemu_irq_raise(s->irq);
176 trace_stm32l4x5_usart_irq_raised(s->isr);
177 } else {
178 qemu_irq_lower(s->irq);
179 trace_stm32l4x5_usart_irq_lowered();
180 }
181 }
182
stm32l4x5_usart_base_can_receive(void * opaque)183 static int stm32l4x5_usart_base_can_receive(void *opaque)
184 {
185 Stm32l4x5UsartBaseState *s = opaque;
186
187 if (!(s->isr & R_ISR_RXNE_MASK)) {
188 return 1;
189 }
190
191 return 0;
192 }
193
stm32l4x5_usart_base_receive(void * opaque,const uint8_t * buf,int size)194 static void stm32l4x5_usart_base_receive(void *opaque, const uint8_t *buf,
195 int size)
196 {
197 Stm32l4x5UsartBaseState *s = opaque;
198
199 if (!((s->cr1 & R_CR1_UE_MASK) && (s->cr1 & R_CR1_RE_MASK))) {
200 trace_stm32l4x5_usart_receiver_not_enabled(
201 FIELD_EX32(s->cr1, CR1, UE), FIELD_EX32(s->cr1, CR1, RE));
202 return;
203 }
204
205 /* Check if overrun detection is enabled and if there is an overrun */
206 if (!(s->cr3 & R_CR3_OVRDIS_MASK) && (s->isr & R_ISR_RXNE_MASK)) {
207 /*
208 * A character has been received while
209 * the previous has not been read = Overrun.
210 */
211 s->isr |= R_ISR_ORE_MASK;
212 trace_stm32l4x5_usart_overrun_detected(s->rdr, *buf);
213 } else {
214 /* No overrun */
215 s->rdr = *buf;
216 s->isr |= R_ISR_RXNE_MASK;
217 trace_stm32l4x5_usart_rx(s->rdr);
218 }
219
220 stm32l4x5_update_irq(s);
221 }
222
223 /*
224 * Try to send tx data, and arrange to be called back later if
225 * we can't (ie the char backend is busy/blocking).
226 */
usart_transmit(void * do_not_use,GIOCondition cond,void * opaque)227 static gboolean usart_transmit(void *do_not_use, GIOCondition cond,
228 void *opaque)
229 {
230 Stm32l4x5UsartBaseState *s = STM32L4X5_USART_BASE(opaque);
231 int ret;
232 /* TODO: Handle 9 bits transmission */
233 uint8_t ch = s->tdr;
234
235 s->watch_tag = 0;
236
237 if (!(s->cr1 & R_CR1_TE_MASK) || (s->isr & R_ISR_TXE_MASK)) {
238 return G_SOURCE_REMOVE;
239 }
240
241 ret = qemu_chr_fe_write(&s->chr, &ch, 1);
242 if (ret <= 0) {
243 s->watch_tag = qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP,
244 usart_transmit, s);
245 if (!s->watch_tag) {
246 /*
247 * Most common reason to be here is "no chardev backend":
248 * just insta-drain the buffer, so the serial output
249 * goes into a void, rather than blocking the guest.
250 */
251 goto buffer_drained;
252 }
253 /* Transmit pending */
254 trace_stm32l4x5_usart_tx_pending();
255 return G_SOURCE_REMOVE;
256 }
257
258 buffer_drained:
259 /* Character successfully sent */
260 trace_stm32l4x5_usart_tx(ch);
261 s->isr |= R_ISR_TC_MASK | R_ISR_TXE_MASK;
262 stm32l4x5_update_irq(s);
263 return G_SOURCE_REMOVE;
264 }
265
usart_cancel_transmit(Stm32l4x5UsartBaseState * s)266 static void usart_cancel_transmit(Stm32l4x5UsartBaseState *s)
267 {
268 if (s->watch_tag) {
269 g_source_remove(s->watch_tag);
270 s->watch_tag = 0;
271 }
272 }
273
stm32l4x5_update_params(Stm32l4x5UsartBaseState * s)274 static void stm32l4x5_update_params(Stm32l4x5UsartBaseState *s)
275 {
276 int speed, parity, data_bits, stop_bits;
277 uint32_t value, usart_div;
278 QEMUSerialSetParams ssp;
279
280 /* Select the parity type */
281 if (s->cr1 & R_CR1_PCE_MASK) {
282 if (s->cr1 & R_CR1_PS_MASK) {
283 parity = 'O';
284 } else {
285 parity = 'E';
286 }
287 } else {
288 parity = 'N';
289 }
290
291 /* Select the number of stop bits */
292 switch (FIELD_EX32(s->cr2, CR2, STOP)) {
293 case 0:
294 stop_bits = 1;
295 break;
296 case 2:
297 stop_bits = 2;
298 break;
299 default:
300 qemu_log_mask(LOG_UNIMP,
301 "UNIMPLEMENTED: fractionnal stop bits; CR2[13:12] = %u",
302 FIELD_EX32(s->cr2, CR2, STOP));
303 return;
304 }
305
306 /* Select the length of the word */
307 switch ((FIELD_EX32(s->cr1, CR1, M1) << 1) | FIELD_EX32(s->cr1, CR1, M0)) {
308 case 0:
309 data_bits = 8;
310 break;
311 case 1:
312 data_bits = 9;
313 break;
314 case 2:
315 data_bits = 7;
316 break;
317 default:
318 qemu_log_mask(LOG_GUEST_ERROR,
319 "UNDEFINED: invalid word length, CR1.M = 0b11");
320 return;
321 }
322
323 /* Select the baud rate */
324 value = FIELD_EX32(s->brr, BRR, BRR);
325 if (value < 16) {
326 qemu_log_mask(LOG_GUEST_ERROR,
327 "UNDEFINED: BRR less than 16: %u", value);
328 return;
329 }
330
331 if (FIELD_EX32(s->cr1, CR1, OVER8) == 0) {
332 /*
333 * Oversampling by 16
334 * BRR = USARTDIV
335 */
336 usart_div = value;
337 } else {
338 /*
339 * Oversampling by 8
340 * - BRR[2:0] = USARTDIV[3:0] shifted 1 bit to the right.
341 * - BRR[3] must be kept cleared.
342 * - BRR[15:4] = USARTDIV[15:4]
343 * - The frequency is multiplied by 2
344 */
345 usart_div = ((value & 0xFFF0) | ((value & 0x0007) << 1)) / 2;
346 }
347
348 speed = clock_get_hz(s->clk) / usart_div;
349
350 ssp.speed = speed;
351 ssp.parity = parity;
352 ssp.data_bits = data_bits;
353 ssp.stop_bits = stop_bits;
354
355 qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
356
357 trace_stm32l4x5_usart_update_params(speed, parity, data_bits, stop_bits);
358 }
359
stm32l4x5_usart_base_reset_hold(Object * obj,ResetType type)360 static void stm32l4x5_usart_base_reset_hold(Object *obj, ResetType type)
361 {
362 Stm32l4x5UsartBaseState *s = STM32L4X5_USART_BASE(obj);
363
364 s->cr1 = 0x00000000;
365 s->cr2 = 0x00000000;
366 s->cr3 = 0x00000000;
367 s->brr = 0x00000000;
368 s->gtpr = 0x00000000;
369 s->rtor = 0x00000000;
370 s->isr = 0x020000C0;
371 s->rdr = 0x00000000;
372 s->tdr = 0x00000000;
373
374 usart_cancel_transmit(s);
375 stm32l4x5_update_irq(s);
376 }
377
usart_update_rqr(Stm32l4x5UsartBaseState * s,uint32_t value)378 static void usart_update_rqr(Stm32l4x5UsartBaseState *s, uint32_t value)
379 {
380 /* TXFRQ */
381 /* Reset RXNE flag */
382 if (value & R_RQR_RXFRQ_MASK) {
383 s->isr &= ~R_ISR_RXNE_MASK;
384 }
385 /* MMRQ */
386 /* SBKRQ */
387 /* ABRRQ */
388 stm32l4x5_update_irq(s);
389 }
390
stm32l4x5_usart_base_read(void * opaque,hwaddr addr,unsigned int size)391 static uint64_t stm32l4x5_usart_base_read(void *opaque, hwaddr addr,
392 unsigned int size)
393 {
394 Stm32l4x5UsartBaseState *s = opaque;
395 uint64_t retvalue = 0;
396
397 switch (addr) {
398 case A_CR1:
399 retvalue = s->cr1;
400 break;
401 case A_CR2:
402 retvalue = s->cr2;
403 break;
404 case A_CR3:
405 retvalue = s->cr3;
406 break;
407 case A_BRR:
408 retvalue = FIELD_EX32(s->brr, BRR, BRR);
409 break;
410 case A_GTPR:
411 retvalue = s->gtpr;
412 break;
413 case A_RTOR:
414 retvalue = s->rtor;
415 break;
416 case A_RQR:
417 /* RQR is a write only register */
418 retvalue = 0x00000000;
419 break;
420 case A_ISR:
421 retvalue = s->isr;
422 break;
423 case A_ICR:
424 /* ICR is a clear register */
425 retvalue = 0x00000000;
426 break;
427 case A_RDR:
428 retvalue = FIELD_EX32(s->rdr, RDR, RDR);
429 /* Reset RXNE flag */
430 s->isr &= ~R_ISR_RXNE_MASK;
431 stm32l4x5_update_irq(s);
432 break;
433 case A_TDR:
434 retvalue = FIELD_EX32(s->tdr, TDR, TDR);
435 break;
436 default:
437 qemu_log_mask(LOG_GUEST_ERROR,
438 "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
439 break;
440 }
441
442 trace_stm32l4x5_usart_read(addr, retvalue);
443
444 return retvalue;
445 }
446
stm32l4x5_usart_base_write(void * opaque,hwaddr addr,uint64_t val64,unsigned int size)447 static void stm32l4x5_usart_base_write(void *opaque, hwaddr addr,
448 uint64_t val64, unsigned int size)
449 {
450 Stm32l4x5UsartBaseState *s = opaque;
451 const uint32_t value = val64;
452
453 trace_stm32l4x5_usart_write(addr, value);
454
455 switch (addr) {
456 case A_CR1:
457 s->cr1 = value;
458 stm32l4x5_update_params(s);
459 stm32l4x5_update_irq(s);
460 return;
461 case A_CR2:
462 s->cr2 = value;
463 stm32l4x5_update_params(s);
464 return;
465 case A_CR3:
466 s->cr3 = value;
467 return;
468 case A_BRR:
469 s->brr = value;
470 stm32l4x5_update_params(s);
471 return;
472 case A_GTPR:
473 s->gtpr = value;
474 return;
475 case A_RTOR:
476 s->rtor = value;
477 return;
478 case A_RQR:
479 usart_update_rqr(s, value);
480 return;
481 case A_ISR:
482 qemu_log_mask(LOG_GUEST_ERROR,
483 "%s: ISR is read only !\n", __func__);
484 return;
485 case A_ICR:
486 /* Clear the status flags */
487 s->isr &= ~value;
488 stm32l4x5_update_irq(s);
489 return;
490 case A_RDR:
491 qemu_log_mask(LOG_GUEST_ERROR,
492 "%s: RDR is read only !\n", __func__);
493 return;
494 case A_TDR:
495 s->tdr = value;
496 s->isr &= ~R_ISR_TXE_MASK;
497 usart_transmit(NULL, G_IO_OUT, s);
498 return;
499 default:
500 qemu_log_mask(LOG_GUEST_ERROR,
501 "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
502 }
503 }
504
505 static const MemoryRegionOps stm32l4x5_usart_base_ops = {
506 .read = stm32l4x5_usart_base_read,
507 .write = stm32l4x5_usart_base_write,
508 .endianness = DEVICE_NATIVE_ENDIAN,
509 .valid = {
510 .max_access_size = 4,
511 .min_access_size = 4,
512 .unaligned = false
513 },
514 .impl = {
515 .max_access_size = 4,
516 .min_access_size = 4,
517 .unaligned = false
518 },
519 };
520
521 static Property stm32l4x5_usart_base_properties[] = {
522 DEFINE_PROP_CHR("chardev", Stm32l4x5UsartBaseState, chr),
523 DEFINE_PROP_END_OF_LIST(),
524 };
525
stm32l4x5_usart_base_init(Object * obj)526 static void stm32l4x5_usart_base_init(Object *obj)
527 {
528 Stm32l4x5UsartBaseState *s = STM32L4X5_USART_BASE(obj);
529
530 sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
531
532 memory_region_init_io(&s->mmio, obj, &stm32l4x5_usart_base_ops, s,
533 TYPE_STM32L4X5_USART_BASE, 0x400);
534 sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
535
536 s->clk = qdev_init_clock_in(DEVICE(s), "clk", NULL, s, 0);
537 }
538
stm32l4x5_usart_base_post_load(void * opaque,int version_id)539 static int stm32l4x5_usart_base_post_load(void *opaque, int version_id)
540 {
541 Stm32l4x5UsartBaseState *s = (Stm32l4x5UsartBaseState *)opaque;
542
543 stm32l4x5_update_params(s);
544 return 0;
545 }
546
547 static const VMStateDescription vmstate_stm32l4x5_usart_base = {
548 .name = TYPE_STM32L4X5_USART_BASE,
549 .version_id = 1,
550 .minimum_version_id = 1,
551 .post_load = stm32l4x5_usart_base_post_load,
552 .fields = (VMStateField[]) {
553 VMSTATE_UINT32(cr1, Stm32l4x5UsartBaseState),
554 VMSTATE_UINT32(cr2, Stm32l4x5UsartBaseState),
555 VMSTATE_UINT32(cr3, Stm32l4x5UsartBaseState),
556 VMSTATE_UINT32(brr, Stm32l4x5UsartBaseState),
557 VMSTATE_UINT32(gtpr, Stm32l4x5UsartBaseState),
558 VMSTATE_UINT32(rtor, Stm32l4x5UsartBaseState),
559 VMSTATE_UINT32(isr, Stm32l4x5UsartBaseState),
560 VMSTATE_UINT32(rdr, Stm32l4x5UsartBaseState),
561 VMSTATE_UINT32(tdr, Stm32l4x5UsartBaseState),
562 VMSTATE_CLOCK(clk, Stm32l4x5UsartBaseState),
563 VMSTATE_END_OF_LIST()
564 }
565 };
566
567
stm32l4x5_usart_base_realize(DeviceState * dev,Error ** errp)568 static void stm32l4x5_usart_base_realize(DeviceState *dev, Error **errp)
569 {
570 ERRP_GUARD();
571 Stm32l4x5UsartBaseState *s = STM32L4X5_USART_BASE(dev);
572 if (!clock_has_source(s->clk)) {
573 error_setg(errp, "USART clock must be wired up by SoC code");
574 return;
575 }
576
577 qemu_chr_fe_set_handlers(&s->chr, stm32l4x5_usart_base_can_receive,
578 stm32l4x5_usart_base_receive, NULL, NULL,
579 s, NULL, true);
580 }
581
stm32l4x5_usart_base_class_init(ObjectClass * klass,void * data)582 static void stm32l4x5_usart_base_class_init(ObjectClass *klass, void *data)
583 {
584 DeviceClass *dc = DEVICE_CLASS(klass);
585 ResettableClass *rc = RESETTABLE_CLASS(klass);
586
587 rc->phases.hold = stm32l4x5_usart_base_reset_hold;
588 device_class_set_props(dc, stm32l4x5_usart_base_properties);
589 dc->realize = stm32l4x5_usart_base_realize;
590 dc->vmsd = &vmstate_stm32l4x5_usart_base;
591 }
592
stm32l4x5_usart_class_init(ObjectClass * oc,void * data)593 static void stm32l4x5_usart_class_init(ObjectClass *oc, void *data)
594 {
595 Stm32l4x5UsartBaseClass *subc = STM32L4X5_USART_BASE_CLASS(oc);
596
597 subc->type = STM32L4x5_USART;
598 }
599
stm32l4x5_uart_class_init(ObjectClass * oc,void * data)600 static void stm32l4x5_uart_class_init(ObjectClass *oc, void *data)
601 {
602 Stm32l4x5UsartBaseClass *subc = STM32L4X5_USART_BASE_CLASS(oc);
603
604 subc->type = STM32L4x5_UART;
605 }
606
stm32l4x5_lpuart_class_init(ObjectClass * oc,void * data)607 static void stm32l4x5_lpuart_class_init(ObjectClass *oc, void *data)
608 {
609 Stm32l4x5UsartBaseClass *subc = STM32L4X5_USART_BASE_CLASS(oc);
610
611 subc->type = STM32L4x5_LPUART;
612 }
613
614 static const TypeInfo stm32l4x5_usart_types[] = {
615 {
616 .name = TYPE_STM32L4X5_USART_BASE,
617 .parent = TYPE_SYS_BUS_DEVICE,
618 .instance_size = sizeof(Stm32l4x5UsartBaseState),
619 .instance_init = stm32l4x5_usart_base_init,
620 .class_size = sizeof(Stm32l4x5UsartBaseClass),
621 .class_init = stm32l4x5_usart_base_class_init,
622 .abstract = true,
623 }, {
624 .name = TYPE_STM32L4X5_USART,
625 .parent = TYPE_STM32L4X5_USART_BASE,
626 .class_init = stm32l4x5_usart_class_init,
627 }, {
628 .name = TYPE_STM32L4X5_UART,
629 .parent = TYPE_STM32L4X5_USART_BASE,
630 .class_init = stm32l4x5_uart_class_init,
631 }, {
632 .name = TYPE_STM32L4X5_LPUART,
633 .parent = TYPE_STM32L4X5_USART_BASE,
634 .class_init = stm32l4x5_lpuart_class_init,
635 }
636 };
637
638 DEFINE_TYPES(stm32l4x5_usart_types)
639