1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * AMD ACP 6.3 Register Documentation
4  *
5  * Copyright 2022 Advanced Micro Devices, Inc.
6  */
7 
8 #ifndef _acp_ip_OFFSET_HEADER
9 #define _acp_ip_OFFSET_HEADER
10 
11 /* Registers from ACP_DMA block */
12 #define ACP_DMA_CNTL_0                                0x0000000
13 #define ACP_DMA_CNTL_1                                0x0000004
14 #define ACP_DMA_CNTL_2                                0x0000008
15 #define ACP_DMA_CNTL_3                                0x000000C
16 #define ACP_DMA_CNTL_4                                0x0000010
17 #define ACP_DMA_CNTL_5                                0x0000014
18 #define ACP_DMA_CNTL_6                                0x0000018
19 #define ACP_DMA_CNTL_7                                0x000001C
20 #define ACP_DMA_DSCR_STRT_IDX_0                       0x0000020
21 #define ACP_DMA_DSCR_STRT_IDX_1                       0x0000024
22 #define ACP_DMA_DSCR_STRT_IDX_2                       0x0000028
23 #define ACP_DMA_DSCR_STRT_IDX_3                       0x000002C
24 #define ACP_DMA_DSCR_STRT_IDX_4                       0x0000030
25 #define ACP_DMA_DSCR_STRT_IDX_5                       0x0000034
26 #define ACP_DMA_DSCR_STRT_IDX_6                       0x0000038
27 #define ACP_DMA_DSCR_STRT_IDX_7                       0x000003C
28 #define ACP_DMA_DSCR_CNT_0                            0x0000040
29 #define ACP_DMA_DSCR_CNT_1                            0x0000044
30 #define ACP_DMA_DSCR_CNT_2                            0x0000048
31 #define ACP_DMA_DSCR_CNT_3                            0x000004C
32 #define ACP_DMA_DSCR_CNT_4                            0x0000050
33 #define ACP_DMA_DSCR_CNT_5                            0x0000054
34 #define ACP_DMA_DSCR_CNT_6                            0x0000058
35 #define ACP_DMA_DSCR_CNT_7                            0x000005C
36 #define ACP_DMA_PRIO_0                                0x0000060
37 #define ACP_DMA_PRIO_1                                0x0000064
38 #define ACP_DMA_PRIO_2                                0x0000068
39 #define ACP_DMA_PRIO_3                                0x000006C
40 #define ACP_DMA_PRIO_4                                0x0000070
41 #define ACP_DMA_PRIO_5                                0x0000074
42 #define ACP_DMA_PRIO_6                                0x0000078
43 #define ACP_DMA_PRIO_7                                0x000007C
44 #define ACP_DMA_CUR_DSCR_0                            0x0000080
45 #define ACP_DMA_CUR_DSCR_1                            0x0000084
46 #define ACP_DMA_CUR_DSCR_2                            0x0000088
47 #define ACP_DMA_CUR_DSCR_3                            0x000008C
48 #define ACP_DMA_CUR_DSCR_4                            0x0000090
49 #define ACP_DMA_CUR_DSCR_5                            0x0000094
50 #define ACP_DMA_CUR_DSCR_6                            0x0000098
51 #define ACP_DMA_CUR_DSCR_7                            0x000009C
52 #define ACP_DMA_CUR_TRANS_CNT_0                       0x00000A0
53 #define ACP_DMA_CUR_TRANS_CNT_1                       0x00000A4
54 #define ACP_DMA_CUR_TRANS_CNT_2                       0x00000A8
55 #define ACP_DMA_CUR_TRANS_CNT_3                       0x00000AC
56 #define ACP_DMA_CUR_TRANS_CNT_4                       0x00000B0
57 #define ACP_DMA_CUR_TRANS_CNT_5                       0x00000B4
58 #define ACP_DMA_CUR_TRANS_CNT_6                       0x00000B8
59 #define ACP_DMA_CUR_TRANS_CNT_7                       0x00000BC
60 #define ACP_DMA_ERR_STS_0                             0x00000C0
61 #define ACP_DMA_ERR_STS_1                             0x00000C4
62 #define ACP_DMA_ERR_STS_2                             0x00000C8
63 #define ACP_DMA_ERR_STS_3                             0x00000CC
64 #define ACP_DMA_ERR_STS_4                             0x00000D0
65 #define ACP_DMA_ERR_STS_5                             0x00000D4
66 #define ACP_DMA_ERR_STS_6                             0x00000D8
67 #define ACP_DMA_ERR_STS_7                             0x00000DC
68 #define ACP_DMA_DESC_BASE_ADDR                        0x00000E0
69 #define ACP_DMA_DESC_MAX_NUM_DSCR                     0x00000E4
70 #define ACP_DMA_CH_STS                                0x00000E8
71 #define ACP_DMA_CH_GROUP                              0x00000EC
72 #define ACP_DMA_CH_RST_STS                            0x00000F0
73 
74 /* Registers from ACP_AXI2AXIATU block */
75 #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_1                0x0000C00
76 #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_1                0x0000C04
77 #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_2                0x0000C08
78 #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_2                0x0000C0C
79 #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_3                0x0000C10
80 #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_3                0x0000C14
81 #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_4                0x0000C18
82 #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_4                0x0000C1C
83 #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_5                0x0000C20
84 #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_5                0x0000C24
85 #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_6                0x0000C28
86 #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_6                0x0000C2C
87 #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_7                0x0000C30
88 #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_7                0x0000C34
89 #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_8                0x0000C38
90 #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_8                0x0000C3C
91 #define ACPAXI2AXI_ATU_CTRL                           0x0000C40
92 #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_9                0x0000C44
93 #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_9                0x0000C48
94 #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_10               0x0000C4C
95 #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_10               0x0000C50
96 #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_11               0x0000C54
97 #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_11               0x0000C58
98 #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_12               0x0000C5C
99 #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_12               0x0000C60
100 #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_13               0x0000C64
101 #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_13               0x0000C68
102 #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_14               0x0000C6C
103 #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_14               0x0000C70
104 #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_15               0x0000C74
105 #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_15               0x0000C78
106 #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_16               0x0000C7C
107 #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_16               0x0000C80
108 
109 /* Registers from ACP_CLKRST block */
110 #define ACP_SOFT_RESET                                0x0001000
111 #define ACP_CONTROL                                   0x0001004
112 #define ACP_STATUS                                    0x0001008
113 #define ACP_DYNAMIC_CG_MASTER_CONTROL                 0x0001010
114 #define ACP_ZSC_DSP_CTRL                              0x0001014
115 #define ACP_ZSC_STS                                   0x0001018
116 #define ACP_PGFSM_CONTROL                             0x0001024
117 #define ACP_PGFSM_STATUS                              0x0001028
118 #define ACP_CLKMUX_SEL                                0x000102C
119 
120 /* Registers from ACP_AON block */
121 #define ACP_PME_EN                                    0x0001400
122 #define ACP_DEVICE_STATE                              0x0001404
123 #define AZ_DEVICE_STATE                               0x0001408
124 #define ACP_PIN_CONFIG                                0x0001440
125 #define ACP_PAD_PULLUP_CTRL                           0x0001444
126 #define ACP_PAD_PULLDOWN_CTRL                         0x0001448
127 #define ACP_PAD_DRIVE_STRENGTH_CTRL                   0x000144C
128 #define ACP_PAD_SCHMEN_CTRL                           0x0001450
129 #define ACP_SW0_PAD_KEEPER_EN                         0x0001454
130 #define ACP_SW0_WAKE_EN                               0x0001458
131 #define ACP_I2S_WAKE_EN                               0x000145C
132 #define ACP_SW1_WAKE_EN                               0x0001460
133 
134 #define ACP_SW0_I2S_ERROR_REASON                      0x00018B4
135 #define ACP_SW0_POS_TRACK_AUDIO0_TX_CTRL              0x00018B8
136 #define ACP_SW0_AUDIO0_TX_DMA_POS                     0x00018BC
137 #define ACP_SW0_POS_TRACK_AUDIO1_TX_CTRL              0x00018C0
138 #define ACP_SW0_AUDIO1_TX_DMA_POS                     0x00018C4
139 #define ACP_SW0_POS_TRACK_AUDIO2_TX_CTRL              0x00018C8
140 #define ACP_SW0_AUDIO2_TX_DMA_POS                     0x00018CC
141 #define ACP_SW0_POS_TRACK_AUDIO0_RX_CTRL              0x00018D0
142 #define ACP_SW0_AUDIO0_DMA_POS                        0x00018D4
143 #define ACP_SW0_POS_TRACK_AUDIO1_RX_CTRL              0x00018D8
144 #define ACP_SW0_AUDIO1_RX_DMA_POS                     0x00018DC
145 #define ACP_SW0_POS_TRACK_AUDIO2_RX_CTRL              0x00018E0
146 #define ACP_SW0_AUDIO2_RX_DMA_POS                     0x00018E4
147 #define ACP_ERROR_INTR_MASK1                          0X0001974
148 #define ACP_ERROR_INTR_MASK2                          0X0001978
149 #define ACP_ERROR_INTR_MASK3                          0X000197C
150 
151 /* Registers from ACP_P1_MISC block */
152 #define ACP_EXTERNAL_INTR_ENB                         0x0001A00
153 #define ACP_EXTERNAL_INTR_CNTL                        0x0001A04
154 #define ACP_EXTERNAL_INTR_CNTL1                       0x0001A08
155 #define ACP_EXTERNAL_INTR_STAT                        0x0001A0C
156 #define ACP_EXTERNAL_INTR_STAT1                       0x0001A10
157 #define ACP_ERROR_STATUS                              0x0001A4C
158 #define ACP_SW1_I2S_ERROR_REASON                      0x0001A50
159 #define ACP_SW1_POS_TRACK_AUDIO0_TX_CTRL              0x0001A6C
160 #define ACP_SW1_AUDIO0_TX_DMA_POS                     0x0001A70
161 #define ACP_SW1_POS_TRACK_AUDIO0_RX_CTRL              0x0001A74
162 #define ACP_SW1_AUDIO0_RX_DMA_POS                     0x0001A78
163 #define ACP_P1_DMIC_I2S_GPIO_INTR_CTRL                0x0001A7C
164 #define ACP_P1_DMIC_I2S_GPIO_INTR_STATUS              0x0001A80
165 #define ACP_SCRATCH_REG_BASE_ADDR                     0x0001A84
166 #define ACP_SW1_POS_TRACK_AUDIO1_TX_CTRL              0x0001A88
167 #define ACP_SW1_AUDIO1_TX_DMA_POS                     0x0001A8C
168 #define ACP_SW1_POS_TRACK_AUDIO2_TX_CTRL              0x0001A90
169 #define ACP_SW1_AUDIO2_TX_DMA_POS                     0x0001A94
170 #define ACP_SW1_POS_TRACK_AUDIO1_RX_CTRL              0x0001A98
171 #define ACP_SW1_AUDIO1_RX_DMA_POS                     0x0001A9C
172 #define ACP_SW1_POS_TRACK_AUDIO2_RX_CTRL              0x0001AA0
173 #define ACP_SW1_AUDIO2_RX_DMA_POS                     0x0001AA4
174 #define ACP_ERROR_INTR_MASK4                          0X0001AEC
175 #define ACP_ERROR_INTR_MASK5                          0X0001AF0
176 
177 /* Registers from ACP_AUDIO_BUFFERS block */
178 #define ACP_AUDIO0_RX_RINGBUFADDR                        0x0002000
179 #define ACP_AUDIO0_RX_RINGBUFSIZE                        0x0002004
180 #define ACP_AUDIO0_RX_LINKPOSITIONCNTR                   0x0002008
181 #define ACP_AUDIO0_RX_FIFOADDR                           0x000200C
182 #define ACP_AUDIO0_RX_FIFOSIZE                           0x0002010
183 #define ACP_AUDIO0_RX_DMA_SIZE                           0x0002014
184 #define ACP_AUDIO0_RX_LINEARPOSITIONCNTR_HIGH            0x0002018
185 #define ACP_AUDIO0_RX_LINEARPOSITIONCNTR_LOW             0x000201C
186 #define ACP_AUDIO0_RX_INTR_WATERMARK_SIZE                0x0002020
187 #define ACP_AUDIO0_TX_RINGBUFADDR                        0x0002024
188 #define ACP_AUDIO0_TX_RINGBUFSIZE                        0x0002028
189 #define ACP_AUDIO0_TX_LINKPOSITIONCNTR                   0x000202C
190 #define ACP_AUDIO0_TX_FIFOADDR                           0x0002030
191 #define ACP_AUDIO0_TX_FIFOSIZE                           0x0002034
192 #define ACP_AUDIO0_TX_DMA_SIZE                           0x0002038
193 #define ACP_AUDIO0_TX_LINEARPOSITIONCNTR_HIGH            0x000203C
194 #define ACP_AUDIO0_TX_LINEARPOSITIONCNTR_LOW             0x0002040
195 #define ACP_AUDIO0_TX_INTR_WATERMARK_SIZE                0x0002044
196 #define ACP_AUDIO1_RX_RINGBUFADDR                        0x0002048
197 #define ACP_AUDIO1_RX_RINGBUFSIZE                        0x000204C
198 #define ACP_AUDIO1_RX_LINKPOSITIONCNTR                   0x0002050
199 #define ACP_AUDIO1_RX_FIFOADDR                           0x0002054
200 #define ACP_AUDIO1_RX_FIFOSIZE                           0x0002058
201 #define ACP_AUDIO1_RX_DMA_SIZE                           0x000205C
202 #define ACP_AUDIO1_RX_LINEARPOSITIONCNTR_HIGH            0x0002060
203 #define ACP_AUDIO1_RX_LINEARPOSITIONCNTR_LOW             0x0002064
204 #define ACP_AUDIO1_RX_INTR_WATERMARK_SIZE                0x0002068
205 #define ACP_AUDIO1_TX_RINGBUFADDR                        0x000206C
206 #define ACP_AUDIO1_TX_RINGBUFSIZE                        0x0002070
207 #define ACP_AUDIO1_TX_LINKPOSITIONCNTR                   0x0002074
208 #define ACP_AUDIO1_TX_FIFOADDR                           0x0002078
209 #define ACP_AUDIO1_TX_FIFOSIZE                           0x000207C
210 #define ACP_AUDIO1_TX_DMA_SIZE                           0x0002080
211 #define ACP_AUDIO1_TX_LINEARPOSITIONCNTR_HIGH            0x0002084
212 #define ACP_AUDIO1_TX_LINEARPOSITIONCNTR_LOW             0x0002088
213 #define ACP_AUDIO1_TX_INTR_WATERMARK_SIZE                0x000208C
214 #define ACP_AUDIO2_RX_RINGBUFADDR                        0x0002090
215 #define ACP_AUDIO2_RX_RINGBUFSIZE                        0x0002094
216 #define ACP_AUDIO2_RX_LINKPOSITIONCNTR                   0x0002098
217 #define ACP_AUDIO2_RX_FIFOADDR                           0x000209C
218 #define ACP_AUDIO2_RX_FIFOSIZE                           0x00020A0
219 #define ACP_AUDIO2_RX_DMA_SIZE                           0x00020A4
220 #define ACP_AUDIO2_RX_LINEARPOSITIONCNTR_HIGH            0x00020A8
221 #define ACP_AUDIO2_RX_LINEARPOSITIONCNTR_LOW             0x00020AC
222 #define ACP_AUDIO2_RX_INTR_WATERMARK_SIZE                0x00020B0
223 #define ACP_AUDIO2_TX_RINGBUFADDR                        0x00020B4
224 #define ACP_AUDIO2_TX_RINGBUFSIZE                        0x00020B8
225 #define ACP_AUDIO2_TX_LINKPOSITIONCNTR                   0x00020BC
226 #define ACP_AUDIO2_TX_FIFOADDR                           0x00020C0
227 #define ACP_AUDIO2_TX_FIFOSIZE                           0x00020C4
228 #define ACP_AUDIO2_TX_DMA_SIZE                           0x00020C8
229 #define ACP_AUDIO2_TX_LINEARPOSITIONCNTR_HIGH            0x00020CC
230 #define ACP_AUDIO2_TX_LINEARPOSITIONCNTR_LOW             0x00020D0
231 #define ACP_AUDIO2_TX_INTR_WATERMARK_SIZE                0x00020D4
232 
233 /* Registers from ACP_I2S_TDM block */
234 #define ACP_I2STDM_IER                                0x0002400
235 #define ACP_I2STDM_IRER                               0x0002404
236 #define ACP_I2STDM_RXFRMT                             0x0002408
237 #define ACP_I2STDM_ITER                               0x000240C
238 #define ACP_I2STDM_TXFRMT                             0x0002410
239 #define ACP_I2STDM0_MSTRCLKGEN                        0x0002414
240 #define ACP_I2STDM1_MSTRCLKGEN                        0x0002418
241 #define ACP_I2STDM2_MSTRCLKGEN                        0x000241C
242 #define ACP_I2STDM_REFCLKGEN                          0x0002420
243 
244 /* Registers from ACP_BT_TDM block */
245 #define ACP_BTTDM_IER                                 0x0002800
246 #define ACP_BTTDM_IRER                                0x0002804
247 #define ACP_BTTDM_RXFRMT                              0x0002808
248 #define ACP_BTTDM_ITER                                0x000280C
249 #define ACP_BTTDM_TXFRMT                              0x0002810
250 #define ACP_HSTDM_IER                                 0x0002814
251 #define ACP_HSTDM_IRER                                0x0002818
252 #define ACP_HSTDM_RXFRMT                              0x000281C
253 #define ACP_HSTDM_ITER                                0x0002820
254 #define ACP_HSTDM_TXFRMT                              0x0002824
255 
256 /* Registers from ACP_WOV block */
257 #define ACP_WOV_PDM_ENABLE                            0x0002C04
258 #define ACP_WOV_PDM_DMA_ENABLE                        0x0002C08
259 #define ACP_WOV_RX_RINGBUFADDR                        0x0002C0C
260 #define ACP_WOV_RX_RINGBUFSIZE                        0x0002C10
261 #define ACP_WOV_RX_LINKPOSITIONCNTR                   0x0002C14
262 #define ACP_WOV_RX_LINEARPOSITIONCNTR_HIGH            0x0002C18
263 #define ACP_WOV_RX_LINEARPOSITIONCNTR_LOW             0x0002C1C
264 #define ACP_WOV_RX_INTR_WATERMARK_SIZE                0x0002C20
265 #define ACP_WOV_PDM_FIFO_FLUSH                        0x0002C24
266 #define ACP_WOV_PDM_NO_OF_CHANNELS                    0x0002C28
267 #define ACP_WOV_PDM_DECIMATION_FACTOR                 0x0002C2C
268 #define ACP_WOV_PDM_VAD_CTRL                          0x0002C30
269 #define ACP_WOV_WAKE                                  0x0002C54
270 #define ACP_WOV_BUFFER_STATUS                         0x0002C58
271 #define ACP_WOV_MISC_CTRL                             0x0002C5C
272 #define ACP_WOV_CLK_CTRL                              0x0002C60
273 #define ACP_PDM_VAD_DYNAMIC_CLK_GATING_EN             0x0002C64
274 #define ACP_WOV_ERROR_STATUS_REGISTER                 0x0002C68
275 #define ACP_PDM_CLKDIV                                0x0002C6C
276 
277 /* Registers from ACP_SW0_SWCLK block */
278 #define ACP_SW0_EN                                     0x0003000
279 #define ACP_SW0_EN_STATUS                              0x0003004
280 #define ACP_SW0_FRAMESIZE                              0x0003008
281 #define ACP_SW0_SSP_COUNTER                            0x000300C
282 #define ACP_SW0_AUDIO0_TX_EN                           0x0003010
283 #define ACP_SW0_AUDIO0_TX_EN_STATUS                    0x0003014
284 #define ACP_SW0_AUDIO0_TX_FRAME_FORMAT                 0x0003018
285 #define ACP_SW0_AUDIO0_TX_SAMPLEINTERVAL               0x000301C
286 #define ACP_SW0_AUDIO0_TX_HCTRL_DP0                    0x0003020
287 #define ACP_SW0_AUDIO0_TX_HCTRL_DP1                    0x0003024
288 #define ACP_SW0_AUDIO0_TX_HCTRL_DP2                    0x0003028
289 #define ACP_SW0_AUDIO0_TX_HCTRL_DP3                    0x000302C
290 #define ACP_SW0_AUDIO0_TX_OFFSET_DP0                   0x0003030
291 #define ACP_SW0_AUDIO0_TX_OFFSET_DP1                   0x0003034
292 #define ACP_SW0_AUDIO0_TX_OFFSET_DP2                   0x0003038
293 #define ACP_SW0_AUDIO0_TX_OFFSET_DP3                   0x000303C
294 #define ACP_SW0_AUDIO0_TX_CHANNEL_ENABLE_DP0           0x0003040
295 #define ACP_SW0_AUDIO0_TX_CHANNEL_ENABLE_DP1           0x0003044
296 #define ACP_SW0_AUDIO0_TX_CHANNEL_ENABLE_DP2           0x0003048
297 #define ACP_SW0_AUDIO0_TX_CHANNEL_ENABLE_DP3           0x000304C
298 #define ACP_SW0_AUDIO1_TX_EN                           0x0003050
299 #define ACP_SW0_AUDIO1_TX_EN_STATUS                    0x0003054
300 #define ACP_SW0_AUDIO1_TX_FRAME_FORMAT                 0x0003058
301 #define ACP_SW0_AUDIO1_TX_SAMPLEINTERVAL               0x000305C
302 #define ACP_SW0_AUDIO1_TX_HCTRL                        0x0003060
303 #define ACP_SW0_AUDIO1_TX_OFFSET                       0x0003064
304 #define ACP_SW0_AUDIO1_TX_CHANNEL_ENABLE_DP0           0x0003068
305 #define ACP_SW0_AUDIO2_TX_EN                           0x000306C
306 #define ACP_SW0_AUDIO2_TX_EN_STATUS                    0x0003070
307 #define ACP_SW0_AUDIO2_TX_FRAME_FORMAT                 0x0003074
308 #define ACP_SW0_AUDIO2_TX_SAMPLEINTERVAL               0x0003078
309 #define ACP_SW0_AUDIO2_TX_HCTRL                        0x000307C
310 #define ACP_SW0_AUDIO2_TX_OFFSET                       0x0003080
311 #define ACP_SW0_AUDIO2_TX_CHANNEL_ENABLE_DP0           0x0003084
312 #define ACP_SW0_AUDIO0_RX_EN                           0x0003088
313 #define ACP_SW0_AUDIO0_RX_EN_STATUS                    0x000308C
314 #define ACP_SW0_AUDIO0_RX_FRAME_FORMAT                 0x0003090
315 #define ACP_SW0_AUDIO0_RX_SAMPLEINTERVAL               0x0003094
316 #define ACP_SW0_AUDIO0_RX_HCTRL_DP0                    0x0003098
317 #define ACP_SW0_AUDIO0_RX_HCTRL_DP1                    0x000309C
318 #define ACP_SW0_AUDIO0_RX_HCTRL_DP2                    0x0003100
319 #define ACP_SW0_AUDIO0_RX_HCTRL_DP3                    0x0003104
320 #define ACP_SW0_AUDIO0_RX_OFFSET_DP0                   0x0003108
321 #define ACP_SW0_AUDIO0_RX_OFFSET_DP1                   0x000310C
322 #define ACP_SW0_AUDIO0_RX_OFFSET_DP2                   0x0003110
323 #define ACP_SW0_AUDIO0_RX_OFFSET_DP3                   0x0003114
324 #define ACP_SW0_AUDIO0_RX_CHANNEL_ENABLE_DP0           0x0003118
325 #define ACP_SW0_AUDIO0_RX_CHANNEL_ENABLE_DP1           0x000311C
326 #define ACP_SW0_AUDIO0_RX_CHANNEL_ENABLE_DP2           0x0003120
327 #define ACP_SW0_AUDIO0_RX_CHANNEL_ENABLE_DP3           0x0003124
328 #define ACP_SW0_AUDIO1_RX_EN                           0x0003128
329 #define ACP_SW0_AUDIO1_RX_EN_STATUS                    0x000312C
330 #define ACP_SW0_AUDIO1_RX_FRAME_FORMAT                 0x0003130
331 #define ACP_SW0_AUDIO1_RX_SAMPLEINTERVAL               0x0003134
332 #define ACP_SW0_AUDIO1_RX_HCTRL                        0x0003138
333 #define ACP_SW0_AUDIO1_RX_OFFSET                       0x000313C
334 #define ACP_SW0_AUDIO1_RX_CHANNEL_ENABLE_DP0           0x0003140
335 #define ACP_SW0_AUDIO2_RX_EN                           0x0003144
336 #define ACP_SW0_AUDIO2_RX_EN_STATUS                    0x0003148
337 #define ACP_SW0_AUDIO2_RX_FRAME_FORMAT                 0x000314C
338 #define ACP_SW0_AUDIO2_RX_SAMPLEINTERVAL               0x0003150
339 #define ACP_SW0_AUDIO2_RX_HCTRL                        0x0003154
340 #define ACP_SW0_AUDIO2_RX_OFFSET                       0x0003158
341 #define ACP_SW0_AUDIO2_RX_CHANNEL_ENABLE_DP0           0x000315C
342 #define ACP_SW0_BPT_PORT_EN                            0x0003160
343 #define ACP_SW0_BPT_PORT_EN_STATUS                     0x0003164
344 #define ACP_SW0_BPT_PORT_FRAME_FORMAT                  0x0003168
345 #define ACP_SW0_BPT_PORT_SAMPLEINTERVAL                0x000316C
346 #define ACP_SW0_BPT_PORT_HCTRL                         0x0003170
347 #define ACP_SW0_BPT_PORT_OFFSET                        0x0003174
348 #define ACP_SW0_BPT_PORT_CHANNEL_ENABLE                0x0003178
349 #define ACP_SW0_BPT_PORT_FIRST_BYTE_ADDR               0x000317C
350 #define ACP_SW0_CLK_RESUME_CTRL                        0x0003180
351 #define ACP_SW0_CLK_RESUME_DELAY_CNTR                  0x0003184
352 #define ACP_SW0_BUS_RESET_CTRL                         0x0003188
353 #define ACP_SW0_PRBS_ERR_STATUS                        0x000318C
354 #define ACP_SW0_IMM_CMD_UPPER_WORD                     0x0003230
355 #define ACP_SW0_IMM_CMD_LOWER_QWORD                    0x0003234
356 #define ACP_SW0_IMM_RESP_UPPER_WORD                    0x0003238
357 #define ACP_SW0_IMM_RESP_LOWER_QWORD                   0x000323C
358 #define ACP_SW0_IMM_CMD_STS                            0x0003240
359 #define ACP_SW0_BRA_BASE_ADDRESS                       0x0003244
360 #define ACP_SW0_BRA_TRANSFER_SIZE                      0x0003248
361 #define ACP_SW0_BRA_DMA_BUSY                           0x000324C
362 #define ACP_SW0_BRA_RESP                               0x0003250
363 #define ACP_SW0_BRA_RESP_FRAME_ADDR                    0x0003254
364 #define ACP_SW0_BRA_CURRENT_TRANSFER_SIZE              0x0003258
365 #define ACP_SW0_STATECHANGE_STATUS_0TO7                0x000325C
366 #define ACP_SW0_STATECHANGE_STATUS_8TO11               0x0003260
367 #define ACP_SW0_STATECHANGE_STATUS_MASK_0TO7           0x0003264
368 #define ACP_SW0_STATECHANGE_STATUS_MASK_8TO11          0x0003268
369 #define ACP_SW0_CLK_FREQUENCY_CTRL                     0x000326C
370 #define ACP_SW0_ERROR_INTR_MASK                        0x0003270
371 #define ACP_SW0_PHY_TEST_MODE_DATA_OFF                 0x0003274
372 
373 /* Registers from ACP_P1_AUDIO_BUFFERS block */
374 #define ACP_P1_AUDIO0_RX_RINGBUFADDR                     0x0003A00
375 #define ACP_P1_AUDIO0_RX_RINGBUFSIZE                     0x0003A04
376 #define ACP_P1_AUDIO0_RX_LINKPOSITIONCNTR                0x0003A08
377 #define ACP_P1_AUDIO0_RX_FIFOADDR                        0x0003A0C
378 #define ACP_P1_AUDIO0_RX_FIFOSIZE                        0x0003A10
379 #define ACP_P1_AUDIO0_RX_DMA_SIZE                        0x0003A14
380 #define ACP_P1_AUDIO0_RX_LINEARPOSITIONCNTR_HIGH         0x0003A18
381 #define ACP_P1_AUDIO0_RX_LINEARPOSITIONCNTR_LOW          0x0003A1C
382 #define ACP_P1_AUDIO0_RX_INTR_WATERMARK_SIZE             0x0003A20
383 #define ACP_P1_AUDIO0_TX_RINGBUFADDR                     0x0003A24
384 #define ACP_P1_AUDIO0_TX_RINGBUFSIZE                     0x0003A28
385 #define ACP_P1_AUDIO0_TX_LINKPOSITIONCNTR                0x0003A2C
386 #define ACP_P1_AUDIO0_TX_FIFOADDR                        0x0003A30
387 #define ACP_P1_AUDIO0_TX_FIFOSIZE                        0x0003A34
388 #define ACP_P1_AUDIO0_TX_DMA_SIZE                        0x0003A38
389 #define ACP_P1_AUDIO0_TX_LINEARPOSITIONCNTR_HIGH         0x0003A3C
390 #define ACP_P1_AUDIO0_TX_LINEARPOSITIONCNTR_LOW          0x0003A40
391 #define ACP_P1_AUDIO0_TX_INTR_WATERMARK_SIZE             0x0003A44
392 #define ACP_P1_AUDIO1_RX_RINGBUFADDR                     0x0003A48
393 #define ACP_P1_AUDIO1_RX_RINGBUFSIZE                     0x0003A4C
394 #define ACP_P1_AUDIO1_RX_LINKPOSITIONCNTR                0x0003A50
395 #define ACP_P1_AUDIO1_RX_FIFOADDR                        0x0003A54
396 #define ACP_P1_AUDIO1_RX_FIFOSIZE                        0x0003A58
397 #define ACP_P1_AUDIO1_RX_DMA_SIZE                        0x0003A5C
398 #define ACP_P1_AUDIO1_RX_LINEARPOSITIONCNTR_HIGH         0x0003A60
399 #define ACP_P1_AUDIO1_RX_LINEARPOSITIONCNTR_LOW          0x0003A64
400 #define ACP_P1_AUDIO1_RX_INTR_WATERMARK_SIZE             0x0003A68
401 #define ACP_P1_AUDIO1_TX_RINGBUFADDR                     0x0003A6C
402 #define ACP_P1_AUDIO1_TX_RINGBUFSIZE                     0x0003A70
403 #define ACP_P1_AUDIO1_TX_LINKPOSITIONCNTR                0x0003A74
404 #define ACP_P1_AUDIO1_TX_FIFOADDR                        0x0003A78
405 #define ACP_P1_AUDIO1_TX_FIFOSIZE                        0x0003A7C
406 #define ACP_P1_AUDIO1_TX_DMA_SIZE                        0x0003A80
407 #define ACP_P1_AUDIO1_TX_LINEARPOSITIONCNTR_HIGH         0x0003A84
408 #define ACP_P1_AUDIO1_TX_LINEARPOSITIONCNTR_LOW          0x0003A88
409 #define ACP_P1_AUDIO1_TX_INTR_WATERMARK_SIZE             0x0003A8C
410 #define ACP_P1_AUDIO2_RX_RINGBUFADDR                     0x0003A90
411 #define ACP_P1_AUDIO2_RX_RINGBUFSIZE                     0x0003A94
412 #define ACP_P1_AUDIO2_RX_LINKPOSITIONCNTR                0x0003A98
413 #define ACP_P1_AUDIO2_RX_FIFOADDR                        0x0003A9C
414 #define ACP_P1_AUDIO2_RX_FIFOSIZE                        0x0003AA0
415 #define ACP_P1_AUDIO2_RX_DMA_SIZE                        0x0003AA4
416 #define ACP_P1_AUDIO2_RX_LINEARPOSITIONCNTR_HIGH         0x0003AA8
417 #define ACP_P1_AUDIO2_RX_LINEARPOSITIONCNTR_LOW          0x0003AAC
418 #define ACP_P1_AUDIO2_RX_INTR_WATERMARK_SIZE             0x0003AB0
419 #define ACP_P1_AUDIO2_TX_RINGBUFADDR                     0x0003AB4
420 #define ACP_P1_AUDIO2_TX_RINGBUFSIZE                     0x0003AB8
421 #define ACP_P1_AUDIO2_TX_LINKPOSITIONCNTR                0x0003ABC
422 #define ACP_P1_AUDIO2_TX_FIFOADDR                        0x0003AC0
423 #define ACP_P1_AUDIO2_TX_FIFOSIZE                        0x0003AC4
424 #define ACP_P1_AUDIO2_TX_DMA_SIZE                        0x0003AC8
425 #define ACP_P1_AUDIO2_TX_LINEARPOSITIONCNTR_HIGH         0x0003ACC
426 #define ACP_P1_AUDIO2_TX_LINEARPOSITIONCNTR_LOW          0x0003AD0
427 #define ACP_P1_AUDIO2_TX_INTR_WATERMARK_SIZE             0x0003AD4
428 
429 /* Registers from ACP_SW1_SWCLK block */
430 #define ACP_SW1_EN                                       0x0003C00
431 #define ACP_SW1_EN_STATUS                                0x0003C04
432 #define ACP_SW1_FRAMESIZE                                0x0003C08
433 #define ACP_SW1_SSP_COUNTER                              0x0003C0C
434 #define ACP_SW1_AUDIO1_TX_EN                             0x0003C50
435 #define ACP_SW1_AUDIO1_TX_EN_STATUS                      0x0003C54
436 #define ACP_SW1_AUDIO1_TX_FRAME_FORMAT                   0x0003C58
437 #define ACP_SW1_AUDIO1_TX_SAMPLEINTERVAL                 0x0003C5C
438 #define ACP_SW1_AUDIO1_TX_HCTRL                          0x0003C60
439 #define ACP_SW1_AUDIO1_TX_OFFSET                         0x0003C64
440 #define ACP_SW1_AUDIO1_TX_CHANNEL_ENABLE_DP0             0x0003C68
441 #define ACP_SW1_AUDIO1_RX_EN                             0x0003D28
442 #define ACP_SW1_AUDIO1_RX_EN_STATUS                      0x0003D2C
443 #define ACP_SW1_AUDIO1_RX_FRAME_FORMAT                   0x0003D30
444 #define ACP_SW1_AUDIO1_RX_SAMPLEINTERVAL                 0x0003D34
445 #define ACP_SW1_AUDIO1_RX_HCTRL                          0x0003D38
446 #define ACP_SW1_AUDIO1_RX_OFFSET                         0x0003D3C
447 #define ACP_SW1_AUDIO1_RX_CHANNEL_ENABLE_DP0             0x0003D40
448 #define ACP_SW1_BPT_PORT_EN                              0x0003D60
449 #define ACP_SW1_BPT_PORT_EN_STATUS                       0x0003D64
450 #define ACP_SW1_BPT_PORT_FRAME_FORMAT                    0x0003D68
451 #define ACP_SW1_BPT_PORT_SAMPLEINTERVAL                  0x0003D6C
452 #define ACP_SW1_BPT_PORT_HCTRL                           0x0003D70
453 #define ACP_SW1_BPT_PORT_OFFSET                          0x0003D74
454 #define ACP_SW1_BPT_PORT_CHANNEL_ENABLE                  0x0003D78
455 #define ACP_SW1_BPT_PORT_FIRST_BYTE_ADDR                 0x0003D7C
456 #define ACP_SW1_CLK_RESUME_CTRL                          0x0003D80
457 #define ACP_SW1_CLK_RESUME_DELAY_CNTR                    0x0003D84
458 #define ACP_SW1_BUS_RESET_CTRL                           0x0003D88
459 #define ACP_SW1_PRBS_ERR_STATUS                          0x0003D8C
460 
461 /* Registers from ACP_SW1_ACLK block */
462 #define ACP_SW1_CORB_BASE_ADDRESS                       0x0003E00
463 #define ACP_SW1_CORB_WRITE_POINTER                      0x0003E04
464 #define ACP_SW1_CORB_READ_POINTER                       0x0003E08
465 #define ACP_SW1_CORB_CONTROL                            0x0003E0C
466 #define ACP_SW1_CORB_SIZE                               0x0003E14
467 #define ACP_SW1_RIRB_BASE_ADDRESS                       0x0003E18
468 #define ACP_SW1_RIRB_WRITE_POINTER                      0x0003E1C
469 #define ACP_SW1_RIRB_RESPONSE_INTERRUPT_COUNT           0x0003E20
470 #define ACP_SW1_RIRB_CONTROL                            0x0003E24
471 #define ACP_SW1_RIRB_SIZE                               0x0003E28
472 #define ACP_SW1_RIRB_FIFO_MIN_THDL                      0x0003E2C
473 #define ACP_SW1_IMM_CMD_UPPER_WORD                      0x0003E30
474 #define ACP_SW1_IMM_CMD_LOWER_QWORD                     0x0003E34
475 #define ACP_SW1_IMM_RESP_UPPER_WORD                     0x0003E38
476 #define ACP_SW1_IMM_RESP_LOWER_QWORD                    0x0003E3C
477 #define ACP_SW1_IMM_CMD_STS                             0x0003E40
478 #define ACP_SW1_BRA_BASE_ADDRESS                        0x0003E44
479 #define ACP_SW1_BRA_TRANSFER_SIZE                       0x0003E48
480 #define ACP_SW1_BRA_DMA_BUSY                            0x0003E4C
481 #define ACP_SW1_BRA_RESP                                0x0003E50
482 #define ACP_SW1_BRA_RESP_FRAME_ADDR                     0x0003E54
483 #define ACP_SW1_BRA_CURRENT_TRANSFER_SIZE               0x0003E58
484 #define ACP_SW1_STATECHANGE_STATUS_0TO7                 0x0003E5C
485 #define ACP_SW1_STATECHANGE_STATUS_8TO11                0x0003E60
486 #define ACP_SW1_STATECHANGE_STATUS_MASK_0TO7            0x0003E64
487 #define ACP_SW1_STATECHANGE_STATUS_MASK_8TO11           0x0003E68
488 #define ACP_SW1_CLK_FREQUENCY_CTRL                      0x0003E6C
489 #define ACP_SW1_ERROR_INTR_MASK                         0x0003E70
490 #define ACP_SW1_PHY_TEST_MODE_DATA_OFF                  0x0003E74
491 
492 /* Registers from ACP_SCRATCH block */
493 #define ACP_SCRATCH_REG_0                               0x0010000
494 
495 #endif
496