1/* 2 * QEMU float support 3 * 4 * The code in this source file is derived from release 2a of the SoftFloat 5 * IEC/IEEE Floating-point Arithmetic Package. Those parts of the code (and 6 * some later contributions) are provided under that license, as detailed below. 7 * It has subsequently been modified by contributors to the QEMU Project, 8 * so some portions are provided under: 9 * the SoftFloat-2a license 10 * the BSD license 11 * GPL-v2-or-later 12 * 13 * Any future contributions to this file after December 1st 2014 will be 14 * taken to be licensed under the Softfloat-2a license unless specifically 15 * indicated otherwise. 16 */ 17 18/* 19=============================================================================== 20This C source fragment is part of the SoftFloat IEC/IEEE Floating-point 21Arithmetic Package, Release 2a. 22 23Written by John R. Hauser. This work was made possible in part by the 24International Computer Science Institute, located at Suite 600, 1947 Center 25Street, Berkeley, California 94704. Funding was partially provided by the 26National Science Foundation under grant MIP-9311980. The original version 27of this code was written as part of a project to build a fixed-point vector 28processor in collaboration with the University of California at Berkeley, 29overseen by Profs. Nelson Morgan and John Wawrzynek. More information 30is available through the Web page `http://HTTP.CS.Berkeley.EDU/~jhauser/ 31arithmetic/SoftFloat.html'. 32 33THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE. Although reasonable effort 34has been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT 35TIMES RESULT IN INCORRECT BEHAVIOR. USE OF THIS SOFTWARE IS RESTRICTED TO 36PERSONS AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ANY 37AND ALL LOSSES, COSTS, OR OTHER PROBLEMS ARISING FROM ITS USE. 38 39Derivative works are acceptable, even for commercial purposes, so long as 40(1) they include prominent notice that the work is derivative, and (2) they 41include prominent notice akin to these four paragraphs for those parts of 42this code that are retained. 43 44=============================================================================== 45*/ 46 47/* BSD licensing: 48 * Copyright (c) 2006, Fabrice Bellard 49 * All rights reserved. 50 * 51 * Redistribution and use in source and binary forms, with or without 52 * modification, are permitted provided that the following conditions are met: 53 * 54 * 1. Redistributions of source code must retain the above copyright notice, 55 * this list of conditions and the following disclaimer. 56 * 57 * 2. Redistributions in binary form must reproduce the above copyright notice, 58 * this list of conditions and the following disclaimer in the documentation 59 * and/or other materials provided with the distribution. 60 * 61 * 3. Neither the name of the copyright holder nor the names of its contributors 62 * may be used to endorse or promote products derived from this software without 63 * specific prior written permission. 64 * 65 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 66 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 67 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 68 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 69 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 70 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 71 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 72 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 73 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 74 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 75 * THE POSSIBILITY OF SUCH DAMAGE. 76 */ 77 78/* Portions of this work are licensed under the terms of the GNU GPL, 79 * version 2 or later. See the COPYING file in the top-level directory. 80 */ 81 82/* 83 * Define whether architecture deviates from IEEE in not supporting 84 * signaling NaNs (so all NaNs are treated as quiet). 85 */ 86static inline bool no_signaling_nans(float_status *status) 87{ 88 return status->no_signaling_nans; 89} 90 91/* Define how the architecture discriminates signaling NaNs. 92 * This done with the most significant bit of the fraction. 93 * In IEEE 754-1985 this was implementation defined, but in IEEE 754-2008 94 * the msb must be zero. MIPS is (so far) unique in supporting both the 95 * 2008 revision and backward compatibility with their original choice. 96 */ 97static inline bool snan_bit_is_one(float_status *status) 98{ 99 return status->snan_bit_is_one; 100} 101 102/*---------------------------------------------------------------------------- 103| For the deconstructed floating-point with fraction FRAC, return true 104| if the fraction represents a signalling NaN; otherwise false. 105*----------------------------------------------------------------------------*/ 106 107static bool parts_is_snan_frac(uint64_t frac, float_status *status) 108{ 109 if (no_signaling_nans(status)) { 110 return false; 111 } else { 112 bool msb = extract64(frac, DECOMPOSED_BINARY_POINT - 1, 1); 113 return msb == snan_bit_is_one(status); 114 } 115} 116 117/*---------------------------------------------------------------------------- 118| The pattern for a default generated deconstructed floating-point NaN. 119*----------------------------------------------------------------------------*/ 120 121static void parts64_default_nan(FloatParts64 *p, float_status *status) 122{ 123 bool sign = 0; 124 uint64_t frac; 125 uint8_t dnan_pattern = status->default_nan_pattern; 126 127 assert(dnan_pattern != 0); 128 129 sign = dnan_pattern >> 7; 130 /* 131 * Place default_nan_pattern [6:0] into bits [62:56], 132 * and replecate bit [0] down into [55:0] 133 */ 134 frac = deposit64(0, DECOMPOSED_BINARY_POINT - 7, 7, dnan_pattern); 135 frac = deposit64(frac, 0, DECOMPOSED_BINARY_POINT - 7, -(dnan_pattern & 1)); 136 137 *p = (FloatParts64) { 138 .cls = float_class_qnan, 139 .sign = sign, 140 .exp = INT_MAX, 141 .frac = frac 142 }; 143} 144 145static void parts128_default_nan(FloatParts128 *p, float_status *status) 146{ 147 /* 148 * Extrapolate from the choices made by parts64_default_nan to fill 149 * in the quad-floating format. If the low bit is set, assume we 150 * want to set all non-snan bits. 151 */ 152 FloatParts64 p64; 153 parts64_default_nan(&p64, status); 154 155 *p = (FloatParts128) { 156 .cls = float_class_qnan, 157 .sign = p64.sign, 158 .exp = INT_MAX, 159 .frac_hi = p64.frac, 160 .frac_lo = -(p64.frac & 1) 161 }; 162} 163 164/*---------------------------------------------------------------------------- 165| Returns a quiet NaN from a signalling NaN for the deconstructed 166| floating-point parts. 167*----------------------------------------------------------------------------*/ 168 169static uint64_t parts_silence_nan_frac(uint64_t frac, float_status *status) 170{ 171 g_assert(!no_signaling_nans(status)); 172 173 /* The only snan_bit_is_one target without default_nan_mode is HPPA. */ 174 if (snan_bit_is_one(status)) { 175 frac &= ~(1ULL << (DECOMPOSED_BINARY_POINT - 1)); 176 frac |= 1ULL << (DECOMPOSED_BINARY_POINT - 2); 177 } else { 178 frac |= 1ULL << (DECOMPOSED_BINARY_POINT - 1); 179 } 180 return frac; 181} 182 183static void parts64_silence_nan(FloatParts64 *p, float_status *status) 184{ 185 p->frac = parts_silence_nan_frac(p->frac, status); 186 p->cls = float_class_qnan; 187} 188 189static void parts128_silence_nan(FloatParts128 *p, float_status *status) 190{ 191 p->frac_hi = parts_silence_nan_frac(p->frac_hi, status); 192 p->cls = float_class_qnan; 193} 194 195/*---------------------------------------------------------------------------- 196| The pattern for a default generated extended double-precision NaN. 197*----------------------------------------------------------------------------*/ 198floatx80 floatx80_default_nan(float_status *status) 199{ 200 floatx80 r; 201 /* 202 * Extrapolate from the choices made by parts64_default_nan to fill 203 * in the floatx80 format. We assume that floatx80's explicit 204 * integer bit is always set (this is true for i386 and m68k, 205 * which are the only real users of this format). 206 */ 207 FloatParts64 p64; 208 parts64_default_nan(&p64, status); 209 210 r.high = 0x7FFF | (p64.sign << 15); 211 r.low = (1ULL << DECOMPOSED_BINARY_POINT) | p64.frac; 212 return r; 213} 214 215/*---------------------------------------------------------------------------- 216| The pattern for a default generated extended double-precision inf. 217*----------------------------------------------------------------------------*/ 218 219floatx80 floatx80_default_inf(bool zSign, float_status *status) 220{ 221 /* 222 * Whether the Integer bit is set in the default Infinity is 223 * target dependent. 224 */ 225 bool z = status->floatx80_behaviour & floatx80_default_inf_int_bit_is_zero; 226 return packFloatx80(zSign, 0x7fff, z ? 0 : (1ULL << 63)); 227} 228 229/*---------------------------------------------------------------------------- 230| Returns 1 if the half-precision floating-point value `a' is a quiet 231| NaN; otherwise returns 0. 232*----------------------------------------------------------------------------*/ 233 234bool float16_is_quiet_nan(float16 a_, float_status *status) 235{ 236 if (no_signaling_nans(status)) { 237 return float16_is_any_nan(a_); 238 } else { 239 uint16_t a = float16_val(a_); 240 if (snan_bit_is_one(status)) { 241 return (((a >> 9) & 0x3F) == 0x3E) && (a & 0x1FF); 242 } else { 243 244 return ((a >> 9) & 0x3F) == 0x3F; 245 } 246 } 247} 248 249/*---------------------------------------------------------------------------- 250| Returns 1 if the bfloat16 value `a' is a quiet 251| NaN; otherwise returns 0. 252*----------------------------------------------------------------------------*/ 253 254bool bfloat16_is_quiet_nan(bfloat16 a_, float_status *status) 255{ 256 if (no_signaling_nans(status)) { 257 return bfloat16_is_any_nan(a_); 258 } else { 259 uint16_t a = a_; 260 if (snan_bit_is_one(status)) { 261 return (((a >> 6) & 0x1FF) == 0x1FE) && (a & 0x3F); 262 } else { 263 return ((a >> 6) & 0x1FF) == 0x1FF; 264 } 265 } 266} 267 268/*---------------------------------------------------------------------------- 269| Returns 1 if the half-precision floating-point value `a' is a signaling 270| NaN; otherwise returns 0. 271*----------------------------------------------------------------------------*/ 272 273bool float16_is_signaling_nan(float16 a_, float_status *status) 274{ 275 if (no_signaling_nans(status)) { 276 return 0; 277 } else { 278 uint16_t a = float16_val(a_); 279 if (snan_bit_is_one(status)) { 280 return ((a >> 9) & 0x3F) == 0x3F; 281 } else { 282 return (((a >> 9) & 0x3F) == 0x3E) && (a & 0x1FF); 283 } 284 } 285} 286 287/*---------------------------------------------------------------------------- 288| Returns 1 if the bfloat16 value `a' is a signaling 289| NaN; otherwise returns 0. 290*----------------------------------------------------------------------------*/ 291 292bool bfloat16_is_signaling_nan(bfloat16 a_, float_status *status) 293{ 294 if (no_signaling_nans(status)) { 295 return 0; 296 } else { 297 uint16_t a = a_; 298 if (snan_bit_is_one(status)) { 299 return ((a >> 6) & 0x1FF) == 0x1FF; 300 } else { 301 return (((a >> 6) & 0x1FF) == 0x1FE) && (a & 0x3F); 302 } 303 } 304} 305 306/*---------------------------------------------------------------------------- 307| Returns 1 if the single-precision floating-point value `a' is a quiet 308| NaN; otherwise returns 0. 309*----------------------------------------------------------------------------*/ 310 311bool float32_is_quiet_nan(float32 a_, float_status *status) 312{ 313 if (no_signaling_nans(status)) { 314 return float32_is_any_nan(a_); 315 } else { 316 uint32_t a = float32_val(a_); 317 if (snan_bit_is_one(status)) { 318 return (((a >> 22) & 0x1FF) == 0x1FE) && (a & 0x003FFFFF); 319 } else { 320 return ((uint32_t)(a << 1) >= 0xFF800000); 321 } 322 } 323} 324 325/*---------------------------------------------------------------------------- 326| Returns 1 if the single-precision floating-point value `a' is a signaling 327| NaN; otherwise returns 0. 328*----------------------------------------------------------------------------*/ 329 330bool float32_is_signaling_nan(float32 a_, float_status *status) 331{ 332 if (no_signaling_nans(status)) { 333 return 0; 334 } else { 335 uint32_t a = float32_val(a_); 336 if (snan_bit_is_one(status)) { 337 return ((uint32_t)(a << 1) >= 0xFF800000); 338 } else { 339 return (((a >> 22) & 0x1FF) == 0x1FE) && (a & 0x003FFFFF); 340 } 341 } 342} 343 344/*---------------------------------------------------------------------------- 345| Returns 1 if the double-precision floating-point value `a' is a quiet 346| NaN; otherwise returns 0. 347*----------------------------------------------------------------------------*/ 348 349bool float64_is_quiet_nan(float64 a_, float_status *status) 350{ 351 if (no_signaling_nans(status)) { 352 return float64_is_any_nan(a_); 353 } else { 354 uint64_t a = float64_val(a_); 355 if (snan_bit_is_one(status)) { 356 return (((a >> 51) & 0xFFF) == 0xFFE) 357 && (a & 0x0007FFFFFFFFFFFFULL); 358 } else { 359 return ((a << 1) >= 0xFFF0000000000000ULL); 360 } 361 } 362} 363 364/*---------------------------------------------------------------------------- 365| Returns 1 if the double-precision floating-point value `a' is a signaling 366| NaN; otherwise returns 0. 367*----------------------------------------------------------------------------*/ 368 369bool float64_is_signaling_nan(float64 a_, float_status *status) 370{ 371 if (no_signaling_nans(status)) { 372 return 0; 373 } else { 374 uint64_t a = float64_val(a_); 375 if (snan_bit_is_one(status)) { 376 return ((a << 1) >= 0xFFF0000000000000ULL); 377 } else { 378 return (((a >> 51) & 0xFFF) == 0xFFE) 379 && (a & UINT64_C(0x0007FFFFFFFFFFFF)); 380 } 381 } 382} 383 384/*---------------------------------------------------------------------------- 385| Returns 1 if the extended double-precision floating-point value `a' is a 386| quiet NaN; otherwise returns 0. This slightly differs from the same 387| function for other types as floatx80 has an explicit bit. 388*----------------------------------------------------------------------------*/ 389 390int floatx80_is_quiet_nan(floatx80 a, float_status *status) 391{ 392 if (no_signaling_nans(status)) { 393 return floatx80_is_any_nan(a); 394 } else { 395 if (snan_bit_is_one(status)) { 396 uint64_t aLow; 397 398 aLow = a.low & ~0x4000000000000000ULL; 399 return ((a.high & 0x7FFF) == 0x7FFF) 400 && (aLow << 1) 401 && (a.low == aLow); 402 } else { 403 return ((a.high & 0x7FFF) == 0x7FFF) 404 && (UINT64_C(0x8000000000000000) <= ((uint64_t)(a.low << 1))); 405 } 406 } 407} 408 409/*---------------------------------------------------------------------------- 410| Returns 1 if the extended double-precision floating-point value `a' is a 411| signaling NaN; otherwise returns 0. This slightly differs from the same 412| function for other types as floatx80 has an explicit bit. 413*----------------------------------------------------------------------------*/ 414 415int floatx80_is_signaling_nan(floatx80 a, float_status *status) 416{ 417 if (no_signaling_nans(status)) { 418 return 0; 419 } else { 420 if (snan_bit_is_one(status)) { 421 return ((a.high & 0x7FFF) == 0x7FFF) 422 && ((a.low << 1) >= 0x8000000000000000ULL); 423 } else { 424 uint64_t aLow; 425 426 aLow = a.low & ~UINT64_C(0x4000000000000000); 427 return ((a.high & 0x7FFF) == 0x7FFF) 428 && (uint64_t)(aLow << 1) 429 && (a.low == aLow); 430 } 431 } 432} 433 434/*---------------------------------------------------------------------------- 435| Returns a quiet NaN from a signalling NaN for the extended double-precision 436| floating point value `a'. 437*----------------------------------------------------------------------------*/ 438 439floatx80 floatx80_silence_nan(floatx80 a, float_status *status) 440{ 441 /* None of the targets that have snan_bit_is_one use floatx80. */ 442 assert(!snan_bit_is_one(status)); 443 a.low |= UINT64_C(0xC000000000000000); 444 return a; 445} 446 447/*---------------------------------------------------------------------------- 448| Returns 1 if the quadruple-precision floating-point value `a' is a quiet 449| NaN; otherwise returns 0. 450*----------------------------------------------------------------------------*/ 451 452bool float128_is_quiet_nan(float128 a, float_status *status) 453{ 454 if (no_signaling_nans(status)) { 455 return float128_is_any_nan(a); 456 } else { 457 if (snan_bit_is_one(status)) { 458 return (((a.high >> 47) & 0xFFFF) == 0xFFFE) 459 && (a.low || (a.high & 0x00007FFFFFFFFFFFULL)); 460 } else { 461 return ((a.high << 1) >= 0xFFFF000000000000ULL) 462 && (a.low || (a.high & 0x0000FFFFFFFFFFFFULL)); 463 } 464 } 465} 466 467/*---------------------------------------------------------------------------- 468| Returns 1 if the quadruple-precision floating-point value `a' is a 469| signaling NaN; otherwise returns 0. 470*----------------------------------------------------------------------------*/ 471 472bool float128_is_signaling_nan(float128 a, float_status *status) 473{ 474 if (no_signaling_nans(status)) { 475 return 0; 476 } else { 477 if (snan_bit_is_one(status)) { 478 return ((a.high << 1) >= 0xFFFF000000000000ULL) 479 && (a.low || (a.high & 0x0000FFFFFFFFFFFFULL)); 480 } else { 481 return (((a.high >> 47) & 0xFFFF) == 0xFFFE) 482 && (a.low || (a.high & UINT64_C(0x00007FFFFFFFFFFF))); 483 } 484 } 485} 486