xref: /openbmc/linux/arch/arm64/boot/dts/qcom/sm4450.dtsi (revision 7a1fd03e)
1// SPDX-License-Identifier: BSD-3-Clause
2/*
3 * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
4 */
5
6#include <dt-bindings/gpio/gpio.h>
7#include <dt-bindings/interrupt-controller/arm-gic.h>
8
9/ {
10	interrupt-parent = <&intc>;
11
12	#address-cells = <2>;
13	#size-cells = <2>;
14
15	chosen { };
16
17	clocks{
18		xo_board: xo-board {
19			compatible = "fixed-clock";
20			clock-frequency = <76800000>;
21			#clock-cells = <0>;
22		};
23
24		sleep_clk: sleep-clk {
25			compatible = "fixed-clock";
26			clock-frequency = <32000>;
27			#clock-cells = <0>;
28		};
29	};
30
31	cpus {
32		#address-cells = <2>;
33		#size-cells = <0>;
34
35		CPU0: cpu@0 {
36			device_type = "cpu";
37			compatible = "arm,cortex-a55";
38			reg = <0x0 0x0>;
39			enable-method = "psci";
40			next-level-cache = <&L2_0>;
41			power-domains = <&CPU_PD0>;
42			power-domain-names = "psci";
43			#cooling-cells = <2>;
44
45			L2_0: l2-cache {
46				compatible = "cache";
47				cache-level = <2>;
48				cache-unified;
49				next-level-cache = <&L3_0>;
50
51				L3_0: l3-cache {
52					compatible = "cache";
53					cache-level = <3>;
54					cache-unified;
55				};
56			};
57		};
58
59		CPU1: cpu@100 {
60			device_type = "cpu";
61			compatible = "arm,cortex-a55";
62			reg = <0x0 0x100>;
63			enable-method = "psci";
64			next-level-cache = <&L2_100>;
65			power-domains = <&CPU_PD0>;
66			power-domain-names = "psci";
67			#cooling-cells = <2>;
68
69			L2_100: l2-cache {
70				compatible = "cache";
71				cache-level = <2>;
72				cache-unified;
73				next-level-cache = <&L3_0>;
74			};
75		};
76
77		CPU2: cpu@200 {
78			device_type = "cpu";
79			compatible = "arm,cortex-a55";
80			reg = <0x0 0x200>;
81			enable-method = "psci";
82			next-level-cache = <&L2_200>;
83			power-domains = <&CPU_PD0>;
84			power-domain-names = "psci";
85			#cooling-cells = <2>;
86
87			L2_200: l2-cache {
88				compatible = "cache";
89				cache-level = <2>;
90				cache-unified;
91				next-level-cache = <&L3_0>;
92			};
93		};
94
95		CPU3: cpu@300 {
96			device_type = "cpu";
97			compatible = "arm,cortex-a55";
98			reg = <0x0 0x300>;
99			enable-method = "psci";
100			next-level-cache = <&L2_300>;
101			power-domains = <&CPU_PD0>;
102			power-domain-names = "psci";
103			#cooling-cells = <2>;
104
105			L2_300: l2-cache {
106				compatible = "cache";
107				cache-level = <2>;
108				cache-unified;
109				next-level-cache = <&L3_0>;
110			};
111		};
112
113		CPU4: cpu@400 {
114			device_type = "cpu";
115			compatible = "arm,cortex-a55";
116			reg = <0x0 0x400>;
117			enable-method = "psci";
118			next-level-cache = <&L2_400>;
119			power-domains = <&CPU_PD0>;
120			power-domain-names = "psci";
121			#cooling-cells = <2>;
122
123			L2_400: l2-cache {
124				compatible = "cache";
125				cache-level = <2>;
126				cache-unified;
127				next-level-cache = <&L3_0>;
128			};
129		};
130
131		CPU5: cpu@500 {
132			device_type = "cpu";
133			compatible = "arm,cortex-a55";
134			reg = <0x0 0x500>;
135			enable-method = "psci";
136			next-level-cache = <&L2_500>;
137			power-domains = <&CPU_PD0>;
138			power-domain-names = "psci";
139			#cooling-cells = <2>;
140
141			L2_500: l2-cache {
142				compatible = "cache";
143				cache-level = <2>;
144				cache-unified;
145				next-level-cache = <&L3_0>;
146			};
147		};
148
149		CPU6: cpu@600 {
150			device_type = "cpu";
151			compatible = "arm,cortex-a78";
152			reg = <0x0 0x600>;
153			enable-method = "psci";
154			next-level-cache = <&L2_600>;
155			power-domains = <&CPU_PD0>;
156			power-domain-names = "psci";
157			#cooling-cells = <2>;
158
159			L2_600: l2-cache {
160				compatible = "cache";
161				cache-level = <2>;
162				cache-unified;
163				next-level-cache = <&L3_0>;
164			};
165		};
166
167		CPU7: cpu@700 {
168			device_type = "cpu";
169			compatible = "arm,cortex-a78";
170			reg = <0x0 0x700>;
171			enable-method = "psci";
172			next-level-cache = <&L2_700>;
173			power-domains = <&CPU_PD0>;
174			power-domain-names = "psci";
175			#cooling-cells = <2>;
176
177			L2_700: l2-cache {
178				compatible = "cache";
179				cache-level = <2>;
180				cache-unified;
181				next-level-cache = <&L3_0>;
182			};
183		};
184
185		cpu-map {
186			cluster0 {
187				core0 {
188					cpu = <&CPU0>;
189				};
190
191				core1 {
192					cpu = <&CPU1>;
193				};
194
195				core2 {
196					cpu = <&CPU2>;
197				};
198
199				core3 {
200					cpu = <&CPU3>;
201				};
202
203				core4 {
204					cpu = <&CPU4>;
205				};
206
207				core5 {
208					cpu = <&CPU5>;
209				};
210
211				core6 {
212					cpu = <&CPU6>;
213				};
214
215				core7 {
216					cpu = <&CPU7>;
217				};
218			};
219		};
220
221		idle-states {
222			entry-method = "psci";
223
224			LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
225				compatible = "arm,idle-state";
226				arm,psci-suspend-param = <0x40000004>;
227				entry-latency-us = <800>;
228				exit-latency-us = <750>;
229				min-residency-us = <4090>;
230				local-timer-stop;
231			};
232
233			BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
234				compatible = "arm,idle-state";
235				arm,psci-suspend-param = <0x40000004>;
236				entry-latency-us = <600>;
237				exit-latency-us = <1550>;
238				min-residency-us = <4791>;
239				local-timer-stop;
240			};
241		};
242
243		domain-idle-states {
244			CLUSTER_SLEEP_0: cluster-sleep-0 {
245				compatible = "domain-idle-state";
246				arm,psci-suspend-param = <0x41000044>;
247				entry-latency-us = <1050>;
248				exit-latency-us = <2500>;
249				min-residency-us = <5309>;
250			};
251
252			CLUSTER_SLEEP_1: cluster-sleep-1 {
253				compatible = "domain-idle-state";
254				arm,psci-suspend-param = <0x41003344>;
255				entry-latency-us = <1561>;
256				exit-latency-us = <2801>;
257				min-residency-us = <8550>;
258			};
259		};
260	};
261
262	memory@a0000000 {
263		device_type = "memory";
264		/* We expect the bootloader to fill in the size */
265		reg = <0x0 0xa0000000 0x0 0x0>;
266	};
267
268	pmu {
269		compatible = "arm,armv8-pmuv3";
270		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
271	};
272
273	psci {
274		compatible = "arm,psci-1.0";
275		method = "smc";
276
277		CPU_PD0: power-domain-cpu0 {
278			#power-domain-cells = <0>;
279			power-domains = <&CLUSTER_PD>;
280			domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
281		};
282
283		CPU_PD1: power-domain-cpu1 {
284			#power-domain-cells = <0>;
285			power-domains = <&CLUSTER_PD>;
286			domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
287		};
288
289		CPU_PD2: power-domain-cpu2 {
290			#power-domain-cells = <0>;
291			power-domains = <&CLUSTER_PD>;
292			domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
293		};
294
295		CPU_PD3: power-domain-cpu3 {
296			#power-domain-cells = <0>;
297			power-domains = <&CLUSTER_PD>;
298			domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
299		};
300
301		CPU_PD4: power-domain-cpu4 {
302			#power-domain-cells = <0>;
303			power-domains = <&CLUSTER_PD>;
304			domain-idle-states = <&BIG_CPU_SLEEP_0>;
305		};
306
307		CPU_PD5: power-domain-cpu5 {
308			#power-domain-cells = <0>;
309			power-domains = <&CLUSTER_PD>;
310			domain-idle-states = <&BIG_CPU_SLEEP_0>;
311		};
312
313		CPU_PD6: power-domain-cpu6 {
314			#power-domain-cells = <0>;
315			power-domains = <&CLUSTER_PD>;
316			domain-idle-states = <&BIG_CPU_SLEEP_0>;
317		};
318
319		CPU_PD7: power-domain-cpu7 {
320			#power-domain-cells = <0>;
321			power-domains = <&CLUSTER_PD>;
322			domain-idle-states = <&BIG_CPU_SLEEP_0>;
323		};
324
325		CLUSTER_PD: power-domain-cpu-cluster0 {
326			#power-domain-cells = <0>;
327			domain-idle-states = <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>;
328		};
329	};
330
331	soc: soc@0 {
332		#address-cells = <2>;
333		#size-cells = <2>;
334		ranges = <0 0 0 0 0x10 0>;
335		dma-ranges = <0 0 0 0 0x10 0>;
336		compatible = "simple-bus";
337
338		tcsr_mutex: hwlock@1f40000 {
339			compatible = "qcom,tcsr-mutex";
340			reg = <0x0 0x01f40000 0x0 0x40000>;
341			#hwlock-cells = <1>;
342		};
343
344		pdc: interrupt-controller@b220000 {
345			compatible = "qcom,sm4450-pdc", "qcom,pdc";
346			reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>;
347			qcom,pdc-ranges = <0 480 94>, <94 494 31>,
348					  <125 63 1>;
349			#interrupt-cells = <2>;
350			interrupt-parent = <&intc>;
351			interrupt-controller;
352		};
353
354		intc: interrupt-controller@17200000 {
355			compatible = "arm,gic-v3";
356			reg = <0x0 0x17200000 0x0 0x10000>,     /* GICD */
357			      <0x0 0x17260000 0x0 0x100000>;    /* GICR * 8 */
358			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
359			#interrupt-cells = <3>;
360			interrupt-controller;
361			#redistributor-regions = <1>;
362			redistributor-stride = <0x0 0x20000>;
363		};
364
365		timer@17420000 {
366			compatible = "arm,armv7-timer-mem";
367			reg = <0x0 0x17420000 0x0 0x1000>;
368			ranges = <0 0 0 0x20000000>;
369			#address-cells = <1>;
370			#size-cells = <1>;
371
372			frame@17421000 {
373				reg = <0x17421000 0x1000>,
374				      <0x17422000 0x1000>;
375				frame-number = <0>;
376				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
377					     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
378			};
379
380			frame@17423000 {
381				reg = <0x17423000 0x1000>;
382				frame-number = <1>;
383				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
384				status = "disabled";
385			};
386
387			frame@17425000 {
388				reg = <0x17425000 0x1000>;
389				frame-number = <2>;
390				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
391				status = "disabled";
392			};
393
394			frame@17427000 {
395				reg = <0x17427000 0x1000>;
396				frame-number = <3>;
397				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
398				status = "disabled";
399			};
400
401			frame@17429000 {
402				reg = <0x17429000 0x1000>;
403				frame-number = <4>;
404				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
405				status = "disabled";
406			};
407
408			frame@1742b000 {
409				reg = <0x1742b000 0x1000>;
410				frame-number = <5>;
411				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
412				status = "disabled";
413			};
414
415			frame@1742d000 {
416				reg = <0x1742d000 0x1000>;
417				frame-number = <6>;
418				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
419				status = "disabled";
420			};
421		};
422	};
423
424	timer {
425		compatible = "arm,armv8-timer";
426		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
427			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
428			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
429			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
430	};
431};
432