1 #ifndef CPER_SECTION_PCIE_H 2 #define CPER_SECTION_PCIE_H 3 4 #ifdef __cplusplus 5 extern "C" { 6 #endif 7 8 #include <stdio.h> 9 #include <json.h> 10 #include <libcper/Cper.h> 11 12 #define PCIE_ERROR_VALID_BITFIELD_NAMES \ 13 (const char *[]){ "portTypeValid", \ 14 "versionValid", \ 15 "commandStatusValid", \ 16 "deviceIDValid", \ 17 "deviceSerialNumberValid", \ 18 "bridgeControlStatusValid", \ 19 "capabilityStructureStatusValid", \ 20 "aerInfoValid" } 21 #define PCIE_ERROR_PORT_TYPES_KEYS (int[]){ 0, 1, 4, 5, 6, 7, 8, 9, 10 } 22 #define PCIE_ERROR_PORT_TYPES_VALUES \ 23 (const char *[]){ "PCI Express End Point", \ 24 "Legacy PCI End Point Device", \ 25 "Root Port", \ 26 "Upstream Switch Port", \ 27 "Downstream Switch Port", \ 28 "PCI Express to PCI/PCI-X Bridge", \ 29 "PCI/PCI-X Bridge to PCI Express Bridge", \ 30 "Root Complex Integrated Endpoint Device", \ 31 "Root Complex Event Collector" } 32 33 struct class_code { 34 UINT8 base; 35 UINT8 sub; 36 UINT8 programming; 37 const char *name; 38 }; 39 40 json_object *cper_section_pcie_to_ir(const UINT8 *section, UINT32 size); 41 void ir_section_pcie_to_cper(json_object *section, FILE *out); 42 43 /* 44 * This file is designed as a standard c header file and as a script friendly 45 * source fo the PCIe PCIe Capability and Advanced Error Registers structures. 46 * The template of each register is: 47 * 48 * 49 * * <Name of Capabaility Structure> 50 * * CAPABILITY_ID = <id of capability structure> 51 * * <Register Name> 52 * * Offset: <offset of the register in the capability structure> 53 * struct { 54 * <register width> <field name> : <field width>; 55 * <register width> <field name> : <field width>; 56 * <register width> <field name> : <field width>; 57 * } 58 */ 59 60 /* 61 * PCI Express Capability Structure 62 * CAPABILITY_ID = 0x10 63 * PCI Express Capability Structure Header 64 * Offset: 0x0 65 */ 66 typedef struct { 67 UINT16 capability_id : 8; // bits [7:0] - Capability ID (should be 0x10) 68 UINT16 next_capability_pointer : 8; // bits [7:0] - Next capability pointer 69 } __attribute__((packed)) pcie_capability_header_t; 70 71 /* 72 * PCI Express Capability Structure 73 * CAPABILITY_ID = 0x10 74 * PCI Express Capabilities Register 75 * Offset: 0x2 76 */ 77 typedef struct { 78 UINT16 capability_version : 4; // bits [3:0] 79 UINT16 device_port_type : 4; // bits [7:4] 80 UINT16 slot_implemented : 1; // bit [8] 81 UINT16 interrupt_message_number : 5; // bits [13:9] 82 UINT16 undefined : 1; // bit [14] 83 UINT16 flit_mode_supported : 1; // bit [15] 84 } __attribute__((packed)) pcie_capabilities_t; 85 86 static const char *device_port_type_dict[] = { 87 "PCIE", // 0x0 88 "PCI", // 0x1 89 "ROOT_PORT", // 0x4 90 "UPSTREAM", // 0x5 91 "DOWNSTREAM", // 0x6 92 "PCIE_PCI_BRIDGE", // 0x7 93 "PCI_PCIE_BRIDGE", // 0x8 94 "RCiEP", // 0x9 95 "RCEC", // 0xa 96 }; 97 98 static const size_t device_port_type_dict_size = 99 sizeof(device_port_type_dict) / sizeof(device_port_type_dict[0]); 100 101 /* 102 * Begin Of PCIe Capability Registers 103 */ 104 105 /* 106 * PCI Express Capability Structure 107 * CAPABILITY_ID = 0x10 108 * Device Capabilities Register 109 * Offset: 0x4 110 */ 111 typedef struct { 112 UINT32 max_payload_size_supported : 3; // bits [2:0] 113 UINT32 phantom_functions_supported : 2; // bits [4:3] 114 UINT32 extended_tag_field_supported : 1; // bit [5] 115 UINT32 endpoint_l0s_acceptable_latency : 3; // bits [8:6] 116 UINT32 endpoint_l1_acceptable_latency : 3; // bits [11:9] 117 UINT32 undefined : 3; // bits [14:12] 118 UINT32 role_based_error_reporting : 1; // bit [15] 119 UINT32 err_cor_subclass_capable : 1; // bit [16] 120 UINT32 rx_mps_fixed : 1; // bits [17] 121 UINT32 captured_slot_power_limit_value : 8; // bits [25:18] 122 UINT32 captured_slot_power_limit_scale : 2; // bits [27:26] 123 UINT32 function_level_reset_capability : 1; // bit [28] 124 UINT32 mixed_mps_supported : 1; // bit [29] 125 UINT32 tee_io_supported : 1; // bit [30] 126 UINT32 rsvdp : 1; // bit [31] 127 } __attribute__((packed)) device_capabilities_t; 128 129 /* 130 * PCI Express Capability Structure 131 * CAPABILITY_ID = 0x10 132 * Device Control Register 133 * Offset: 0x8 134 */ 135 typedef struct { 136 UINT16 correctable_error_reporting_enable : 1; // bit [0] 137 UINT16 non_fatal_error_reporting_enable : 1; // bit [1] 138 UINT16 fatal_error_reporting_enable : 1; // bit [2] 139 UINT16 unsupported_request_reporting_enable : 1; // bit [3] 140 UINT16 enable_relaxed_ordering : 1; // bit [4] 141 UINT16 max_payload_size : 3; // bits [7:5] 142 UINT16 extended_tag_field_enable : 1; // bit [8] 143 UINT16 phantom_functions_enable : 1; // bit [9] 144 UINT16 aux_power_pm_enable : 1; // bit [10] 145 UINT16 enable_no_snoop : 1; // bit [11] 146 UINT16 max_read_request_size : 3; // bits [14:12] 147 UINT16 function_level_reset : 1; // bit [15] 148 } __attribute__((packed)) device_control_t; 149 150 /* 151 * PCI Express Capability Structure 152 * CAPABILITY_ID = 0x10 153 * Device Status Register 154 * Offset: 0xA 155 */ 156 typedef struct { 157 UINT16 correctable_error_detected : 1; // bit [0] 158 UINT16 non_fatal_error_detected : 1; // bit [1] 159 UINT16 fatal_error_detected : 1; // bit [2] 160 UINT16 unsupported_request_detected : 1; // bit [3] 161 UINT16 aux_power_detected : 1; // bit [4] 162 UINT16 transactions_pending : 1; // bit [5] 163 UINT16 emergency_power_reduction : 2; // bits [7:6] (PCIe 4.0+) 164 UINT16 rsvdz : 8; // bits [15:8] 165 } __attribute__((packed)) device_status_t; 166 167 /* 168 * PCI Express Capability Structure 169 * CAPABILITY_ID = 0x10 170 * Link Capabilities Register 171 * Offset: 0xC 172 */ 173 typedef struct { 174 UINT32 max_link_speed : 4; // bits [3:0] 175 UINT32 maximum_link_width : 6; // bits [9:4] 176 UINT32 aspm_support : 2; // bits [11:10] 177 UINT32 l0s_exit_latency : 3; // bits [14:12] 178 UINT32 l1_exit_latency : 3; // bits [17:15] 179 UINT32 clock_power_management : 1; // bit [18] 180 UINT32 surprise_down_error_reporting_capable : 1; // bit [19] 181 UINT32 data_link_layer_link_active_reporting_capable : 1; // bit [20] 182 UINT32 link_bandwidth_notification_capability : 1; // bit [21] 183 UINT32 aspm_optionality_compliance : 1; // bit [22] 184 UINT32 rsvdp : 1; // bit [23] 185 UINT32 port_number : 8; // bits [31:24] 186 } __attribute__((packed)) link_capabilities_t; 187 188 /* 189 * PCI Express Capability Structure 190 * CAPABILITY_ID = 0x10 191 * Link Control Register 192 * Offset: 0x10 193 */ 194 typedef struct { 195 UINT16 aspm_control : 2; // bits [1:0] 196 // ptm_propagation_delay_adaptation_interpretation_bit 197 UINT16 ptm_prop_delay_adaptation_interpretation : 1; // bit [2] 198 UINT16 read_completion_boundary : 1; // bit [3] 199 UINT16 link_disable : 1; // bit [4] 200 UINT16 retrain_link : 1; // bit [5] 201 UINT16 common_clock_configuration : 1; // bit [6] 202 UINT16 extended_synch : 1; // bit [7] 203 UINT16 enable_clock_power_management : 1; // bit [8] 204 UINT16 hardware_autonomous_width_disable : 1; // bit [9] 205 UINT16 link_bandwidth_management_interrupt_enable : 1; // bit [10] 206 UINT16 link_autonomous_bandwidth_interrupt_enable : 1; // bit [11] 207 UINT16 sris_clocking : 1; // bit [12] 208 UINT16 flit_mode_disable : 1; // bit [13] 209 UINT16 drs_signaling_control : 1; // bits [15:14] 210 } __attribute__((packed)) link_control_t; 211 212 /* 213 * PCI Express Capability Structure 214 * CAPABILITY_ID = 0x10 215 * Link Status Register 216 * Offset: 0x12 217 */ 218 typedef struct { 219 UINT16 current_link_speed : 4; // bits [3:0] 220 UINT16 negotiated_link_width : 6; // bits [9:4] 221 UINT16 undefined : 1; // bit [10] 222 UINT16 link_training : 1; // bit [11] 223 UINT16 slot_clock_configuration : 1; // bit [12] 224 UINT16 data_link_layer_link_active : 1; // bit [13] 225 UINT16 link_bandwidth_management_status : 1; // bit [14] 226 UINT16 link_autonomous_bandwidth_status : 1; // bit [15] 227 } __attribute__((packed)) link_status_t; 228 229 /* 230 * PCI Express Capability Structure 231 * CAPABILITY_ID = 0x10 232 * Slot Capabilities Register 233 * Offset: 0x14 234 */ 235 typedef struct { 236 UINT32 attention_button_present : 1; // bit [0] 237 UINT32 power_controller_present : 1; // bit [1] 238 UINT32 mrl_sensor_present : 1; // bit [2] 239 UINT32 attention_indicator_present : 1; // bit [3] 240 UINT32 power_indicator_present : 1; // bit [4] 241 UINT32 hot_plug_surprise : 1; // bit [5] 242 UINT32 hot_plug_capable : 1; // bit [6] 243 UINT32 slot_power_limit_value : 8; // bits [14:7] 244 UINT32 slot_power_limit_scale : 2; // bits [16:15] 245 UINT32 electromechanical_interlock_present : 1; // bit [17] 246 UINT32 no_command_completed_support : 1; // bit [18] 247 UINT32 physical_slot_number : 13; // bits [31:19] 248 } __attribute__((packed)) slot_capabilities_t; 249 250 /* 251 * PCI Express Capability Structure 252 * CAPABILITY_ID = 0x10 253 * Slot Control Register 254 * Offset: 0x18 255 */ 256 typedef struct { 257 UINT16 attention_button_pressed_enable : 1; // bit [0] 258 UINT16 power_fault_detected_enable : 1; // bit [1] 259 UINT16 mrl_sensor_changed_enable : 1; // bit [2] 260 UINT16 presence_detect_changed_enable : 1; // bit [3] 261 UINT16 command_completed_interrupt_enable : 1; // bit [4] 262 UINT16 hot_plug_interrupt_enable : 1; // bit [5] 263 UINT16 attention_indicator_control : 2; // bits [7:6] 264 UINT16 power_indicator_control : 2; // bits [9:8] 265 UINT16 power_controller_control : 1; // bit [10] 266 UINT16 electromechanical_interlock_control : 1; // bit [11] 267 UINT16 data_link_layer_state_changed_enable : 1; // bit [12] 268 UINT16 auto_slot_power_limit_disable : 1; // bit [13] 269 UINT16 in_band_pd_disable : 1; // bit [14] 270 UINT16 rsvdp : 1; // bit [15] 271 } __attribute__((packed)) slot_control_t; 272 273 /* 274 * PCI Express Capability Structure 275 * CAPABILITY_ID = 0x10 276 * Slot Status Register 277 * Offset: 0x1A 278 */ 279 typedef struct { 280 UINT16 attention_button_pressed : 1; // bit [0] 281 UINT16 power_fault_detected : 1; // bit [1] 282 UINT16 mrl_sensor_changed : 1; // bit [2] 283 UINT16 presence_detect_changed : 1; // bit [3] 284 UINT16 command_completed : 1; // bit [4] 285 UINT16 mrl_sensor_state : 1; // bit [5] 286 UINT16 presence_detect_state : 1; // bit [6] 287 UINT16 electromechanical_interlock_status : 1; // bit [7] 288 UINT16 data_link_layer_state_changed : 1; // bit [8] 289 UINT16 rsvdz : 7; // bits [15:9] 290 } __attribute__((packed)) slot_status_t; 291 292 /* 293 * PCI Express Capability Structure 294 * CAPABILITY_ID = 0x10 295 * Root Control Register 296 * Offset: 0x1C 297 */ 298 typedef struct { 299 UINT16 system_error_on_correctable_error_enable : 1; // bit [0] 300 UINT16 system_error_on_non_fatal_error_enable : 1; // bit [1] 301 UINT16 system_error_on_fatal_error_enable : 1; // bit [2] 302 UINT16 pme_interrupt_enable : 1; // bit [3] 303 UINT16 configuration_rrs_software_visibility_enable : 1; // bit [4] 304 UINT16 no_nfm_subtree_below_this_root_port : 1; // bit [5] 305 UINT16 rsvdp : 10; // bits [15:6] 306 } __attribute__((packed)) root_control_t; 307 308 /* 309 * PCI Express Capability Structure 310 * CAPABILITY_ID = 0x10 311 * Root Capabilities Register 312 * Offset: 0x1E 313 */ 314 typedef struct { 315 UINT16 configuraton_rrs_software_visibility : 1; // bit [0] 316 UINT16 rsvdp : 15; // bits [15:1] 317 } __attribute__((packed)) root_capabilities_t; 318 319 /* 320 * PCI Express Capability Structure 321 * CAPABILITY_ID = 0x10 322 * Root Status Register 323 * Offset: 0x20 324 */ 325 typedef struct { 326 UINT32 pme_requester_id : 16; // bits [15:0] 327 UINT32 pme_status : 1; // bit [16] 328 UINT32 pme_pending : 1; // bit [17] 329 UINT32 rsvdp : 14; // bits [31:18] 330 } __attribute__((packed)) root_status_t; 331 332 /* 333 * PCI Express Capability Structure 334 * CAPABILITY_ID = 0x10 335 * Device Capabilities 2 Register 336 * Offset: 0x24 337 */ 338 typedef struct { 339 UINT32 completion_timeout_ranges_supported : 4; // bits [3:0] 340 UINT32 completion_timeout_disable_supported : 1; // bit [4] 341 UINT32 ari_forwarding_supported : 1; // bit [5] 342 UINT32 atomic_op_routing_supported : 1; // bit [6] 343 UINT32 _32_bit_atomicop_completer_supported : 1; // bit [7] 344 UINT32 _64_bit_atomicop_completer_supported : 1; // bit [8] 345 UINT32 _128_bit_cas_completer_supported : 1; // bit [9] 346 UINT32 no_ro_enabled_pr_pr_passing : 1; // bit [10] 347 UINT32 ltr_mechanism_supported : 1; // bit [11] 348 UINT32 tph_completer_supported : 2; // bits [13:12] 349 UINT32 undefined : 2; // bit [15:14] 350 UINT32 _10_bit_tag_completer_supported : 1; // bit [16] 351 UINT32 _10_bit_tag_requester_supported : 1; // bit [17] 352 UINT32 obff_supported : 2; // bits [19:18] 353 UINT32 extended_fmt_field_supported : 1; // bit [20] 354 UINT32 end_end_tlp_prefix_supported : 1; // bit [21] 355 UINT32 max_end_end_tlp_prefixes : 2; // bits [23:22] 356 UINT32 emergency_power_reduction_supported : 2; // bits [25:24] 357 // emergency_power_reduction_initialization_required 358 UINT32 emergency_power_reduction_init_required : 1; // bit [26] 359 UINT32 rsvdp : 1; // bit [27] 360 UINT32 dmwr_completer_supported : 1; // bit [28] 361 UINT32 dmwr_lengths_supported : 2; // bits [30:29] 362 UINT32 frs_supported : 1; // bit [31] 363 } __attribute__((packed)) device_capabilities2_t; 364 365 /* 366 * PCI Express Capability Structure 367 * CAPABILITY_ID = 0x10 368 * Device Control 2 Register 369 * Offset: 0x28 370 */ 371 typedef struct { 372 UINT16 completion_timeout_value : 4; // bits [3:0] 373 UINT16 completion_timeout_disable : 1; // bit [4] 374 UINT16 ari_forwarding_enable : 1; // bit [5] 375 UINT16 atomicop_requester_enable : 1; // bit [6] 376 UINT16 atomicop_egress_blocking : 1; // bit [7] 377 UINT16 ido_request_enable : 1; // bit [8] 378 UINT16 ido_completion_enable : 1; // bit [9] 379 UINT16 ltr_mechanism_enable : 1; // bit [10] 380 UINT16 emergency_power_reduction_request : 1; // bit [11] 381 UINT16 bit_tag_requester_10_enable : 1; // bit [12] 382 UINT16 obff_enable : 2; // bits [14:13] 383 UINT16 end_end_tlp_prefix_blocking : 1; // bit [15] 384 } __attribute__((packed)) device_control2_t; 385 386 /* 387 * PCI Express Capability Structure 388 * CAPABILITY_ID = 0x10 389 * Device Status 2 Register 390 * Offset: 0x2A 391 */ 392 typedef struct { 393 UINT16 rsvdz : 16; // bits [15:0] 394 } __attribute__((packed)) device_status2_t; 395 396 /* 397 * PCI Express Capability Structure 398 * CAPABILITY_ID = 0x10 399 * Link Capabilities 2 Register 400 * Offset: 0x2C 401 */ 402 typedef struct { 403 UINT32 rsvdp : 1; // bit [0] 404 union { 405 struct { 406 UINT32 l_2_5g_supported : 1; 407 UINT32 l_5g_supported : 1; 408 UINT32 l_8g_supported : 1; 409 UINT32 l_16g_supported : 1; 410 UINT32 l_32g_supported : 1; 411 UINT32 reserved1 : 1; 412 UINT32 reserved2 : 1; 413 } __attribute__((packed)) supported_link_speeds; 414 UINT32 supported_link_speeds_register : 7; // bits [7:1] 415 }; 416 417 UINT32 crosslink_supported : 1; // bit [8] 418 UINT32 lower_skp_os_generation_supported : 7; // bit [15:9] 419 UINT32 lower_skp_os_reception_supported : 7; // bit [22:16] 420 UINT32 retimer_presence_detect_supported : 1; // bit [23] 421 UINT32 two_retimers_presence_detect_supported : 1; // bit [24] 422 UINT32 reserved : 6; // bits [30:25] 423 UINT32 drs_supported : 1; // bit [31] 424 } __attribute__((packed)) link_capabilities2_t; 425 426 /* 427 * PCI Express Capability Structure 428 * CAPABILITY_ID = 0x10 429 * Link Control 2 Register 430 * Offset: 0x30 431 */ 432 typedef struct { 433 UINT16 target_link_speed : 4; // bits [3:0] 434 UINT16 enter_compliance : 1; // bit [4] 435 UINT16 hardware_autonomous_speed_disable : 1; // bit [5] 436 UINT16 selectable_de_emphasis : 1; // bit [6] 437 UINT16 transmit_margin : 3; // bits [9:7] 438 UINT16 enter_modified_compliance : 1; // bit [10] 439 UINT16 compliance_sos : 1; // bit [11] 440 UINT16 compliance_preset_de_emphasis : 4; // bits [15:12] 441 } __attribute__((packed)) link_control2_t; 442 443 /* 444 * PCI Express Capability Structure 445 * CAPABILITY_ID = 0x10 446 * Link Status 2 Register 447 * Offset: 0x32 448 */ 449 typedef struct { 450 UINT16 current_de_emphasis_level : 1; // bit [0] 451 UINT16 equalization_8gts_complete : 1; // bit [1] 452 UINT16 equalization_8gts_phase1_successful : 1; // bit [2] 453 UINT16 equalization_8gts_phase2_successful : 1; // bit [3] 454 UINT16 equalization_8gts_phase3_successful : 1; // bit [4] 455 UINT16 link_equalization_request_8gts : 1; // bit [5] 456 UINT16 retimer_presence_detected : 1; // bit [6] 457 UINT16 two_retimers_presence_detected : 1; // bit [7] 458 UINT16 crosslink_resolution : 2; // bits [9:8] 459 UINT16 flit_mode_status : 1; // bit [10] 460 UINT16 rsvdz : 1; // bit [11] 461 UINT16 downstream_component_presence : 3; // bits [14:12] 462 UINT16 drs_message_received : 1; // bit [15] 463 } __attribute__((packed)) link_status2_t; 464 465 /* 466 * PCI Express Capability Structure 467 * CAPABILITY_ID = 0x10 468 * Slot Capabilities 2 Register 469 * Offset: 0x34 470 */ 471 typedef struct { 472 UINT32 rsvdp : 32; // bits [31:0] 473 } __attribute__((packed)) slot_capabilities2_t; 474 475 /* 476 * PCI Express Capability Structure 477 * CAPABILITY_ID = 0x10 478 * Slot Control 2 Register 479 * Offset: 0x38 480 */ 481 typedef struct { 482 UINT16 rsvdp : 16; // bits [15:0] 483 } __attribute__((packed)) slot_control2_t; 484 485 /* 486 * PCI Express Capability Structure 487 * CAPABILITY_ID = 0x10 488 * Slot Status 2 Register 489 * Offset: 0x3A 490 */ 491 typedef struct { 492 UINT16 rsvdp : 16; // bits [15:0] 493 } __attribute__((packed)) slot_status2_t; 494 495 /* 496 * End Of PCIe Capability Registers 497 */ 498 499 /* 500 * Begin Of AER Registers 501 */ 502 503 /* 504 * PCI Express Advanced Error Reporting Capability Structure 505 * CAPABILITY_ID = 0x01 506 * AER Capability Header 507 * Offset: 0x0 508 */ 509 typedef struct { 510 UINT16 capability_id : 16; // bits [15:0] 511 UINT16 capability_version : 4; // bits [19:16] 512 UINT16 next_capability_offset : 12; // bits [31:20] 513 } __attribute__((packed)) capability_header_t; 514 515 /* 516 * PCI Express Advanced Error Reporting Capability Structure 517 * CAPABILITY_ID = 0x01 518 * Uncorrectable Error Status Register 519 * Offset: 0x4 520 */ 521 typedef struct { 522 UINT32 undefined : 1; // bits [0] 523 UINT32 rsvdz1 : 3; // bits [3:1] 524 UINT32 data_link_protocol_error_status : 1; // bit [4] 525 UINT32 surprise_down_error_status : 1; // bit [5] 526 UINT32 rsvdz2 : 6; // bits [11:6] 527 UINT32 poisoned_tlp_received : 1; // bit [12] 528 UINT32 flow_control_protocol_error_status : 1; // bit [13] 529 UINT32 completion_timeout_status : 1; // bit [14] 530 UINT32 completer_abort_status : 1; // bit [15] 531 UINT32 unexpected_completion_status : 1; // bit [16] 532 UINT32 receiver_overflow_status : 1; // bit [17] 533 UINT32 malformed_tlp_status : 1; // bit [18] 534 UINT32 ecrc_error_status : 1; // bit [19] 535 UINT32 unsupported_request_error_status : 1; // bit [20] 536 UINT32 acs_violation_status : 1; // bit [21] 537 UINT32 uncorrectable_internal_error_status : 1; // bit [22] 538 UINT32 mc_blocked_tlp_status : 1; // bit [23] 539 UINT32 atomicop_egress_blocked_status : 1; // bit [24] 540 UINT32 tlp_prefix_blocked_error_status : 1; // bit [25] 541 UINT32 poisoned_tlp_egress_blocked_status : 1; // bit [26] 542 UINT32 dmwr_request_egress_blocked_status : 1; // bit [27] 543 UINT32 ide_check_failed_status : 1; // bit [28] 544 UINT32 misrouted_ide_tlp_status : 1; // bit [29] 545 UINT32 pcrc_check_failed_status : 1; // bit [30] 546 UINT32 tlp_translation_egress_blocked_status : 1; // bit [31] 547 } __attribute__((packed)) uncorrectable_error_status_t; 548 549 /* 550 * PCI Express Advanced Error Reporting Capability Structure 551 * CAPABILITY_ID = 0x01 552 * Uncorrectable Error Mask Register 553 * Offset: 0x8 554 */ 555 typedef struct { 556 UINT32 undefined : 1; // bits [0] 557 UINT32 rsvdz1 : 3; // bits [3:1] 558 UINT32 data_link_protocol_error_mask : 1; // bit [4] 559 UINT32 surprise_down_error_mask : 1; // bit [5] 560 UINT32 rsvdz2 : 6; // bits [11:6] 561 UINT32 poisoned_tlp_received_mask : 1; // bit [12] 562 UINT32 flow_control_protocol_error_mask : 1; // bit [13] 563 UINT32 completion_timeout_mask : 1; // bit [14] 564 UINT32 completer_abort_mask : 1; // bit [15] 565 UINT32 unexpected_completion_mask : 1; // bit [16] 566 UINT32 receiver_overflow_mask : 1; // bit [17] 567 UINT32 malformed_tlp_mask : 1; // bit [18] 568 UINT32 ecrc_error_mask : 1; // bit [19] 569 UINT32 unsupported_request_error_mask : 1; // bit [20] 570 UINT32 acs_violation_mask : 1; // bit [21] 571 UINT32 uncorrectable_internal_error_mask : 1; // bit [22] 572 UINT32 mc_blocked_tlp_mask : 1; // bit [23] 573 UINT32 atomicop_egress_blocked_mask : 1; // bit [24] 574 UINT32 tlp_prefix_blocked_error_mask : 1; // bit [25] 575 UINT32 poisoned_tlp_egress_blocked_mask : 1; // bit [26] 576 UINT32 dmwr_request_egress_blocked_mask : 1; // bit [27] 577 UINT32 ide_check_failed_mask : 1; // bit [28] 578 UINT32 misrouted_ide_tlp_mask : 1; // bit [29] 579 UINT32 pcrc_check_failed_mask : 1; // bit [30] 580 UINT32 tlp_translation_egress_blocked_mask : 1; // bit [31] 581 } __attribute__((packed)) uncorrectable_error_mask_t; 582 583 static const char *severity_dict[] = { 584 "NonFatal", // 0x0 585 "Fatal", // 0x1 586 }; 587 588 static const size_t severity_dict_size = 589 sizeof(severity_dict) / sizeof(severity_dict[0]); 590 591 static const char *supported_dict[] = { 592 "NotSupported", // 0x0 593 "Supported", // 0x1 594 }; 595 596 static const size_t supported_dict_size = 597 sizeof(severity_dict) / sizeof(severity_dict[0]); 598 599 static const char *enabled_dict[] = { 600 "Disabled", // 0x0 601 "Enabled", // 0x1 602 }; 603 604 static const size_t enabled_dict_size = 605 sizeof(enabled_dict) / sizeof(enabled_dict[0]); 606 607 static const char *passing_dict[] = { 608 "Failed", // 0x0 609 "Passing", // 0x1 610 }; 611 612 static const size_t passing_dict_size = 613 sizeof(passing_dict) / sizeof(passing_dict[0]); 614 615 /* 616 * PCI Express Advanced Error Reporting Capability Structure 617 * CAPABILITY_ID = 0x01 618 * Uncorrectable Error Severity Register 619 * Offset: 0xC 620 */ 621 typedef struct { 622 UINT32 undefined : 1; // bits [0] 623 UINT32 rsvdz1 : 3; // bits [3:1] 624 UINT32 data_link_protocol_error_severity : 1; // bit [4] 625 UINT32 surprise_down_error_severity : 1; // bit [5] 626 UINT32 rsvdz2 : 6; // bits [11:6] 627 UINT32 poisoned_tlp_received_severity : 1; // bit [12] 628 UINT32 flow_control_protocol_error_severity : 1; // bit [13] 629 UINT32 completion_timeout_severity : 1; // bit [14] 630 UINT32 completer_abort_severity : 1; // bit [15] 631 UINT32 unexpected_completion_severity : 1; // bit [16] 632 UINT32 receiver_overflow_severity : 1; // bit [17] 633 UINT32 malformed_tlp_severity : 1; // bit [18] 634 UINT32 ecrc_error_severity : 1; // bit [19] 635 UINT32 unsupported_request_error_severity : 1; // bit [20] 636 UINT32 acs_violation_severity : 1; // bit [21] 637 UINT32 uncorrectable_internal_error_severity : 1; // bit [22] 638 UINT32 mc_blocked_tlp_severity : 1; // bit [23] 639 UINT32 atomicop_egress_blocked_severity : 1; // bit [24] 640 UINT32 tlp_prefix_blocked_error_severity : 1; // bit [25] 641 UINT32 poisoned_tlp_egress_blocked_severity : 1; // bit [26] 642 UINT32 dmwr_request_egress_blocked_severity : 1; // bit [27] 643 UINT32 ide_check_failed_severity : 1; // bit [28] 644 UINT32 misrouted_ide_tlp_severity : 1; // bit [29] 645 UINT32 pcrc_check_failed_severity : 1; // bit [30] 646 UINT32 tlp_translation_egress_blocked_severity : 1; // bit [31] 647 } __attribute__((packed)) uncorrectable_error_severity_t; 648 649 /* 650 * PCI Express Advanced Error Reporting Capability Structure 651 * CAPABILITY_ID = 0x01 652 * Correctable Error Status Register 653 * Offset: 0x10 654 */ 655 typedef struct { 656 UINT32 receiver_error_status : 1; // bit [0] 657 UINT32 rsvdz1 : 5; // bits [5:1] 658 UINT32 bad_tlp_status : 1; // bit [6] 659 UINT32 bad_dllp_status : 1; // bit [7] 660 UINT32 replay_num_rollover_status : 1; // bit [8] 661 UINT32 rsvdz2 : 3; // bits [11:9] 662 UINT32 replay_timer_timeout_status : 1; // bit [12] 663 UINT32 advisory_non_fatal_error_status : 1; // bit [13] 664 UINT32 corrected_internal_error_status : 1; // bit [14] 665 UINT32 header_log_overflow_status : 1; // bit [15] 666 UINT32 rsvdz3 : 16; // bits [31:16] 667 } __attribute__((packed)) correctable_error_status_t; 668 669 /* 670 * PCI Express Advanced Error Reporting Capability Structure 671 * CAPABILITY_ID = 0x01 672 * Correctable Error Mask Register 673 * Offset: 0x14 674 */ 675 typedef struct { 676 UINT32 receiver_error_mask : 1; // bit [0] 677 UINT32 rsvdz1 : 5; // bits [5:1] 678 UINT32 bad_tlp_mask : 1; // bit [6] 679 UINT32 bad_dllp_mask : 1; // bit [7] 680 UINT32 replay_num_rollover_mask : 1; // bit [8] 681 UINT32 rsvdz2 : 3; // bits [11:9] 682 UINT32 replay_timer_timeout_mask : 1; // bit [12] 683 UINT32 advisory_non_fatal_error_mask : 1; // bit [13] 684 UINT32 corrected_internal_error_mask : 1; // bit [14] 685 UINT32 header_log_overflow_mask : 1; // bit [15] 686 UINT32 rsvdz3 : 16; // bits [31:16] 687 } __attribute__((packed)) correctable_error_mask_t; 688 689 /* 690 * PCI Express Advanced Error Reporting Capability Structure 691 * CAPABILITY_ID = 0x01 692 * Advanced Error Capabilities and Control Register 693 * Offset: 0x18 694 */ 695 typedef struct { 696 UINT32 first_error_pointer : 5; // bits [4:0] 697 UINT32 ecrc_generation_capable : 1; // bit [5] 698 UINT32 ecrc_generation_enable : 1; // bit [6] 699 UINT32 ecrc_check_capable : 1; // bit [7] 700 UINT32 ecrc_check_enable : 1; // bit [8] 701 UINT32 multiple_header_recording_capable : 1; // bit [9] 702 UINT32 multiple_header_recording_enable : 1; // bit [10] 703 UINT32 tlp_prefix_log_present : 1; // bit [11] 704 UINT32 completion_timeout_prefix_header_log_capable : 1; // bit [12] 705 UINT32 header_log_size : 5; // bits [17:13] 706 UINT32 logged_tlp_was_flit_mode : 1; // bit [18] 707 UINT32 logged_tlp_size : 5; // bits [23:19] 708 UINT32 rsvdp : 8; // bits [31:24] 709 } __attribute__((packed)) advanced_error_capabilities_and_control_t; 710 711 /* 712 * PCI Express Advanced Error Reporting Capability Structure 713 * CAPABILITY_ID = 0x01 714 * Root Error Command Register 715 * Offset: 0x2C 716 */ 717 typedef struct { 718 UINT32 correctable_error_reporting_enable : 1; // bit [0] 719 UINT32 non_fatal_error_reporting_enable : 1; // bit [1] 720 UINT32 fatal_error_reporting_enable : 1; // bit [2] 721 UINT32 rsvdp : 29; // bits [31:3] 722 } __attribute__((packed)) root_error_command_t; 723 724 /* 725 * PCI Express Advanced Error Reporting Capability Structure 726 * CAPABILITY_ID = 0x01 727 * Root Error Status Register 728 * Offset: 0x30 729 */ 730 typedef struct { 731 UINT32 err_cor_received : 1; // bit [0] 732 UINT32 multiple_err_cor_received : 1; // bit [1] 733 UINT32 err_fatal_nonfatal_received : 1; // bit [2] 734 UINT32 multiple_err_fatal_nonfatal_received : 1; // bit [3] 735 UINT32 first_uncorrectable_fatal : 1; // bit [4] 736 UINT32 non_fatal_error_messages_received : 1; // bit [5] 737 UINT32 fatal_error_messages_received : 1; // bit [6] 738 UINT32 err_cor_subclass : 2; // bit [8:7] 739 UINT32 rsvdz : 16; // bit [9:26] 740 UINT32 advanced_error_interrupt_message_number : 5; // bits [31:27] 741 } __attribute__((packed)) root_error_status_t; 742 743 /* 744 * PCI Express Advanced Error Reporting Capability Structure 745 * CAPABILITY_ID = 0x01 746 * Error Source Identification Register 747 * Offset: 0x34 748 */ 749 typedef struct { 750 UINT32 err_cor_source_identification : 16; // bits [15:0] 751 UINT32 err_fatal_nonfatal_source_identification : 16; // bits [31:16] 752 } __attribute__((packed)) error_source_id_t; 753 754 typedef struct { 755 pcie_capability_header_t pcie_capability_header; 756 pcie_capabilities_t pcie_capabilities; 757 device_capabilities_t device_capabilities; 758 device_control_t device_control; 759 device_status_t device_status; 760 link_capabilities_t link_capabilities; 761 link_control_t link_control; 762 link_status_t link_status; 763 slot_capabilities_t slot_capabilities; 764 slot_control_t slot_control; 765 slot_status_t slot_status; 766 root_control_t root_control; 767 root_capabilities_t root_capabilities; 768 root_status_t root_status; 769 // "2" postfixed only valid when pcie_capabilities_fields.cap_version >= 2 770 device_capabilities2_t device_capabilities2; 771 device_control2_t device_control2; 772 device_status2_t device_status2; 773 link_capabilities2_t link_capabilities2; 774 link_control2_t link_control2; 775 link_status2_t link_status2; 776 slot_capabilities2_t slot_capabilities2; 777 slot_control2_t slot_control2; 778 slot_status2_t slot_status2; 779 } __attribute__((packed)) capability_registers; 780 781 typedef struct { 782 capability_header_t capability_header; 783 uncorrectable_error_status_t uncorrectable_error_status; 784 uncorrectable_error_mask_t uncorrectable_error_mask; 785 uncorrectable_error_severity_t uncorrectable_error_severity; 786 correctable_error_status_t correctable_error_status; 787 correctable_error_mask_t correctable_error_mask; 788 advanced_error_capabilities_and_control_t 789 advanced_error_capabilities_and_control; 790 UINT32 tlp_header[4]; 791 root_error_command_t root_error_command; 792 root_error_status_t root_error_status; 793 error_source_id_t error_source_id; 794 union { 795 struct { // Non-flit mode TLP prefix logs 796 UINT32 log[4]; 797 } non_flit_logs; 798 struct { // Flit mode TLP header logs 799 UINT32 header[10]; 800 } flit_tlp_header_logs; 801 } tlp_pfrefix; 802 } __attribute__((packed)) aer_info_registers; 803 804 #ifdef __cplusplus 805 } 806 #endif 807 808 #endif 809