xref: /openbmc/u-boot/drivers/ata/sata_sil.h (revision e8f80a5a)
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright (C) 2011 Freescale Semiconductor, Inc.
4  * Author: Tang Yuantian <b29983@freescale.com>
5  */
6 
7 #ifndef SATA_SIL3132_H
8 #define SATA_SIL3132_H
9 
10 #define READ_CMD	0
11 #define WRITE_CMD	1
12 
13 /*
14  * SATA device driver struct for each dev
15  */
16 struct sil_sata {
17 	char	name[12];
18 	void	*port;	/* the port base address */
19 	int		lba48;
20 	u16		pio;
21 	u16		mwdma;
22 	u16		udma;
23 	pci_dev_t devno;
24 	int		wcache;
25 	int		flush;
26 	int		flush_ext;
27 };
28 
29 /* sata info for each controller */
30 struct sata_info {
31 	ulong iobase[3];
32 	pci_dev_t devno;
33 	int portbase;
34 	int maxport;
35 };
36 
37 /*
38  * Scatter gather entry (SGE),MUST 8 bytes aligned
39  */
40 struct sil_sge {
41 	__le64 addr;
42 	__le32 cnt;
43 	__le32 flags;
44 } __attribute__ ((aligned(8), packed));
45 
46 /*
47  * Port request block, MUST 8 bytes aligned
48  */
49 struct sil_prb {
50 	__le16 ctrl;
51 	__le16 prot;
52 	__le32 rx_cnt;
53 	struct sata_fis_h2d fis;
54 } __attribute__ ((aligned(8), packed));
55 
56 struct sil_cmd_block {
57 	struct sil_prb prb;
58 	struct sil_sge sge;
59 };
60 
61 enum {
62 	HOST_SLOT_STAT		= 0x00, /* 32 bit slot stat * 4 */
63 	HOST_CTRL		= 0x40,
64 	HOST_IRQ_STAT		= 0x44,
65 	HOST_PHY_CFG		= 0x48,
66 	HOST_BIST_CTRL		= 0x50,
67 	HOST_BIST_PTRN		= 0x54,
68 	HOST_BIST_STAT		= 0x58,
69 	HOST_MEM_BIST_STAT	= 0x5c,
70 	HOST_FLASH_CMD		= 0x70,
71 		/* 8 bit regs */
72 	HOST_FLASH_DATA		= 0x74,
73 	HOST_TRANSITION_DETECT	= 0x75,
74 	HOST_GPIO_CTRL		= 0x76,
75 	HOST_I2C_ADDR		= 0x78, /* 32 bit */
76 	HOST_I2C_DATA		= 0x7c,
77 	HOST_I2C_XFER_CNT	= 0x7e,
78 	HOST_I2C_CTRL		= 0x7f,
79 
80 	/* HOST_SLOT_STAT bits */
81 	HOST_SSTAT_ATTN		= (1 << 31),
82 
83 	/* HOST_CTRL bits */
84 	HOST_CTRL_M66EN		= (1 << 16), /* M66EN PCI bus signal */
85 	HOST_CTRL_TRDY		= (1 << 17), /* latched PCI TRDY */
86 	HOST_CTRL_STOP		= (1 << 18), /* latched PCI STOP */
87 	HOST_CTRL_DEVSEL	= (1 << 19), /* latched PCI DEVSEL */
88 	HOST_CTRL_REQ64		= (1 << 20), /* latched PCI REQ64 */
89 	HOST_CTRL_GLOBAL_RST	= (1 << 31), /* global reset */
90 
91 	/*
92 	 * Port registers
93 	 * (8192 bytes @ +0x0000, +0x2000, +0x4000 and +0x6000 @ BAR2)
94 	 */
95 	PORT_REGS_SIZE		= 0x2000,
96 
97 	PORT_LRAM		= 0x0000, /* 31 LRAM slots and PMP regs */
98 	PORT_LRAM_SLOT_SZ	= 0x0080, /* 32 bytes PRB + 2 SGE, ACT... */
99 
100 	PORT_PMP		= 0x0f80, /* 8 bytes PMP * 16 (128 bytes) */
101 	PORT_PMP_STATUS		= 0x0000, /* port device status offset */
102 	PORT_PMP_QACTIVE	= 0x0004, /* port device QActive offset */
103 	PORT_PMP_SIZE		= 0x0008, /* 8 bytes per PMP */
104 
105 	/* 32 bit regs */
106 	PORT_CTRL_STAT		= 0x1000, /* write: ctrl-set, read: stat */
107 	PORT_CTRL_CLR		= 0x1004, /* write: ctrl-clear */
108 	PORT_IRQ_STAT		= 0x1008, /* high: status, low: interrupt */
109 	PORT_IRQ_ENABLE_SET	= 0x1010, /* write: enable-set */
110 	PORT_IRQ_ENABLE_CLR	= 0x1014, /* write: enable-clear */
111 	PORT_ACTIVATE_UPPER_ADDR = 0x101c,
112 	PORT_EXEC_FIFO		= 0x1020, /* command execution fifo */
113 	PORT_CMD_ERR		= 0x1024, /* command error number */
114 	PORT_FIS_CFG		= 0x1028,
115 	PORT_FIFO_THRES		= 0x102c,
116 
117 	/* 16 bit regs */
118 	PORT_DECODE_ERR_CNT	= 0x1040,
119 	PORT_DECODE_ERR_THRESH	= 0x1042,
120 	PORT_CRC_ERR_CNT	= 0x1044,
121 	PORT_CRC_ERR_THRESH	= 0x1046,
122 	PORT_HSHK_ERR_CNT	= 0x1048,
123 	PORT_HSHK_ERR_THRESH	= 0x104a,
124 
125 	/* 32 bit regs */
126 	PORT_PHY_CFG		= 0x1050,
127 	PORT_SLOT_STAT		= 0x1800,
128 	PORT_CMD_ACTIVATE	= 0x1c00, /* 64 bit cmd activate * 31 */
129 	PORT_CONTEXT		= 0x1e04,
130 	PORT_EXEC_DIAG		= 0x1e00, /* 32bit exec diag * 16 */
131 	PORT_PSD_DIAG		= 0x1e40, /* 32bit psd diag * 16 */
132 	PORT_SCONTROL		= 0x1f00,
133 	PORT_SSTATUS		= 0x1f04,
134 	PORT_SERROR		= 0x1f08,
135 	PORT_SACTIVE		= 0x1f0c,
136 
137 	/* PORT_CTRL_STAT bits */
138 	PORT_CS_PORT_RST	= (1 << 0), /* port reset */
139 	PORT_CS_DEV_RST		= (1 << 1), /* device reset */
140 	PORT_CS_INIT		= (1 << 2), /* port initialize */
141 	PORT_CS_IRQ_WOC		= (1 << 3), /* interrupt write one to clear */
142 	PORT_CS_CDB16		= (1 << 5), /* 0=12b cdb, 1=16b cdb */
143 	PORT_CS_PMP_RESUME	= (1 << 6), /* PMP resume */
144 	PORT_CS_32BIT_ACTV	= (1 << 10), /* 32-bit activation */
145 	PORT_CS_PMP_EN		= (1 << 13), /* port multiplier enable */
146 	PORT_CS_RDY		= (1 << 31), /* port ready to accept commands */
147 
148 	/* PORT_IRQ_STAT/ENABLE_SET/CLR */
149 	/* bits[11:0] are masked */
150 	PORT_IRQ_COMPLETE	= (1 << 0), /* command(s) completed */
151 	PORT_IRQ_ERROR		= (1 << 1), /* command execution error */
152 	PORT_IRQ_PORTRDY_CHG	= (1 << 2), /* port ready change */
153 	PORT_IRQ_PWR_CHG	= (1 << 3), /* power management change */
154 	PORT_IRQ_PHYRDY_CHG	= (1 << 4), /* PHY ready change */
155 	PORT_IRQ_COMWAKE	= (1 << 5), /* COMWAKE received */
156 	PORT_IRQ_UNK_FIS	= (1 << 6), /* unknown FIS received */
157 	PORT_IRQ_DEV_XCHG	= (1 << 7), /* device exchanged */
158 	PORT_IRQ_8B10B		= (1 << 8), /* 8b/10b decode error threshold */
159 	PORT_IRQ_CRC		= (1 << 9), /* CRC error threshold */
160 	PORT_IRQ_HANDSHAKE	= (1 << 10), /* handshake error threshold */
161 	PORT_IRQ_SDB_NOTIFY	= (1 << 11), /* SDB notify received */
162 
163 	DEF_PORT_IRQ		= PORT_IRQ_COMPLETE | PORT_IRQ_ERROR |
164 				  PORT_IRQ_PHYRDY_CHG | PORT_IRQ_DEV_XCHG |
165 				  PORT_IRQ_UNK_FIS | PORT_IRQ_SDB_NOTIFY,
166 
167 	/* bits[27:16] are unmasked (raw) */
168 	PORT_IRQ_RAW_SHIFT	= 16,
169 	PORT_IRQ_MASKED_MASK	= 0x7ff,
170 	PORT_IRQ_RAW_MASK	= (0x7ff << PORT_IRQ_RAW_SHIFT),
171 
172 	/* ENABLE_SET/CLR specific, intr steering - 2 bit field */
173 	PORT_IRQ_STEER_SHIFT	= 30,
174 	PORT_IRQ_STEER_MASK	= (3 << PORT_IRQ_STEER_SHIFT),
175 
176 	/* PORT_CMD_ERR constants */
177 	PORT_CERR_DEV		= 1, /* Error bit in D2H Register FIS */
178 	PORT_CERR_SDB		= 2, /* Error bit in SDB FIS */
179 	PORT_CERR_DATA		= 3, /* Error in data FIS not detected by dev */
180 	PORT_CERR_SEND		= 4, /* Initial cmd FIS transmission failure */
181 	PORT_CERR_INCONSISTENT	= 5, /* Protocol mismatch */
182 	PORT_CERR_DIRECTION	= 6, /* Data direction mismatch */
183 	PORT_CERR_UNDERRUN	= 7, /* Ran out of SGEs while writing */
184 	PORT_CERR_OVERRUN	= 8, /* Ran out of SGEs while reading */
185 
186 	/* bits of PRB control field */
187 	PRB_CTRL_PROTOCOL	= (1 << 0), /* override def. ATA protocol */
188 	PRB_CTRL_PACKET_READ	= (1 << 4), /* PACKET cmd read */
189 	PRB_CTRL_PACKET_WRITE	= (1 << 5), /* PACKET cmd write */
190 	PRB_CTRL_NIEN		= (1 << 6), /* Mask completion irq */
191 	PRB_CTRL_SRST		= (1 << 7), /* Soft reset request (ign BSY?) */
192 
193 	/* PRB protocol field */
194 	PRB_PROT_PACKET		= (1 << 0),
195 	PRB_PROT_TCQ		= (1 << 1),
196 	PRB_PROT_NCQ		= (1 << 2),
197 	PRB_PROT_READ		= (1 << 3),
198 	PRB_PROT_WRITE		= (1 << 4),
199 	PRB_PROT_TRANSPARENT	= (1 << 5),
200 
201 	/*
202 	 * Other constants
203 	 */
204 	SGE_TRM			= (1 << 31), /* Last SGE in chain */
205 	SGE_LNK			= (1 << 30), /* linked list
206 						Points to SGT, not SGE */
207 	SGE_DRD			= (1 << 29), /* discard data read (/dev/null)
208 						data address ignored */
209 
210 	CMD_ERR		= 0x21,
211 };
212 
213 #endif
214