xref: /openbmc/linux/drivers/rtc/rtc-pxa.c (revision 48144c28)
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * Real Time Clock interface for XScale PXA27x and PXA3xx
4  *
5  * Copyright (C) 2008 Robert Jarzmik
6  */
7 
8 #include <linux/init.h>
9 #include <linux/platform_device.h>
10 #include <linux/module.h>
11 #include <linux/rtc.h>
12 #include <linux/seq_file.h>
13 #include <linux/interrupt.h>
14 #include <linux/io.h>
15 #include <linux/slab.h>
16 #include <linux/of.h>
17 
18 #include "rtc-sa1100.h"
19 
20 #define RTC_DEF_DIVIDER		(32768 - 1)
21 #define RTC_DEF_TRIM		0
22 #define MAXFREQ_PERIODIC	1000
23 
24 /*
25  * PXA Registers and bits definitions
26  */
27 #define RTSR_PICE	(1 << 15)	/* Periodic interrupt count enable */
28 #define RTSR_PIALE	(1 << 14)	/* Periodic interrupt Alarm enable */
29 #define RTSR_PIAL	(1 << 13)	/* Periodic interrupt detected */
30 #define RTSR_SWALE2	(1 << 11)	/* RTC stopwatch alarm2 enable */
31 #define RTSR_SWAL2	(1 << 10)	/* RTC stopwatch alarm2 detected */
32 #define RTSR_SWALE1	(1 << 9)	/* RTC stopwatch alarm1 enable */
33 #define RTSR_SWAL1	(1 << 8)	/* RTC stopwatch alarm1 detected */
34 #define RTSR_RDALE2	(1 << 7)	/* RTC alarm2 enable */
35 #define RTSR_RDAL2	(1 << 6)	/* RTC alarm2 detected */
36 #define RTSR_RDALE1	(1 << 5)	/* RTC alarm1 enable */
37 #define RTSR_RDAL1	(1 << 4)	/* RTC alarm1 detected */
38 #define RTSR_HZE	(1 << 3)	/* HZ interrupt enable */
39 #define RTSR_ALE	(1 << 2)	/* RTC alarm interrupt enable */
40 #define RTSR_HZ		(1 << 1)	/* HZ rising-edge detected */
41 #define RTSR_AL		(1 << 0)	/* RTC alarm detected */
42 #define RTSR_TRIG_MASK	(RTSR_AL | RTSR_HZ | RTSR_RDAL1 | RTSR_RDAL2\
43 			 | RTSR_SWAL1 | RTSR_SWAL2)
44 #define RYxR_YEAR_S	9
45 #define RYxR_YEAR_MASK	(0xfff << RYxR_YEAR_S)
46 #define RYxR_MONTH_S	5
47 #define RYxR_MONTH_MASK	(0xf << RYxR_MONTH_S)
48 #define RYxR_DAY_MASK	0x1f
49 #define RDxR_WOM_S     20
50 #define RDxR_WOM_MASK  (0x7 << RDxR_WOM_S)
51 #define RDxR_DOW_S     17
52 #define RDxR_DOW_MASK  (0x7 << RDxR_DOW_S)
53 #define RDxR_HOUR_S	12
54 #define RDxR_HOUR_MASK	(0x1f << RDxR_HOUR_S)
55 #define RDxR_MIN_S	6
56 #define RDxR_MIN_MASK	(0x3f << RDxR_MIN_S)
57 #define RDxR_SEC_MASK	0x3f
58 
59 #define RTSR		0x08
60 #define RTTR		0x0c
61 #define RDCR		0x10
62 #define RYCR		0x14
63 #define RDAR1		0x18
64 #define RYAR1		0x1c
65 #define RTCPICR		0x34
66 #define PIAR		0x38
67 
68 #define rtc_readl(pxa_rtc, reg)	\
69 	__raw_readl((pxa_rtc)->base + (reg))
70 #define rtc_writel(pxa_rtc, reg, value)	\
71 	__raw_writel((value), (pxa_rtc)->base + (reg))
72 
73 struct pxa_rtc {
74 	struct sa1100_rtc sa1100_rtc;
75 	struct resource	*ress;
76 	void __iomem		*base;
77 	struct rtc_device	*rtc;
78 	spinlock_t		lock;		/* Protects this structure */
79 };
80 
81 
ryxr_calc(struct rtc_time * tm)82 static u32 ryxr_calc(struct rtc_time *tm)
83 {
84 	return ((tm->tm_year + 1900) << RYxR_YEAR_S)
85 		| ((tm->tm_mon + 1) << RYxR_MONTH_S)
86 		| tm->tm_mday;
87 }
88 
rdxr_calc(struct rtc_time * tm)89 static u32 rdxr_calc(struct rtc_time *tm)
90 {
91 	return ((((tm->tm_mday + 6) / 7) << RDxR_WOM_S) & RDxR_WOM_MASK)
92 		| (((tm->tm_wday + 1) << RDxR_DOW_S) & RDxR_DOW_MASK)
93 		| (tm->tm_hour << RDxR_HOUR_S)
94 		| (tm->tm_min << RDxR_MIN_S)
95 		| tm->tm_sec;
96 }
97 
tm_calc(u32 rycr,u32 rdcr,struct rtc_time * tm)98 static void tm_calc(u32 rycr, u32 rdcr, struct rtc_time *tm)
99 {
100 	tm->tm_year = ((rycr & RYxR_YEAR_MASK) >> RYxR_YEAR_S) - 1900;
101 	tm->tm_mon = (((rycr & RYxR_MONTH_MASK) >> RYxR_MONTH_S)) - 1;
102 	tm->tm_mday = (rycr & RYxR_DAY_MASK);
103 	tm->tm_wday = ((rycr & RDxR_DOW_MASK) >> RDxR_DOW_S) - 1;
104 	tm->tm_hour = (rdcr & RDxR_HOUR_MASK) >> RDxR_HOUR_S;
105 	tm->tm_min = (rdcr & RDxR_MIN_MASK) >> RDxR_MIN_S;
106 	tm->tm_sec = rdcr & RDxR_SEC_MASK;
107 }
108 
rtsr_clear_bits(struct pxa_rtc * pxa_rtc,u32 mask)109 static void rtsr_clear_bits(struct pxa_rtc *pxa_rtc, u32 mask)
110 {
111 	u32 rtsr;
112 
113 	rtsr = rtc_readl(pxa_rtc, RTSR);
114 	rtsr &= ~RTSR_TRIG_MASK;
115 	rtsr &= ~mask;
116 	rtc_writel(pxa_rtc, RTSR, rtsr);
117 }
118 
rtsr_set_bits(struct pxa_rtc * pxa_rtc,u32 mask)119 static void rtsr_set_bits(struct pxa_rtc *pxa_rtc, u32 mask)
120 {
121 	u32 rtsr;
122 
123 	rtsr = rtc_readl(pxa_rtc, RTSR);
124 	rtsr &= ~RTSR_TRIG_MASK;
125 	rtsr |= mask;
126 	rtc_writel(pxa_rtc, RTSR, rtsr);
127 }
128 
pxa_rtc_irq(int irq,void * dev_id)129 static irqreturn_t pxa_rtc_irq(int irq, void *dev_id)
130 {
131 	struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev_id);
132 	u32 rtsr;
133 	unsigned long events = 0;
134 
135 	spin_lock(&pxa_rtc->lock);
136 
137 	/* clear interrupt sources */
138 	rtsr = rtc_readl(pxa_rtc, RTSR);
139 	rtc_writel(pxa_rtc, RTSR, rtsr);
140 
141 	/* temporary disable rtc interrupts */
142 	rtsr_clear_bits(pxa_rtc, RTSR_RDALE1 | RTSR_PIALE | RTSR_HZE);
143 
144 	/* clear alarm interrupt if it has occurred */
145 	if (rtsr & RTSR_RDAL1)
146 		rtsr &= ~RTSR_RDALE1;
147 
148 	/* update irq data & counter */
149 	if (rtsr & RTSR_RDAL1)
150 		events |= RTC_AF | RTC_IRQF;
151 	if (rtsr & RTSR_HZ)
152 		events |= RTC_UF | RTC_IRQF;
153 	if (rtsr & RTSR_PIAL)
154 		events |= RTC_PF | RTC_IRQF;
155 
156 	rtc_update_irq(pxa_rtc->rtc, 1, events);
157 
158 	/* enable back rtc interrupts */
159 	rtc_writel(pxa_rtc, RTSR, rtsr & ~RTSR_TRIG_MASK);
160 
161 	spin_unlock(&pxa_rtc->lock);
162 	return IRQ_HANDLED;
163 }
164 
pxa_rtc_open(struct device * dev)165 static int pxa_rtc_open(struct device *dev)
166 {
167 	struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
168 	int ret;
169 
170 	ret = request_irq(pxa_rtc->sa1100_rtc.irq_1hz, pxa_rtc_irq, 0,
171 			  "rtc 1Hz", dev);
172 	if (ret < 0) {
173 		dev_err(dev, "can't get irq %i, err %d\n",
174 			pxa_rtc->sa1100_rtc.irq_1hz, ret);
175 		goto err_irq_1Hz;
176 	}
177 	ret = request_irq(pxa_rtc->sa1100_rtc.irq_alarm, pxa_rtc_irq, 0,
178 			  "rtc Alrm", dev);
179 	if (ret < 0) {
180 		dev_err(dev, "can't get irq %i, err %d\n",
181 			pxa_rtc->sa1100_rtc.irq_alarm, ret);
182 		goto err_irq_Alrm;
183 	}
184 
185 	return 0;
186 
187 err_irq_Alrm:
188 	free_irq(pxa_rtc->sa1100_rtc.irq_1hz, dev);
189 err_irq_1Hz:
190 	return ret;
191 }
192 
pxa_rtc_release(struct device * dev)193 static void pxa_rtc_release(struct device *dev)
194 {
195 	struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
196 
197 	spin_lock_irq(&pxa_rtc->lock);
198 	rtsr_clear_bits(pxa_rtc, RTSR_PIALE | RTSR_RDALE1 | RTSR_HZE);
199 	spin_unlock_irq(&pxa_rtc->lock);
200 
201 	free_irq(pxa_rtc->sa1100_rtc.irq_1hz, dev);
202 	free_irq(pxa_rtc->sa1100_rtc.irq_alarm, dev);
203 }
204 
pxa_alarm_irq_enable(struct device * dev,unsigned int enabled)205 static int pxa_alarm_irq_enable(struct device *dev, unsigned int enabled)
206 {
207 	struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
208 
209 	spin_lock_irq(&pxa_rtc->lock);
210 
211 	if (enabled)
212 		rtsr_set_bits(pxa_rtc, RTSR_RDALE1);
213 	else
214 		rtsr_clear_bits(pxa_rtc, RTSR_RDALE1);
215 
216 	spin_unlock_irq(&pxa_rtc->lock);
217 	return 0;
218 }
219 
pxa_rtc_read_time(struct device * dev,struct rtc_time * tm)220 static int pxa_rtc_read_time(struct device *dev, struct rtc_time *tm)
221 {
222 	struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
223 	u32 rycr, rdcr;
224 
225 	rycr = rtc_readl(pxa_rtc, RYCR);
226 	rdcr = rtc_readl(pxa_rtc, RDCR);
227 
228 	tm_calc(rycr, rdcr, tm);
229 	return 0;
230 }
231 
pxa_rtc_set_time(struct device * dev,struct rtc_time * tm)232 static int pxa_rtc_set_time(struct device *dev, struct rtc_time *tm)
233 {
234 	struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
235 
236 	rtc_writel(pxa_rtc, RYCR, ryxr_calc(tm));
237 	rtc_writel(pxa_rtc, RDCR, rdxr_calc(tm));
238 
239 	return 0;
240 }
241 
pxa_rtc_read_alarm(struct device * dev,struct rtc_wkalrm * alrm)242 static int pxa_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
243 {
244 	struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
245 	u32 rtsr, ryar, rdar;
246 
247 	ryar = rtc_readl(pxa_rtc, RYAR1);
248 	rdar = rtc_readl(pxa_rtc, RDAR1);
249 	tm_calc(ryar, rdar, &alrm->time);
250 
251 	rtsr = rtc_readl(pxa_rtc, RTSR);
252 	alrm->enabled = (rtsr & RTSR_RDALE1) ? 1 : 0;
253 	alrm->pending = (rtsr & RTSR_RDAL1) ? 1 : 0;
254 	return 0;
255 }
256 
pxa_rtc_set_alarm(struct device * dev,struct rtc_wkalrm * alrm)257 static int pxa_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
258 {
259 	struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
260 	u32 rtsr;
261 
262 	spin_lock_irq(&pxa_rtc->lock);
263 
264 	rtc_writel(pxa_rtc, RYAR1, ryxr_calc(&alrm->time));
265 	rtc_writel(pxa_rtc, RDAR1, rdxr_calc(&alrm->time));
266 
267 	rtsr = rtc_readl(pxa_rtc, RTSR);
268 	if (alrm->enabled)
269 		rtsr |= RTSR_RDALE1;
270 	else
271 		rtsr &= ~RTSR_RDALE1;
272 	rtc_writel(pxa_rtc, RTSR, rtsr);
273 
274 	spin_unlock_irq(&pxa_rtc->lock);
275 
276 	return 0;
277 }
278 
pxa_rtc_proc(struct device * dev,struct seq_file * seq)279 static int pxa_rtc_proc(struct device *dev, struct seq_file *seq)
280 {
281 	struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
282 
283 	seq_printf(seq, "trim/divider\t: 0x%08x\n", rtc_readl(pxa_rtc, RTTR));
284 	seq_printf(seq, "update_IRQ\t: %s\n",
285 		   (rtc_readl(pxa_rtc, RTSR) & RTSR_HZE) ? "yes" : "no");
286 	seq_printf(seq, "periodic_IRQ\t: %s\n",
287 		   (rtc_readl(pxa_rtc, RTSR) & RTSR_PIALE) ? "yes" : "no");
288 	seq_printf(seq, "periodic_freq\t: %u\n", rtc_readl(pxa_rtc, PIAR));
289 
290 	return 0;
291 }
292 
293 static const struct rtc_class_ops pxa_rtc_ops = {
294 	.read_time = pxa_rtc_read_time,
295 	.set_time = pxa_rtc_set_time,
296 	.read_alarm = pxa_rtc_read_alarm,
297 	.set_alarm = pxa_rtc_set_alarm,
298 	.alarm_irq_enable = pxa_alarm_irq_enable,
299 	.proc = pxa_rtc_proc,
300 };
301 
pxa_rtc_probe(struct platform_device * pdev)302 static int __init pxa_rtc_probe(struct platform_device *pdev)
303 {
304 	struct device *dev = &pdev->dev;
305 	struct pxa_rtc *pxa_rtc;
306 	struct sa1100_rtc *sa1100_rtc;
307 	int ret;
308 
309 	pxa_rtc = devm_kzalloc(dev, sizeof(*pxa_rtc), GFP_KERNEL);
310 	if (!pxa_rtc)
311 		return -ENOMEM;
312 	sa1100_rtc = &pxa_rtc->sa1100_rtc;
313 
314 	spin_lock_init(&pxa_rtc->lock);
315 	platform_set_drvdata(pdev, pxa_rtc);
316 
317 	pxa_rtc->ress = platform_get_resource(pdev, IORESOURCE_MEM, 0);
318 	if (!pxa_rtc->ress) {
319 		dev_err(dev, "No I/O memory resource defined\n");
320 		return -ENXIO;
321 	}
322 
323 	sa1100_rtc->irq_1hz = platform_get_irq(pdev, 0);
324 	if (sa1100_rtc->irq_1hz < 0)
325 		return -ENXIO;
326 	sa1100_rtc->irq_alarm = platform_get_irq(pdev, 1);
327 	if (sa1100_rtc->irq_alarm < 0)
328 		return -ENXIO;
329 
330 	sa1100_rtc->rtc = devm_rtc_allocate_device(&pdev->dev);
331 	if (IS_ERR(sa1100_rtc->rtc))
332 		return PTR_ERR(sa1100_rtc->rtc);
333 
334 	pxa_rtc->base = devm_ioremap(dev, pxa_rtc->ress->start,
335 				resource_size(pxa_rtc->ress));
336 	if (!pxa_rtc->base) {
337 		dev_err(dev, "Unable to map pxa RTC I/O memory\n");
338 		return -ENOMEM;
339 	}
340 
341 	pxa_rtc_open(dev);
342 
343 	sa1100_rtc->rcnr = pxa_rtc->base + 0x0;
344 	sa1100_rtc->rtsr = pxa_rtc->base + 0x8;
345 	sa1100_rtc->rtar = pxa_rtc->base + 0x4;
346 	sa1100_rtc->rttr = pxa_rtc->base + 0xc;
347 	ret = sa1100_rtc_init(pdev, sa1100_rtc);
348 	if (ret) {
349 		dev_err(dev, "Unable to init SA1100 RTC sub-device\n");
350 		return ret;
351 	}
352 
353 	rtsr_clear_bits(pxa_rtc, RTSR_PIALE | RTSR_RDALE1 | RTSR_HZE);
354 
355 	pxa_rtc->rtc = devm_rtc_device_register(&pdev->dev, "pxa-rtc",
356 						&pxa_rtc_ops, THIS_MODULE);
357 	if (IS_ERR(pxa_rtc->rtc)) {
358 		ret = PTR_ERR(pxa_rtc->rtc);
359 		dev_err(dev, "Failed to register RTC device -> %d\n", ret);
360 		return ret;
361 	}
362 
363 	device_init_wakeup(dev, 1);
364 
365 	return 0;
366 }
367 
pxa_rtc_remove(struct platform_device * pdev)368 static int __exit pxa_rtc_remove(struct platform_device *pdev)
369 {
370 	struct device *dev = &pdev->dev;
371 
372 	pxa_rtc_release(dev);
373 	return 0;
374 }
375 
376 #ifdef CONFIG_OF
377 static const struct of_device_id pxa_rtc_dt_ids[] = {
378 	{ .compatible = "marvell,pxa-rtc" },
379 	{}
380 };
381 MODULE_DEVICE_TABLE(of, pxa_rtc_dt_ids);
382 #endif
383 
384 #ifdef CONFIG_PM_SLEEP
pxa_rtc_suspend(struct device * dev)385 static int pxa_rtc_suspend(struct device *dev)
386 {
387 	struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
388 
389 	if (device_may_wakeup(dev))
390 		enable_irq_wake(pxa_rtc->sa1100_rtc.irq_alarm);
391 	return 0;
392 }
393 
pxa_rtc_resume(struct device * dev)394 static int pxa_rtc_resume(struct device *dev)
395 {
396 	struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
397 
398 	if (device_may_wakeup(dev))
399 		disable_irq_wake(pxa_rtc->sa1100_rtc.irq_alarm);
400 	return 0;
401 }
402 #endif
403 
404 static SIMPLE_DEV_PM_OPS(pxa_rtc_pm_ops, pxa_rtc_suspend, pxa_rtc_resume);
405 
406 static struct platform_driver pxa_rtc_driver = {
407 	.remove		= __exit_p(pxa_rtc_remove),
408 	.driver		= {
409 		.name	= "pxa-rtc",
410 		.of_match_table = of_match_ptr(pxa_rtc_dt_ids),
411 		.pm	= &pxa_rtc_pm_ops,
412 	},
413 };
414 
415 module_platform_driver_probe(pxa_rtc_driver, pxa_rtc_probe);
416 
417 MODULE_AUTHOR("Robert Jarzmik <robert.jarzmik@free.fr>");
418 MODULE_DESCRIPTION("PXA27x/PXA3xx Realtime Clock Driver (RTC)");
419 MODULE_LICENSE("GPL");
420 MODULE_ALIAS("platform:pxa-rtc");
421