1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (C) 2019 Linaro Ltd
4  */
5 
6 #include <dt-bindings/interconnect/qcom,qcs404.h>
7 #include <linux/device.h>
8 #include <linux/interconnect-provider.h>
9 #include <linux/io.h>
10 #include <linux/module.h>
11 #include <linux/mod_devicetable.h>
12 #include <linux/platform_device.h>
13 
14 
15 #include "icc-rpm.h"
16 
17 enum {
18 	QCS404_MASTER_AMPSS_M0 = 1,
19 	QCS404_MASTER_GRAPHICS_3D,
20 	QCS404_MASTER_MDP_PORT0,
21 	QCS404_SNOC_BIMC_1_MAS,
22 	QCS404_MASTER_TCU_0,
23 	QCS404_MASTER_SPDM,
24 	QCS404_MASTER_BLSP_1,
25 	QCS404_MASTER_BLSP_2,
26 	QCS404_MASTER_XM_USB_HS1,
27 	QCS404_MASTER_CRYPTO_CORE0,
28 	QCS404_MASTER_SDCC_1,
29 	QCS404_MASTER_SDCC_2,
30 	QCS404_SNOC_PNOC_MAS,
31 	QCS404_MASTER_QPIC,
32 	QCS404_MASTER_QDSS_BAM,
33 	QCS404_BIMC_SNOC_MAS,
34 	QCS404_PNOC_SNOC_MAS,
35 	QCS404_MASTER_QDSS_ETR,
36 	QCS404_MASTER_EMAC,
37 	QCS404_MASTER_PCIE,
38 	QCS404_MASTER_USB3,
39 	QCS404_PNOC_INT_0,
40 	QCS404_PNOC_INT_2,
41 	QCS404_PNOC_INT_3,
42 	QCS404_PNOC_SLV_0,
43 	QCS404_PNOC_SLV_1,
44 	QCS404_PNOC_SLV_2,
45 	QCS404_PNOC_SLV_3,
46 	QCS404_PNOC_SLV_4,
47 	QCS404_PNOC_SLV_6,
48 	QCS404_PNOC_SLV_7,
49 	QCS404_PNOC_SLV_8,
50 	QCS404_PNOC_SLV_9,
51 	QCS404_PNOC_SLV_10,
52 	QCS404_PNOC_SLV_11,
53 	QCS404_SNOC_QDSS_INT,
54 	QCS404_SNOC_INT_0,
55 	QCS404_SNOC_INT_1,
56 	QCS404_SNOC_INT_2,
57 	QCS404_SLAVE_EBI_CH0,
58 	QCS404_BIMC_SNOC_SLV,
59 	QCS404_SLAVE_SPDM_WRAPPER,
60 	QCS404_SLAVE_PDM,
61 	QCS404_SLAVE_PRNG,
62 	QCS404_SLAVE_TCSR,
63 	QCS404_SLAVE_SNOC_CFG,
64 	QCS404_SLAVE_MESSAGE_RAM,
65 	QCS404_SLAVE_DISPLAY_CFG,
66 	QCS404_SLAVE_GRAPHICS_3D_CFG,
67 	QCS404_SLAVE_BLSP_1,
68 	QCS404_SLAVE_TLMM_NORTH,
69 	QCS404_SLAVE_PCIE_1,
70 	QCS404_SLAVE_EMAC_CFG,
71 	QCS404_SLAVE_BLSP_2,
72 	QCS404_SLAVE_TLMM_EAST,
73 	QCS404_SLAVE_TCU,
74 	QCS404_SLAVE_PMIC_ARB,
75 	QCS404_SLAVE_SDCC_1,
76 	QCS404_SLAVE_SDCC_2,
77 	QCS404_SLAVE_TLMM_SOUTH,
78 	QCS404_SLAVE_USB_HS,
79 	QCS404_SLAVE_USB3,
80 	QCS404_SLAVE_CRYPTO_0_CFG,
81 	QCS404_PNOC_SNOC_SLV,
82 	QCS404_SLAVE_APPSS,
83 	QCS404_SLAVE_WCSS,
84 	QCS404_SNOC_BIMC_1_SLV,
85 	QCS404_SLAVE_OCIMEM,
86 	QCS404_SNOC_PNOC_SLV,
87 	QCS404_SLAVE_QDSS_STM,
88 	QCS404_SLAVE_CATS_128,
89 	QCS404_SLAVE_OCMEM_64,
90 	QCS404_SLAVE_LPASS,
91 };
92 
93 static const u16 mas_apps_proc_links[] = {
94 	QCS404_SLAVE_EBI_CH0,
95 	QCS404_BIMC_SNOC_SLV
96 };
97 
98 static struct qcom_icc_node mas_apps_proc = {
99 	.name = "mas_apps_proc",
100 	.id = QCS404_MASTER_AMPSS_M0,
101 	.buswidth = 8,
102 	.mas_rpm_id = 0,
103 	.slv_rpm_id = -1,
104 	.num_links = ARRAY_SIZE(mas_apps_proc_links),
105 	.links = mas_apps_proc_links,
106 };
107 
108 static const u16 mas_oxili_links[] = {
109 	QCS404_SLAVE_EBI_CH0,
110 	QCS404_BIMC_SNOC_SLV
111 };
112 
113 static struct qcom_icc_node mas_oxili = {
114 	.name = "mas_oxili",
115 	.id = QCS404_MASTER_GRAPHICS_3D,
116 	.buswidth = 8,
117 	.mas_rpm_id = -1,
118 	.slv_rpm_id = -1,
119 	.num_links = ARRAY_SIZE(mas_oxili_links),
120 	.links = mas_oxili_links,
121 };
122 
123 static const u16 mas_mdp_links[] = {
124 	QCS404_SLAVE_EBI_CH0,
125 	QCS404_BIMC_SNOC_SLV
126 };
127 
128 static struct qcom_icc_node mas_mdp = {
129 	.name = "mas_mdp",
130 	.id = QCS404_MASTER_MDP_PORT0,
131 	.buswidth = 8,
132 	.mas_rpm_id = -1,
133 	.slv_rpm_id = -1,
134 	.num_links = ARRAY_SIZE(mas_mdp_links),
135 	.links = mas_mdp_links,
136 };
137 
138 static const u16 mas_snoc_bimc_1_links[] = {
139 	QCS404_SLAVE_EBI_CH0
140 };
141 
142 static struct qcom_icc_node mas_snoc_bimc_1 = {
143 	.name = "mas_snoc_bimc_1",
144 	.id = QCS404_SNOC_BIMC_1_MAS,
145 	.buswidth = 8,
146 	.mas_rpm_id = 76,
147 	.slv_rpm_id = -1,
148 	.num_links = ARRAY_SIZE(mas_snoc_bimc_1_links),
149 	.links = mas_snoc_bimc_1_links,
150 };
151 
152 static const u16 mas_tcu_0_links[] = {
153 	QCS404_SLAVE_EBI_CH0,
154 	QCS404_BIMC_SNOC_SLV
155 };
156 
157 static struct qcom_icc_node mas_tcu_0 = {
158 	.name = "mas_tcu_0",
159 	.id = QCS404_MASTER_TCU_0,
160 	.buswidth = 8,
161 	.mas_rpm_id = -1,
162 	.slv_rpm_id = -1,
163 	.num_links = ARRAY_SIZE(mas_tcu_0_links),
164 	.links = mas_tcu_0_links,
165 };
166 
167 static const u16 mas_spdm_links[] = {
168 	QCS404_PNOC_INT_3
169 };
170 
171 static struct qcom_icc_node mas_spdm = {
172 	.name = "mas_spdm",
173 	.id = QCS404_MASTER_SPDM,
174 	.buswidth = 4,
175 	.mas_rpm_id = -1,
176 	.slv_rpm_id = -1,
177 	.num_links = ARRAY_SIZE(mas_spdm_links),
178 	.links = mas_spdm_links,
179 };
180 
181 static const u16 mas_blsp_1_links[] = {
182 	QCS404_PNOC_INT_3
183 };
184 
185 static struct qcom_icc_node mas_blsp_1 = {
186 	.name = "mas_blsp_1",
187 	.id = QCS404_MASTER_BLSP_1,
188 	.buswidth = 4,
189 	.mas_rpm_id = 41,
190 	.slv_rpm_id = -1,
191 	.num_links = ARRAY_SIZE(mas_blsp_1_links),
192 	.links = mas_blsp_1_links,
193 };
194 
195 static const u16 mas_blsp_2_links[] = {
196 	QCS404_PNOC_INT_3
197 };
198 
199 static struct qcom_icc_node mas_blsp_2 = {
200 	.name = "mas_blsp_2",
201 	.id = QCS404_MASTER_BLSP_2,
202 	.buswidth = 4,
203 	.mas_rpm_id = 39,
204 	.slv_rpm_id = -1,
205 	.num_links = ARRAY_SIZE(mas_blsp_2_links),
206 	.links = mas_blsp_2_links,
207 };
208 
209 static const u16 mas_xi_usb_hs1_links[] = {
210 	QCS404_PNOC_INT_0
211 };
212 
213 static struct qcom_icc_node mas_xi_usb_hs1 = {
214 	.name = "mas_xi_usb_hs1",
215 	.id = QCS404_MASTER_XM_USB_HS1,
216 	.buswidth = 8,
217 	.mas_rpm_id = 138,
218 	.slv_rpm_id = -1,
219 	.num_links = ARRAY_SIZE(mas_xi_usb_hs1_links),
220 	.links = mas_xi_usb_hs1_links,
221 };
222 
223 static const u16 mas_crypto_links[] = {
224 	QCS404_PNOC_SNOC_SLV,
225 	QCS404_PNOC_INT_2
226 };
227 
228 static struct qcom_icc_node mas_crypto = {
229 	.name = "mas_crypto",
230 	.id = QCS404_MASTER_CRYPTO_CORE0,
231 	.buswidth = 8,
232 	.mas_rpm_id = 23,
233 	.slv_rpm_id = -1,
234 	.num_links = ARRAY_SIZE(mas_crypto_links),
235 	.links = mas_crypto_links,
236 };
237 
238 static const u16 mas_sdcc_1_links[] = {
239 	QCS404_PNOC_INT_0
240 };
241 
242 static struct qcom_icc_node mas_sdcc_1 = {
243 	.name = "mas_sdcc_1",
244 	.id = QCS404_MASTER_SDCC_1,
245 	.buswidth = 8,
246 	.mas_rpm_id = 33,
247 	.slv_rpm_id = -1,
248 	.num_links = ARRAY_SIZE(mas_sdcc_1_links),
249 	.links = mas_sdcc_1_links,
250 };
251 
252 static const u16 mas_sdcc_2_links[] = {
253 	QCS404_PNOC_INT_0
254 };
255 
256 static struct qcom_icc_node mas_sdcc_2 = {
257 	.name = "mas_sdcc_2",
258 	.id = QCS404_MASTER_SDCC_2,
259 	.buswidth = 8,
260 	.mas_rpm_id = 35,
261 	.slv_rpm_id = -1,
262 	.num_links = ARRAY_SIZE(mas_sdcc_2_links),
263 	.links = mas_sdcc_2_links,
264 };
265 
266 static const u16 mas_snoc_pcnoc_links[] = {
267 	QCS404_PNOC_INT_2
268 };
269 
270 static struct qcom_icc_node mas_snoc_pcnoc = {
271 	.name = "mas_snoc_pcnoc",
272 	.id = QCS404_SNOC_PNOC_MAS,
273 	.buswidth = 8,
274 	.mas_rpm_id = 77,
275 	.slv_rpm_id = -1,
276 	.num_links = ARRAY_SIZE(mas_snoc_pcnoc_links),
277 	.links = mas_snoc_pcnoc_links,
278 };
279 
280 static const u16 mas_qpic_links[] = {
281 	QCS404_PNOC_INT_0
282 };
283 
284 static struct qcom_icc_node mas_qpic = {
285 	.name = "mas_qpic",
286 	.id = QCS404_MASTER_QPIC,
287 	.buswidth = 4,
288 	.mas_rpm_id = -1,
289 	.slv_rpm_id = -1,
290 	.num_links = ARRAY_SIZE(mas_qpic_links),
291 	.links = mas_qpic_links,
292 };
293 
294 static const u16 mas_qdss_bam_links[] = {
295 	QCS404_SNOC_QDSS_INT
296 };
297 
298 static struct qcom_icc_node mas_qdss_bam = {
299 	.name = "mas_qdss_bam",
300 	.id = QCS404_MASTER_QDSS_BAM,
301 	.buswidth = 4,
302 	.mas_rpm_id = -1,
303 	.slv_rpm_id = -1,
304 	.num_links = ARRAY_SIZE(mas_qdss_bam_links),
305 	.links = mas_qdss_bam_links,
306 };
307 
308 static const u16 mas_bimc_snoc_links[] = {
309 	QCS404_SLAVE_OCMEM_64,
310 	QCS404_SLAVE_CATS_128,
311 	QCS404_SNOC_INT_0,
312 	QCS404_SNOC_INT_1
313 };
314 
315 static struct qcom_icc_node mas_bimc_snoc = {
316 	.name = "mas_bimc_snoc",
317 	.id = QCS404_BIMC_SNOC_MAS,
318 	.buswidth = 8,
319 	.mas_rpm_id = 21,
320 	.slv_rpm_id = -1,
321 	.num_links = ARRAY_SIZE(mas_bimc_snoc_links),
322 	.links = mas_bimc_snoc_links,
323 };
324 
325 static const u16 mas_pcnoc_snoc_links[] = {
326 	QCS404_SNOC_BIMC_1_SLV,
327 	QCS404_SNOC_INT_2,
328 	QCS404_SNOC_INT_0
329 };
330 
331 static struct qcom_icc_node mas_pcnoc_snoc = {
332 	.name = "mas_pcnoc_snoc",
333 	.id = QCS404_PNOC_SNOC_MAS,
334 	.buswidth = 8,
335 	.mas_rpm_id = 29,
336 	.slv_rpm_id = -1,
337 	.num_links = ARRAY_SIZE(mas_pcnoc_snoc_links),
338 	.links = mas_pcnoc_snoc_links,
339 };
340 
341 static const u16 mas_qdss_etr_links[] = {
342 	QCS404_SNOC_QDSS_INT
343 };
344 
345 static struct qcom_icc_node mas_qdss_etr = {
346 	.name = "mas_qdss_etr",
347 	.id = QCS404_MASTER_QDSS_ETR,
348 	.buswidth = 8,
349 	.mas_rpm_id = -1,
350 	.slv_rpm_id = -1,
351 	.num_links = ARRAY_SIZE(mas_qdss_etr_links),
352 	.links = mas_qdss_etr_links,
353 };
354 
355 static const u16 mas_emac_links[] = {
356 	QCS404_SNOC_BIMC_1_SLV,
357 	QCS404_SNOC_INT_1
358 };
359 
360 static struct qcom_icc_node mas_emac = {
361 	.name = "mas_emac",
362 	.id = QCS404_MASTER_EMAC,
363 	.buswidth = 8,
364 	.mas_rpm_id = -1,
365 	.slv_rpm_id = -1,
366 	.num_links = ARRAY_SIZE(mas_emac_links),
367 	.links = mas_emac_links,
368 };
369 
370 static const u16 mas_pcie_links[] = {
371 	QCS404_SNOC_BIMC_1_SLV,
372 	QCS404_SNOC_INT_1
373 };
374 
375 static struct qcom_icc_node mas_pcie = {
376 	.name = "mas_pcie",
377 	.id = QCS404_MASTER_PCIE,
378 	.buswidth = 8,
379 	.mas_rpm_id = -1,
380 	.slv_rpm_id = -1,
381 	.num_links = ARRAY_SIZE(mas_pcie_links),
382 	.links = mas_pcie_links,
383 };
384 
385 static const u16 mas_usb3_links[] = {
386 	QCS404_SNOC_BIMC_1_SLV,
387 	QCS404_SNOC_INT_1
388 };
389 
390 static struct qcom_icc_node mas_usb3 = {
391 	.name = "mas_usb3",
392 	.id = QCS404_MASTER_USB3,
393 	.buswidth = 8,
394 	.mas_rpm_id = -1,
395 	.slv_rpm_id = -1,
396 	.num_links = ARRAY_SIZE(mas_usb3_links),
397 	.links = mas_usb3_links,
398 };
399 
400 static const u16 pcnoc_int_0_links[] = {
401 	QCS404_PNOC_SNOC_SLV,
402 	QCS404_PNOC_INT_2
403 };
404 
405 static struct qcom_icc_node pcnoc_int_0 = {
406 	.name = "pcnoc_int_0",
407 	.id = QCS404_PNOC_INT_0,
408 	.buswidth = 8,
409 	.mas_rpm_id = 85,
410 	.slv_rpm_id = 114,
411 	.num_links = ARRAY_SIZE(pcnoc_int_0_links),
412 	.links = pcnoc_int_0_links,
413 };
414 
415 static const u16 pcnoc_int_2_links[] = {
416 	QCS404_PNOC_SLV_10,
417 	QCS404_SLAVE_TCU,
418 	QCS404_PNOC_SLV_11,
419 	QCS404_PNOC_SLV_2,
420 	QCS404_PNOC_SLV_3,
421 	QCS404_PNOC_SLV_0,
422 	QCS404_PNOC_SLV_1,
423 	QCS404_PNOC_SLV_6,
424 	QCS404_PNOC_SLV_7,
425 	QCS404_PNOC_SLV_4,
426 	QCS404_PNOC_SLV_8,
427 	QCS404_PNOC_SLV_9
428 };
429 
430 static struct qcom_icc_node pcnoc_int_2 = {
431 	.name = "pcnoc_int_2",
432 	.id = QCS404_PNOC_INT_2,
433 	.buswidth = 8,
434 	.mas_rpm_id = 124,
435 	.slv_rpm_id = 184,
436 	.num_links = ARRAY_SIZE(pcnoc_int_2_links),
437 	.links = pcnoc_int_2_links,
438 };
439 
440 static const u16 pcnoc_int_3_links[] = {
441 	QCS404_PNOC_SNOC_SLV
442 };
443 
444 static struct qcom_icc_node pcnoc_int_3 = {
445 	.name = "pcnoc_int_3",
446 	.id = QCS404_PNOC_INT_3,
447 	.buswidth = 8,
448 	.mas_rpm_id = 125,
449 	.slv_rpm_id = 185,
450 	.num_links = ARRAY_SIZE(pcnoc_int_3_links),
451 	.links = pcnoc_int_3_links,
452 };
453 
454 static const u16 pcnoc_s_0_links[] = {
455 	QCS404_SLAVE_PRNG,
456 	QCS404_SLAVE_SPDM_WRAPPER,
457 	QCS404_SLAVE_PDM
458 };
459 
460 static struct qcom_icc_node pcnoc_s_0 = {
461 	.name = "pcnoc_s_0",
462 	.id = QCS404_PNOC_SLV_0,
463 	.buswidth = 4,
464 	.mas_rpm_id = 89,
465 	.slv_rpm_id = 118,
466 	.num_links = ARRAY_SIZE(pcnoc_s_0_links),
467 	.links = pcnoc_s_0_links,
468 };
469 
470 static const u16 pcnoc_s_1_links[] = {
471 	QCS404_SLAVE_TCSR
472 };
473 
474 static struct qcom_icc_node pcnoc_s_1 = {
475 	.name = "pcnoc_s_1",
476 	.id = QCS404_PNOC_SLV_1,
477 	.buswidth = 4,
478 	.mas_rpm_id = 90,
479 	.slv_rpm_id = 119,
480 	.num_links = ARRAY_SIZE(pcnoc_s_1_links),
481 	.links = pcnoc_s_1_links,
482 };
483 
484 static const u16 pcnoc_s_2_links[] = {
485 	QCS404_SLAVE_GRAPHICS_3D_CFG
486 };
487 
488 static struct qcom_icc_node pcnoc_s_2 = {
489 	.name = "pcnoc_s_2",
490 	.id = QCS404_PNOC_SLV_2,
491 	.buswidth = 4,
492 	.mas_rpm_id = -1,
493 	.slv_rpm_id = -1,
494 	.num_links = ARRAY_SIZE(pcnoc_s_2_links),
495 	.links = pcnoc_s_2_links,
496 };
497 
498 static const u16 pcnoc_s_3_links[] = {
499 	QCS404_SLAVE_MESSAGE_RAM
500 };
501 
502 static struct qcom_icc_node pcnoc_s_3 = {
503 	.name = "pcnoc_s_3",
504 	.id = QCS404_PNOC_SLV_3,
505 	.buswidth = 4,
506 	.mas_rpm_id = 92,
507 	.slv_rpm_id = 121,
508 	.num_links = ARRAY_SIZE(pcnoc_s_3_links),
509 	.links = pcnoc_s_3_links,
510 };
511 
512 static const u16 pcnoc_s_4_links[] = {
513 	QCS404_SLAVE_SNOC_CFG
514 };
515 
516 static struct qcom_icc_node pcnoc_s_4 = {
517 	.name = "pcnoc_s_4",
518 	.id = QCS404_PNOC_SLV_4,
519 	.buswidth = 4,
520 	.mas_rpm_id = 93,
521 	.slv_rpm_id = 122,
522 	.num_links = ARRAY_SIZE(pcnoc_s_4_links),
523 	.links = pcnoc_s_4_links,
524 };
525 
526 static const u16 pcnoc_s_6_links[] = {
527 	QCS404_SLAVE_BLSP_1,
528 	QCS404_SLAVE_TLMM_NORTH,
529 	QCS404_SLAVE_EMAC_CFG
530 };
531 
532 static struct qcom_icc_node pcnoc_s_6 = {
533 	.name = "pcnoc_s_6",
534 	.id = QCS404_PNOC_SLV_6,
535 	.buswidth = 4,
536 	.mas_rpm_id = 94,
537 	.slv_rpm_id = 123,
538 	.num_links = ARRAY_SIZE(pcnoc_s_6_links),
539 	.links = pcnoc_s_6_links,
540 };
541 
542 static const u16 pcnoc_s_7_links[] = {
543 	QCS404_SLAVE_TLMM_SOUTH,
544 	QCS404_SLAVE_DISPLAY_CFG,
545 	QCS404_SLAVE_SDCC_1,
546 	QCS404_SLAVE_PCIE_1,
547 	QCS404_SLAVE_SDCC_2
548 };
549 
550 static struct qcom_icc_node pcnoc_s_7 = {
551 	.name = "pcnoc_s_7",
552 	.id = QCS404_PNOC_SLV_7,
553 	.buswidth = 4,
554 	.mas_rpm_id = 95,
555 	.slv_rpm_id = 124,
556 	.num_links = ARRAY_SIZE(pcnoc_s_7_links),
557 	.links = pcnoc_s_7_links,
558 };
559 
560 static const u16 pcnoc_s_8_links[] = {
561 	QCS404_SLAVE_CRYPTO_0_CFG
562 };
563 
564 static struct qcom_icc_node pcnoc_s_8 = {
565 	.name = "pcnoc_s_8",
566 	.id = QCS404_PNOC_SLV_8,
567 	.buswidth = 4,
568 	.mas_rpm_id = 96,
569 	.slv_rpm_id = 125,
570 	.num_links = ARRAY_SIZE(pcnoc_s_8_links),
571 	.links = pcnoc_s_8_links,
572 };
573 
574 static const u16 pcnoc_s_9_links[] = {
575 	QCS404_SLAVE_BLSP_2,
576 	QCS404_SLAVE_TLMM_EAST,
577 	QCS404_SLAVE_PMIC_ARB
578 };
579 
580 static struct qcom_icc_node pcnoc_s_9 = {
581 	.name = "pcnoc_s_9",
582 	.id = QCS404_PNOC_SLV_9,
583 	.buswidth = 4,
584 	.mas_rpm_id = 97,
585 	.slv_rpm_id = 126,
586 	.num_links = ARRAY_SIZE(pcnoc_s_9_links),
587 	.links = pcnoc_s_9_links,
588 };
589 
590 static const u16 pcnoc_s_10_links[] = {
591 	QCS404_SLAVE_USB_HS
592 };
593 
594 static struct qcom_icc_node pcnoc_s_10 = {
595 	.name = "pcnoc_s_10",
596 	.id = QCS404_PNOC_SLV_10,
597 	.buswidth = 4,
598 	.mas_rpm_id = 157,
599 	.slv_rpm_id = -1,
600 	.num_links = ARRAY_SIZE(pcnoc_s_10_links),
601 	.links = pcnoc_s_10_links,
602 };
603 
604 static const u16 pcnoc_s_11_links[] = {
605 	QCS404_SLAVE_USB3
606 };
607 
608 static struct qcom_icc_node pcnoc_s_11 = {
609 	.name = "pcnoc_s_11",
610 	.id = QCS404_PNOC_SLV_11,
611 	.buswidth = 4,
612 	.mas_rpm_id = 158,
613 	.slv_rpm_id = 246,
614 	.num_links = ARRAY_SIZE(pcnoc_s_11_links),
615 	.links = pcnoc_s_11_links,
616 };
617 
618 static const u16 qdss_int_links[] = {
619 	QCS404_SNOC_BIMC_1_SLV,
620 	QCS404_SNOC_INT_1
621 };
622 
623 static struct qcom_icc_node qdss_int = {
624 	.name = "qdss_int",
625 	.id = QCS404_SNOC_QDSS_INT,
626 	.buswidth = 8,
627 	.mas_rpm_id = -1,
628 	.slv_rpm_id = -1,
629 	.num_links = ARRAY_SIZE(qdss_int_links),
630 	.links = qdss_int_links,
631 };
632 
633 static const u16 snoc_int_0_links[] = {
634 	QCS404_SLAVE_LPASS,
635 	QCS404_SLAVE_APPSS,
636 	QCS404_SLAVE_WCSS
637 };
638 
639 static struct qcom_icc_node snoc_int_0 = {
640 	.name = "snoc_int_0",
641 	.id = QCS404_SNOC_INT_0,
642 	.buswidth = 8,
643 	.mas_rpm_id = 99,
644 	.slv_rpm_id = 130,
645 	.num_links = ARRAY_SIZE(snoc_int_0_links),
646 	.links = snoc_int_0_links,
647 };
648 
649 static const u16 snoc_int_1_links[] = {
650 	QCS404_SNOC_PNOC_SLV,
651 	QCS404_SNOC_INT_2
652 };
653 
654 static struct qcom_icc_node snoc_int_1 = {
655 	.name = "snoc_int_1",
656 	.id = QCS404_SNOC_INT_1,
657 	.buswidth = 8,
658 	.mas_rpm_id = 100,
659 	.slv_rpm_id = 131,
660 	.num_links = ARRAY_SIZE(snoc_int_1_links),
661 	.links = snoc_int_1_links,
662 };
663 
664 static const u16 snoc_int_2_links[] = {
665 	QCS404_SLAVE_QDSS_STM,
666 	QCS404_SLAVE_OCIMEM
667 };
668 
669 static struct qcom_icc_node snoc_int_2 = {
670 	.name = "snoc_int_2",
671 	.id = QCS404_SNOC_INT_2,
672 	.buswidth = 8,
673 	.mas_rpm_id = 134,
674 	.slv_rpm_id = 197,
675 	.num_links = ARRAY_SIZE(snoc_int_2_links),
676 	.links = snoc_int_2_links,
677 };
678 
679 static struct qcom_icc_node slv_ebi = {
680 	.name = "slv_ebi",
681 	.id = QCS404_SLAVE_EBI_CH0,
682 	.buswidth = 8,
683 	.mas_rpm_id = -1,
684 	.slv_rpm_id = 0,
685 };
686 
687 static const u16 slv_bimc_snoc_links[] = {
688 	QCS404_BIMC_SNOC_MAS
689 };
690 
691 static struct qcom_icc_node slv_bimc_snoc = {
692 	.name = "slv_bimc_snoc",
693 	.id = QCS404_BIMC_SNOC_SLV,
694 	.buswidth = 8,
695 	.mas_rpm_id = -1,
696 	.slv_rpm_id = 2,
697 	.num_links = ARRAY_SIZE(slv_bimc_snoc_links),
698 	.links = slv_bimc_snoc_links,
699 };
700 
701 static struct qcom_icc_node slv_spdm = {
702 	.name = "slv_spdm",
703 	.id = QCS404_SLAVE_SPDM_WRAPPER,
704 	.buswidth = 4,
705 	.mas_rpm_id = -1,
706 	.slv_rpm_id = -1,
707 };
708 
709 static struct qcom_icc_node slv_pdm = {
710 	.name = "slv_pdm",
711 	.id = QCS404_SLAVE_PDM,
712 	.buswidth = 4,
713 	.mas_rpm_id = -1,
714 	.slv_rpm_id = 41,
715 };
716 
717 static struct qcom_icc_node slv_prng = {
718 	.name = "slv_prng",
719 	.id = QCS404_SLAVE_PRNG,
720 	.buswidth = 4,
721 	.mas_rpm_id = -1,
722 	.slv_rpm_id = 44,
723 };
724 
725 static struct qcom_icc_node slv_tcsr = {
726 	.name = "slv_tcsr",
727 	.id = QCS404_SLAVE_TCSR,
728 	.buswidth = 4,
729 	.mas_rpm_id = -1,
730 	.slv_rpm_id = 50,
731 };
732 
733 static struct qcom_icc_node slv_snoc_cfg = {
734 	.name = "slv_snoc_cfg",
735 	.id = QCS404_SLAVE_SNOC_CFG,
736 	.buswidth = 4,
737 	.mas_rpm_id = -1,
738 	.slv_rpm_id = 70,
739 };
740 
741 static struct qcom_icc_node slv_message_ram = {
742 	.name = "slv_message_ram",
743 	.id = QCS404_SLAVE_MESSAGE_RAM,
744 	.buswidth = 4,
745 	.mas_rpm_id = -1,
746 	.slv_rpm_id = 55,
747 };
748 
749 static struct qcom_icc_node slv_disp_ss_cfg = {
750 	.name = "slv_disp_ss_cfg",
751 	.id = QCS404_SLAVE_DISPLAY_CFG,
752 	.buswidth = 4,
753 	.mas_rpm_id = -1,
754 	.slv_rpm_id = -1,
755 };
756 
757 static struct qcom_icc_node slv_gpu_cfg = {
758 	.name = "slv_gpu_cfg",
759 	.id = QCS404_SLAVE_GRAPHICS_3D_CFG,
760 	.buswidth = 4,
761 	.mas_rpm_id = -1,
762 	.slv_rpm_id = -1,
763 };
764 
765 static struct qcom_icc_node slv_blsp_1 = {
766 	.name = "slv_blsp_1",
767 	.id = QCS404_SLAVE_BLSP_1,
768 	.buswidth = 4,
769 	.mas_rpm_id = -1,
770 	.slv_rpm_id = 39,
771 };
772 
773 static struct qcom_icc_node slv_tlmm_north = {
774 	.name = "slv_tlmm_north",
775 	.id = QCS404_SLAVE_TLMM_NORTH,
776 	.buswidth = 4,
777 	.mas_rpm_id = -1,
778 	.slv_rpm_id = 214,
779 };
780 
781 static struct qcom_icc_node slv_pcie = {
782 	.name = "slv_pcie",
783 	.id = QCS404_SLAVE_PCIE_1,
784 	.buswidth = 4,
785 	.mas_rpm_id = -1,
786 	.slv_rpm_id = -1,
787 };
788 
789 static struct qcom_icc_node slv_ethernet = {
790 	.name = "slv_ethernet",
791 	.id = QCS404_SLAVE_EMAC_CFG,
792 	.buswidth = 4,
793 	.mas_rpm_id = -1,
794 	.slv_rpm_id = -1,
795 };
796 
797 static struct qcom_icc_node slv_blsp_2 = {
798 	.name = "slv_blsp_2",
799 	.id = QCS404_SLAVE_BLSP_2,
800 	.buswidth = 4,
801 	.mas_rpm_id = -1,
802 	.slv_rpm_id = 37,
803 };
804 
805 static struct qcom_icc_node slv_tlmm_east = {
806 	.name = "slv_tlmm_east",
807 	.id = QCS404_SLAVE_TLMM_EAST,
808 	.buswidth = 4,
809 	.mas_rpm_id = -1,
810 	.slv_rpm_id = 213,
811 };
812 
813 static struct qcom_icc_node slv_tcu = {
814 	.name = "slv_tcu",
815 	.id = QCS404_SLAVE_TCU,
816 	.buswidth = 8,
817 	.mas_rpm_id = -1,
818 	.slv_rpm_id = -1,
819 };
820 
821 static struct qcom_icc_node slv_pmic_arb = {
822 	.name = "slv_pmic_arb",
823 	.id = QCS404_SLAVE_PMIC_ARB,
824 	.buswidth = 4,
825 	.mas_rpm_id = -1,
826 	.slv_rpm_id = 59,
827 };
828 
829 static struct qcom_icc_node slv_sdcc_1 = {
830 	.name = "slv_sdcc_1",
831 	.id = QCS404_SLAVE_SDCC_1,
832 	.buswidth = 4,
833 	.mas_rpm_id = -1,
834 	.slv_rpm_id = 31,
835 };
836 
837 static struct qcom_icc_node slv_sdcc_2 = {
838 	.name = "slv_sdcc_2",
839 	.id = QCS404_SLAVE_SDCC_2,
840 	.buswidth = 4,
841 	.mas_rpm_id = -1,
842 	.slv_rpm_id = 33,
843 };
844 
845 static struct qcom_icc_node slv_tlmm_south = {
846 	.name = "slv_tlmm_south",
847 	.id = QCS404_SLAVE_TLMM_SOUTH,
848 	.buswidth = 4,
849 	.mas_rpm_id = -1,
850 	.slv_rpm_id = -1,
851 };
852 
853 static struct qcom_icc_node slv_usb_hs = {
854 	.name = "slv_usb_hs",
855 	.id = QCS404_SLAVE_USB_HS,
856 	.buswidth = 4,
857 	.mas_rpm_id = -1,
858 	.slv_rpm_id = 40,
859 };
860 
861 static struct qcom_icc_node slv_usb3 = {
862 	.name = "slv_usb3",
863 	.id = QCS404_SLAVE_USB3,
864 	.buswidth = 4,
865 	.mas_rpm_id = -1,
866 	.slv_rpm_id = 22,
867 };
868 
869 static struct qcom_icc_node slv_crypto_0_cfg = {
870 	.name = "slv_crypto_0_cfg",
871 	.id = QCS404_SLAVE_CRYPTO_0_CFG,
872 	.buswidth = 4,
873 	.mas_rpm_id = -1,
874 	.slv_rpm_id = 52,
875 };
876 
877 static const u16 slv_pcnoc_snoc_links[] = {
878 	QCS404_PNOC_SNOC_MAS
879 };
880 
881 static struct qcom_icc_node slv_pcnoc_snoc = {
882 	.name = "slv_pcnoc_snoc",
883 	.id = QCS404_PNOC_SNOC_SLV,
884 	.buswidth = 8,
885 	.mas_rpm_id = -1,
886 	.slv_rpm_id = 45,
887 	.num_links = ARRAY_SIZE(slv_pcnoc_snoc_links),
888 	.links = slv_pcnoc_snoc_links,
889 };
890 
891 static struct qcom_icc_node slv_kpss_ahb = {
892 	.name = "slv_kpss_ahb",
893 	.id = QCS404_SLAVE_APPSS,
894 	.buswidth = 4,
895 	.mas_rpm_id = -1,
896 	.slv_rpm_id = -1,
897 };
898 
899 static struct qcom_icc_node slv_wcss = {
900 	.name = "slv_wcss",
901 	.id = QCS404_SLAVE_WCSS,
902 	.buswidth = 4,
903 	.mas_rpm_id = -1,
904 	.slv_rpm_id = 23,
905 };
906 
907 static const u16 slv_snoc_bimc_1_links[] = {
908 	QCS404_SNOC_BIMC_1_MAS
909 };
910 
911 static struct qcom_icc_node slv_snoc_bimc_1 = {
912 	.name = "slv_snoc_bimc_1",
913 	.id = QCS404_SNOC_BIMC_1_SLV,
914 	.buswidth = 8,
915 	.mas_rpm_id = -1,
916 	.slv_rpm_id = 104,
917 	.num_links = ARRAY_SIZE(slv_snoc_bimc_1_links),
918 	.links = slv_snoc_bimc_1_links,
919 };
920 
921 static struct qcom_icc_node slv_imem = {
922 	.name = "slv_imem",
923 	.id = QCS404_SLAVE_OCIMEM,
924 	.buswidth = 8,
925 	.mas_rpm_id = -1,
926 	.slv_rpm_id = 26,
927 };
928 
929 static const u16 slv_snoc_pcnoc_links[] = {
930 	QCS404_SNOC_PNOC_MAS
931 };
932 
933 static struct qcom_icc_node slv_snoc_pcnoc = {
934 	.name = "slv_snoc_pcnoc",
935 	.id = QCS404_SNOC_PNOC_SLV,
936 	.buswidth = 8,
937 	.mas_rpm_id = -1,
938 	.slv_rpm_id = 28,
939 	.num_links = ARRAY_SIZE(slv_snoc_pcnoc_links),
940 	.links = slv_snoc_pcnoc_links,
941 };
942 
943 static struct qcom_icc_node slv_qdss_stm = {
944 	.name = "slv_qdss_stm",
945 	.id = QCS404_SLAVE_QDSS_STM,
946 	.buswidth = 4,
947 	.mas_rpm_id = -1,
948 	.slv_rpm_id = 30,
949 };
950 
951 static struct qcom_icc_node slv_cats_0 = {
952 	.name = "slv_cats_0",
953 	.id = QCS404_SLAVE_CATS_128,
954 	.buswidth = 16,
955 	.mas_rpm_id = -1,
956 	.slv_rpm_id = -1,
957 };
958 
959 static struct qcom_icc_node slv_cats_1 = {
960 	.name = "slv_cats_1",
961 	.id = QCS404_SLAVE_OCMEM_64,
962 	.buswidth = 8,
963 	.mas_rpm_id = -1,
964 	.slv_rpm_id = -1,
965 };
966 
967 static struct qcom_icc_node slv_lpass = {
968 	.name = "slv_lpass",
969 	.id = QCS404_SLAVE_LPASS,
970 	.buswidth = 4,
971 	.mas_rpm_id = -1,
972 	.slv_rpm_id = -1,
973 };
974 
975 static struct qcom_icc_node * const qcs404_bimc_nodes[] = {
976 	[MASTER_AMPSS_M0] = &mas_apps_proc,
977 	[MASTER_OXILI] = &mas_oxili,
978 	[MASTER_MDP_PORT0] = &mas_mdp,
979 	[MASTER_SNOC_BIMC_1] = &mas_snoc_bimc_1,
980 	[MASTER_TCU_0] = &mas_tcu_0,
981 	[SLAVE_EBI_CH0] = &slv_ebi,
982 	[SLAVE_BIMC_SNOC] = &slv_bimc_snoc,
983 };
984 
985 static const struct qcom_icc_desc qcs404_bimc = {
986 	.bus_clk_desc = &bimc_clk,
987 	.nodes = qcs404_bimc_nodes,
988 	.num_nodes = ARRAY_SIZE(qcs404_bimc_nodes),
989 };
990 
991 static struct qcom_icc_node * const qcs404_pcnoc_nodes[] = {
992 	[MASTER_SPDM] = &mas_spdm,
993 	[MASTER_BLSP_1] = &mas_blsp_1,
994 	[MASTER_BLSP_2] = &mas_blsp_2,
995 	[MASTER_XI_USB_HS1] = &mas_xi_usb_hs1,
996 	[MASTER_CRYPT0] = &mas_crypto,
997 	[MASTER_SDCC_1] = &mas_sdcc_1,
998 	[MASTER_SDCC_2] = &mas_sdcc_2,
999 	[MASTER_SNOC_PCNOC] = &mas_snoc_pcnoc,
1000 	[MASTER_QPIC] = &mas_qpic,
1001 	[PCNOC_INT_0] = &pcnoc_int_0,
1002 	[PCNOC_INT_2] = &pcnoc_int_2,
1003 	[PCNOC_INT_3] = &pcnoc_int_3,
1004 	[PCNOC_S_0] = &pcnoc_s_0,
1005 	[PCNOC_S_1] = &pcnoc_s_1,
1006 	[PCNOC_S_2] = &pcnoc_s_2,
1007 	[PCNOC_S_3] = &pcnoc_s_3,
1008 	[PCNOC_S_4] = &pcnoc_s_4,
1009 	[PCNOC_S_6] = &pcnoc_s_6,
1010 	[PCNOC_S_7] = &pcnoc_s_7,
1011 	[PCNOC_S_8] = &pcnoc_s_8,
1012 	[PCNOC_S_9] = &pcnoc_s_9,
1013 	[PCNOC_S_10] = &pcnoc_s_10,
1014 	[PCNOC_S_11] = &pcnoc_s_11,
1015 	[SLAVE_SPDM] = &slv_spdm,
1016 	[SLAVE_PDM] = &slv_pdm,
1017 	[SLAVE_PRNG] = &slv_prng,
1018 	[SLAVE_TCSR] = &slv_tcsr,
1019 	[SLAVE_SNOC_CFG] = &slv_snoc_cfg,
1020 	[SLAVE_MESSAGE_RAM] = &slv_message_ram,
1021 	[SLAVE_DISP_SS_CFG] = &slv_disp_ss_cfg,
1022 	[SLAVE_GPU_CFG] = &slv_gpu_cfg,
1023 	[SLAVE_BLSP_1] = &slv_blsp_1,
1024 	[SLAVE_BLSP_2] = &slv_blsp_2,
1025 	[SLAVE_TLMM_NORTH] = &slv_tlmm_north,
1026 	[SLAVE_PCIE] = &slv_pcie,
1027 	[SLAVE_ETHERNET] = &slv_ethernet,
1028 	[SLAVE_TLMM_EAST] = &slv_tlmm_east,
1029 	[SLAVE_TCU] = &slv_tcu,
1030 	[SLAVE_PMIC_ARB] = &slv_pmic_arb,
1031 	[SLAVE_SDCC_1] = &slv_sdcc_1,
1032 	[SLAVE_SDCC_2] = &slv_sdcc_2,
1033 	[SLAVE_TLMM_SOUTH] = &slv_tlmm_south,
1034 	[SLAVE_USB_HS] = &slv_usb_hs,
1035 	[SLAVE_USB3] = &slv_usb3,
1036 	[SLAVE_CRYPTO_0_CFG] = &slv_crypto_0_cfg,
1037 	[SLAVE_PCNOC_SNOC] = &slv_pcnoc_snoc,
1038 };
1039 
1040 static const struct qcom_icc_desc qcs404_pcnoc = {
1041 	.bus_clk_desc = &bus_0_clk,
1042 	.nodes = qcs404_pcnoc_nodes,
1043 	.num_nodes = ARRAY_SIZE(qcs404_pcnoc_nodes),
1044 };
1045 
1046 static struct qcom_icc_node * const qcs404_snoc_nodes[] = {
1047 	[MASTER_QDSS_BAM] = &mas_qdss_bam,
1048 	[MASTER_BIMC_SNOC] = &mas_bimc_snoc,
1049 	[MASTER_PCNOC_SNOC] = &mas_pcnoc_snoc,
1050 	[MASTER_QDSS_ETR] = &mas_qdss_etr,
1051 	[MASTER_EMAC] = &mas_emac,
1052 	[MASTER_PCIE] = &mas_pcie,
1053 	[MASTER_USB3] = &mas_usb3,
1054 	[QDSS_INT] = &qdss_int,
1055 	[SNOC_INT_0] = &snoc_int_0,
1056 	[SNOC_INT_1] = &snoc_int_1,
1057 	[SNOC_INT_2] = &snoc_int_2,
1058 	[SLAVE_KPSS_AHB] = &slv_kpss_ahb,
1059 	[SLAVE_WCSS] = &slv_wcss,
1060 	[SLAVE_SNOC_BIMC_1] = &slv_snoc_bimc_1,
1061 	[SLAVE_IMEM] = &slv_imem,
1062 	[SLAVE_SNOC_PCNOC] = &slv_snoc_pcnoc,
1063 	[SLAVE_QDSS_STM] = &slv_qdss_stm,
1064 	[SLAVE_CATS_0] = &slv_cats_0,
1065 	[SLAVE_CATS_1] = &slv_cats_1,
1066 	[SLAVE_LPASS] = &slv_lpass,
1067 };
1068 
1069 static const struct qcom_icc_desc qcs404_snoc = {
1070 	.bus_clk_desc = &bus_1_clk,
1071 	.nodes = qcs404_snoc_nodes,
1072 	.num_nodes = ARRAY_SIZE(qcs404_snoc_nodes),
1073 };
1074 
1075 
1076 static const struct of_device_id qcs404_noc_of_match[] = {
1077 	{ .compatible = "qcom,qcs404-bimc", .data = &qcs404_bimc },
1078 	{ .compatible = "qcom,qcs404-pcnoc", .data = &qcs404_pcnoc },
1079 	{ .compatible = "qcom,qcs404-snoc", .data = &qcs404_snoc },
1080 	{ },
1081 };
1082 MODULE_DEVICE_TABLE(of, qcs404_noc_of_match);
1083 
1084 static struct platform_driver qcs404_noc_driver = {
1085 	.probe = qnoc_probe,
1086 	.remove = qnoc_remove,
1087 	.driver = {
1088 		.name = "qnoc-qcs404",
1089 		.of_match_table = qcs404_noc_of_match,
1090 	},
1091 };
1092 module_platform_driver(qcs404_noc_driver);
1093 MODULE_DESCRIPTION("Qualcomm QCS404 NoC driver");
1094 MODULE_LICENSE("GPL v2");
1095