1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2015, The Linux Foundation. All rights reserved.
4 */
5
6/dts-v1/;
7
8#include <dt-bindings/clock/qcom,gcc-ipq4019.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10#include <dt-bindings/interrupt-controller/irq.h>
11
12/ {
13	#address-cells = <1>;
14	#size-cells = <1>;
15
16	model = "Qualcomm Technologies, Inc. IPQ4019";
17	compatible = "qcom,ipq4019";
18	interrupt-parent = <&intc>;
19
20	reserved-memory {
21		#address-cells = <0x1>;
22		#size-cells = <0x1>;
23		ranges;
24
25		smem_region: smem@87e00000 {
26			reg = <0x87e00000 0x080000>;
27			no-map;
28		};
29
30		tz@87e80000 {
31			reg = <0x87e80000 0x180000>;
32			no-map;
33		};
34	};
35
36	aliases {
37		spi0 = &blsp1_spi1;
38		spi1 = &blsp1_spi2;
39		i2c0 = &blsp1_i2c3;
40		i2c1 = &blsp1_i2c4;
41	};
42
43	cpus {
44		#address-cells = <1>;
45		#size-cells = <0>;
46		cpu@0 {
47			device_type = "cpu";
48			compatible = "arm,cortex-a7";
49			enable-method = "qcom,kpss-acc-v2";
50			next-level-cache = <&L2>;
51			qcom,acc = <&acc0>;
52			qcom,saw = <&saw0>;
53			reg = <0x0>;
54			clocks = <&gcc GCC_APPS_CLK_SRC>;
55			clock-frequency = <0>;
56			clock-latency = <256000>;
57			operating-points-v2 = <&cpu0_opp_table>;
58		};
59
60		cpu@1 {
61			device_type = "cpu";
62			compatible = "arm,cortex-a7";
63			enable-method = "qcom,kpss-acc-v2";
64			next-level-cache = <&L2>;
65			qcom,acc = <&acc1>;
66			qcom,saw = <&saw1>;
67			reg = <0x1>;
68			clocks = <&gcc GCC_APPS_CLK_SRC>;
69			clock-frequency = <0>;
70			clock-latency = <256000>;
71			operating-points-v2 = <&cpu0_opp_table>;
72		};
73
74		cpu@2 {
75			device_type = "cpu";
76			compatible = "arm,cortex-a7";
77			enable-method = "qcom,kpss-acc-v2";
78			next-level-cache = <&L2>;
79			qcom,acc = <&acc2>;
80			qcom,saw = <&saw2>;
81			reg = <0x2>;
82			clocks = <&gcc GCC_APPS_CLK_SRC>;
83			clock-frequency = <0>;
84			clock-latency = <256000>;
85			operating-points-v2 = <&cpu0_opp_table>;
86		};
87
88		cpu@3 {
89			device_type = "cpu";
90			compatible = "arm,cortex-a7";
91			enable-method = "qcom,kpss-acc-v2";
92			next-level-cache = <&L2>;
93			qcom,acc = <&acc3>;
94			qcom,saw = <&saw3>;
95			reg = <0x3>;
96			clocks = <&gcc GCC_APPS_CLK_SRC>;
97			clock-frequency = <0>;
98			clock-latency = <256000>;
99			operating-points-v2 = <&cpu0_opp_table>;
100		};
101
102		L2: l2-cache {
103			compatible = "cache";
104			cache-level = <2>;
105			cache-unified;
106			qcom,saw = <&saw_l2>;
107		};
108	};
109
110	cpu0_opp_table: opp-table {
111		compatible = "operating-points-v2";
112		opp-shared;
113
114		opp-48000000 {
115			opp-hz = /bits/ 64 <48000000>;
116			clock-latency-ns = <256000>;
117		};
118		opp-200000000 {
119			opp-hz = /bits/ 64 <200000000>;
120			clock-latency-ns = <256000>;
121		};
122		opp-500000000 {
123			opp-hz = /bits/ 64 <500000000>;
124			clock-latency-ns = <256000>;
125		};
126		opp-716000000 {
127			opp-hz = /bits/ 64 <716000000>;
128			clock-latency-ns = <256000>;
129 		};
130	};
131
132	memory {
133		device_type = "memory";
134		reg = <0x0 0x0>;
135	};
136
137	pmu {
138		compatible = "arm,cortex-a7-pmu";
139		interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) |
140					 IRQ_TYPE_LEVEL_HIGH)>;
141	};
142
143	clocks {
144		sleep_clk: sleep_clk {
145			compatible = "fixed-clock";
146			clock-frequency = <32000>;
147			#clock-cells = <0>;
148		};
149
150		xo: xo {
151			compatible = "fixed-clock";
152			clock-frequency = <48000000>;
153			#clock-cells = <0>;
154		};
155	};
156
157	firmware {
158		scm {
159			compatible = "qcom,scm-ipq4019", "qcom,scm";
160		};
161	};
162
163	timer {
164		compatible = "arm,armv7-timer";
165		interrupts = <1 2 0xf08>,
166			     <1 3 0xf08>,
167			     <1 4 0xf08>,
168			     <1 1 0xf08>;
169		clock-frequency = <48000000>;
170		always-on;
171	};
172
173	soc {
174		#address-cells = <1>;
175		#size-cells = <1>;
176		ranges;
177		compatible = "simple-bus";
178
179		intc: interrupt-controller@b000000 {
180			compatible = "qcom,msm-qgic2";
181			interrupt-controller;
182			#interrupt-cells = <3>;
183			reg = <0x0b000000 0x1000>,
184			<0x0b002000 0x1000>;
185		};
186
187		gcc: clock-controller@1800000 {
188			compatible = "qcom,gcc-ipq4019";
189			#clock-cells = <1>;
190			#power-domain-cells = <1>;
191			#reset-cells = <1>;
192			reg = <0x1800000 0x60000>;
193			clocks = <&xo>, <&sleep_clk>;
194			clock-names = "xo", "sleep_clk";
195		};
196
197		prng: rng@22000 {
198			compatible = "qcom,prng";
199			reg = <0x22000 0x140>;
200			clocks = <&gcc GCC_PRNG_AHB_CLK>;
201			clock-names = "core";
202			status = "disabled";
203		};
204
205		tlmm: pinctrl@1000000 {
206			compatible = "qcom,ipq4019-pinctrl";
207			reg = <0x01000000 0x300000>;
208			gpio-controller;
209			gpio-ranges = <&tlmm 0 0 100>;
210			#gpio-cells = <2>;
211			interrupt-controller;
212			#interrupt-cells = <2>;
213			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
214		};
215
216		vqmmc: regulator@1948000 {
217			compatible = "qcom,vqmmc-ipq4019-regulator";
218			reg = <0x01948000 0x4>;
219			regulator-name = "vqmmc";
220			regulator-min-microvolt = <1500000>;
221			regulator-max-microvolt = <3000000>;
222			regulator-always-on;
223			status = "disabled";
224		};
225
226		sdhci: mmc@7824900 {
227			compatible = "qcom,sdhci-msm-v4";
228			reg = <0x7824900 0x11c>, <0x7824000 0x800>;
229			reg-names = "hc", "core";
230			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
231			interrupt-names = "hc_irq", "pwr_irq";
232			bus-width = <8>;
233			clocks = <&gcc GCC_SDCC1_AHB_CLK>,
234				 <&gcc GCC_SDCC1_APPS_CLK>,
235				 <&xo>;
236			clock-names = "iface",
237				      "core",
238				      "xo";
239			status = "disabled";
240		};
241
242		blsp_dma: dma-controller@7884000 {
243			compatible = "qcom,bam-v1.7.0";
244			reg = <0x07884000 0x23000>;
245			interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
246			clocks = <&gcc GCC_BLSP1_AHB_CLK>;
247			clock-names = "bam_clk";
248			#dma-cells = <1>;
249			qcom,ee = <0>;
250			status = "disabled";
251		};
252
253		blsp1_spi1: spi@78b5000 { /* BLSP1 QUP1 */
254			compatible = "qcom,spi-qup-v2.2.1";
255			reg = <0x78b5000 0x600>;
256			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
257			clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
258				 <&gcc GCC_BLSP1_AHB_CLK>;
259			clock-names = "core", "iface";
260			#address-cells = <1>;
261			#size-cells = <0>;
262			dmas = <&blsp_dma 4>, <&blsp_dma 5>;
263			dma-names = "tx", "rx";
264			status = "disabled";
265		};
266
267		blsp1_spi2: spi@78b6000 { /* BLSP1 QUP2 */
268			compatible = "qcom,spi-qup-v2.2.1";
269			reg = <0x78b6000 0x600>;
270			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
271			clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
272				<&gcc GCC_BLSP1_AHB_CLK>;
273			clock-names = "core", "iface";
274			#address-cells = <1>;
275			#size-cells = <0>;
276			dmas = <&blsp_dma 6>, <&blsp_dma 7>;
277			dma-names = "tx", "rx";
278			status = "disabled";
279		};
280
281		blsp1_i2c3: i2c@78b7000 { /* BLSP1 QUP3 */
282			compatible = "qcom,i2c-qup-v2.2.1";
283			reg = <0x78b7000 0x600>;
284			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
285			clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
286				 <&gcc GCC_BLSP1_AHB_CLK>;
287			clock-names = "core", "iface";
288			#address-cells = <1>;
289			#size-cells = <0>;
290			dmas = <&blsp_dma 8>, <&blsp_dma 9>;
291			dma-names = "tx", "rx";
292			status = "disabled";
293		};
294
295		blsp1_i2c4: i2c@78b8000 { /* BLSP1 QUP4 */
296			compatible = "qcom,i2c-qup-v2.2.1";
297			reg = <0x78b8000 0x600>;
298			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
299			clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
300				 <&gcc GCC_BLSP1_AHB_CLK>;
301			clock-names = "core", "iface";
302			#address-cells = <1>;
303			#size-cells = <0>;
304			dmas = <&blsp_dma 10>, <&blsp_dma 11>;
305			dma-names = "tx", "rx";
306			status = "disabled";
307		};
308
309		cryptobam: dma-controller@8e04000 {
310			compatible = "qcom,bam-v1.7.0";
311			reg = <0x08e04000 0x20000>;
312			interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
313			clocks = <&gcc GCC_CRYPTO_AHB_CLK>;
314			clock-names = "bam_clk";
315			#dma-cells = <1>;
316			qcom,ee = <1>;
317			qcom,controlled-remotely;
318			status = "disabled";
319		};
320
321		crypto: crypto@8e3a000 {
322			compatible = "qcom,crypto-v5.1";
323			reg = <0x08e3a000 0x6000>;
324			clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
325				 <&gcc GCC_CRYPTO_AXI_CLK>,
326				 <&gcc GCC_CRYPTO_CLK>;
327			clock-names = "iface", "bus", "core";
328			dmas = <&cryptobam 2>, <&cryptobam 3>;
329			dma-names = "rx", "tx";
330			status = "disabled";
331		};
332
333		acc0: power-manager@b088000 {
334			compatible = "qcom,kpss-acc-v2";
335			reg = <0x0b088000 0x1000>, <0xb008000 0x1000>;
336		};
337
338		acc1: power-manager@b098000 {
339			compatible = "qcom,kpss-acc-v2";
340			reg = <0x0b098000 0x1000>, <0xb008000 0x1000>;
341		};
342
343		acc2: power-manager@b0a8000 {
344			compatible = "qcom,kpss-acc-v2";
345			reg = <0x0b0a8000 0x1000>, <0xb008000 0x1000>;
346		};
347
348		acc3: power-manager@b0b8000 {
349			compatible = "qcom,kpss-acc-v2";
350			reg = <0x0b0b8000 0x1000>, <0xb008000 0x1000>;
351		};
352
353		saw0: regulator@b089000 {
354			compatible = "qcom,saw2";
355			reg = <0x0b089000 0x1000>, <0x0b009000 0x1000>;
356			regulator;
357		};
358
359		saw1: regulator@b099000 {
360			compatible = "qcom,saw2";
361			reg = <0x0b099000 0x1000>, <0x0b009000 0x1000>;
362			regulator;
363		};
364
365		saw2: regulator@b0a9000 {
366			compatible = "qcom,saw2";
367			reg = <0x0b0a9000 0x1000>, <0x0b009000 0x1000>;
368			regulator;
369		};
370
371		saw3: regulator@b0b9000 {
372			compatible = "qcom,saw2";
373			reg = <0x0b0b9000 0x1000>, <0x0b009000 0x1000>;
374			regulator;
375		};
376
377		saw_l2: regulator@b012000 {
378			compatible = "qcom,saw2";
379			reg = <0xb012000 0x1000>;
380			regulator;
381		};
382
383		blsp1_uart1: serial@78af000 {
384			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
385			reg = <0x78af000 0x200>;
386			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
387			status = "disabled";
388			clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
389				<&gcc GCC_BLSP1_AHB_CLK>;
390			clock-names = "core", "iface";
391			dmas = <&blsp_dma 0>, <&blsp_dma 1>;
392			dma-names = "tx", "rx";
393		};
394
395		blsp1_uart2: serial@78b0000 {
396			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
397			reg = <0x78b0000 0x200>;
398			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
399			status = "disabled";
400			clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
401				<&gcc GCC_BLSP1_AHB_CLK>;
402			clock-names = "core", "iface";
403			dmas = <&blsp_dma 2>, <&blsp_dma 3>;
404			dma-names = "tx", "rx";
405		};
406
407		watchdog: watchdog@b017000 {
408			compatible = "qcom,kpss-wdt-ipq4019", "qcom,kpss-wdt";
409			reg = <0xb017000 0x40>;
410			clocks = <&sleep_clk>;
411			timeout-sec = <10>;
412			status = "disabled";
413		};
414
415		restart@4ab000 {
416			compatible = "qcom,pshold";
417			reg = <0x4ab000 0x4>;
418		};
419
420		pcie0: pci@40000000 {
421			compatible = "qcom,pcie-ipq4019";
422			reg = <0x40000000 0xf1d>,
423			      <0x40000f20 0xa8>,
424			      <0x80000 0x2000>,
425			      <0x40100000 0x1000>;
426			reg-names = "dbi", "elbi", "parf", "config";
427			device_type = "pci";
428			linux,pci-domain = <0>;
429			bus-range = <0x00 0xff>;
430			num-lanes = <1>;
431			#address-cells = <3>;
432			#size-cells = <2>;
433
434			ranges = <0x81000000 0x0 0x00000000 0x40200000 0x0 0x00100000>,
435				 <0x82000000 0x0 0x40300000 0x40300000 0x0 0x00d00000>;
436
437			interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
438			interrupt-names = "msi";
439			#interrupt-cells = <1>;
440			interrupt-map-mask = <0 0 0 0x7>;
441			interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
442					<0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
443					<0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
444					<0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
445			clocks = <&gcc GCC_PCIE_AHB_CLK>,
446				 <&gcc GCC_PCIE_AXI_M_CLK>,
447				 <&gcc GCC_PCIE_AXI_S_CLK>;
448			clock-names = "aux",
449				      "master_bus",
450				      "slave_bus";
451
452			resets = <&gcc PCIE_AXI_M_ARES>,
453				 <&gcc PCIE_AXI_S_ARES>,
454				 <&gcc PCIE_PIPE_ARES>,
455				 <&gcc PCIE_AXI_M_VMIDMT_ARES>,
456				 <&gcc PCIE_AXI_S_XPU_ARES>,
457				 <&gcc PCIE_PARF_XPU_ARES>,
458				 <&gcc PCIE_PHY_ARES>,
459				 <&gcc PCIE_AXI_M_STICKY_ARES>,
460				 <&gcc PCIE_PIPE_STICKY_ARES>,
461				 <&gcc PCIE_PWR_ARES>,
462				 <&gcc PCIE_AHB_ARES>,
463				 <&gcc PCIE_PHY_AHB_ARES>;
464			reset-names = "axi_m",
465				      "axi_s",
466				      "pipe",
467				      "axi_m_vmid",
468				      "axi_s_xpu",
469				      "parf",
470				      "phy",
471				      "axi_m_sticky",
472				      "pipe_sticky",
473				      "pwr",
474				      "ahb",
475				      "phy_ahb";
476
477			status = "disabled";
478		};
479
480		qpic_bam: dma-controller@7984000 {
481			compatible = "qcom,bam-v1.7.0";
482			reg = <0x7984000 0x1a000>;
483			interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
484			clocks = <&gcc GCC_QPIC_CLK>;
485			clock-names = "bam_clk";
486			#dma-cells = <1>;
487			qcom,ee = <0>;
488			status = "disabled";
489		};
490
491		nand: nand-controller@79b0000 {
492			compatible = "qcom,ipq4019-nand";
493			reg = <0x79b0000 0x1000>;
494			#address-cells = <1>;
495			#size-cells = <0>;
496			clocks = <&gcc GCC_QPIC_CLK>,
497				 <&gcc GCC_QPIC_AHB_CLK>;
498			clock-names = "core", "aon";
499
500			dmas = <&qpic_bam 0>,
501			       <&qpic_bam 1>,
502			       <&qpic_bam 2>;
503			dma-names = "tx", "rx", "cmd";
504			status = "disabled";
505
506			nand@0 {
507				reg = <0>;
508
509				nand-ecc-strength = <4>;
510				nand-ecc-step-size = <512>;
511				nand-bus-width = <8>;
512			};
513		};
514
515		wifi0: wifi@a000000 {
516			compatible = "qcom,ipq4019-wifi";
517			reg = <0xa000000 0x200000>;
518			resets = <&gcc WIFI0_CPU_INIT_RESET>,
519				 <&gcc WIFI0_RADIO_SRIF_RESET>,
520				 <&gcc WIFI0_RADIO_WARM_RESET>,
521				 <&gcc WIFI0_RADIO_COLD_RESET>,
522				 <&gcc WIFI0_CORE_WARM_RESET>,
523				 <&gcc WIFI0_CORE_COLD_RESET>;
524			reset-names = "wifi_cpu_init", "wifi_radio_srif",
525				      "wifi_radio_warm", "wifi_radio_cold",
526				      "wifi_core_warm", "wifi_core_cold";
527			clocks = <&gcc GCC_WCSS2G_CLK>,
528				 <&gcc GCC_WCSS2G_REF_CLK>,
529				 <&gcc GCC_WCSS2G_RTC_CLK>;
530			clock-names = "wifi_wcss_cmd", "wifi_wcss_ref",
531				      "wifi_wcss_rtc";
532			interrupts = <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>,
533				     <GIC_SPI 33 IRQ_TYPE_EDGE_RISING>,
534				     <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>,
535				     <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>,
536				     <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
537				     <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>,
538				     <GIC_SPI 38 IRQ_TYPE_EDGE_RISING>,
539				     <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>,
540				     <GIC_SPI 40 IRQ_TYPE_EDGE_RISING>,
541				     <GIC_SPI 41 IRQ_TYPE_EDGE_RISING>,
542				     <GIC_SPI 42 IRQ_TYPE_EDGE_RISING>,
543				     <GIC_SPI 43 IRQ_TYPE_EDGE_RISING>,
544				     <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>,
545				     <GIC_SPI 45 IRQ_TYPE_EDGE_RISING>,
546				     <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>,
547				     <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>,
548				     <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
549			interrupt-names = "msi0",  "msi1",  "msi2",  "msi3",
550					  "msi4",  "msi5",  "msi6",  "msi7",
551					  "msi8",  "msi9", "msi10", "msi11",
552					  "msi12", "msi13", "msi14", "msi15",
553					  "legacy";
554			status = "disabled";
555		};
556
557		wifi1: wifi@a800000 {
558			compatible = "qcom,ipq4019-wifi";
559			reg = <0xa800000 0x200000>;
560			resets = <&gcc WIFI1_CPU_INIT_RESET>,
561				 <&gcc WIFI1_RADIO_SRIF_RESET>,
562				 <&gcc WIFI1_RADIO_WARM_RESET>,
563				 <&gcc WIFI1_RADIO_COLD_RESET>,
564				 <&gcc WIFI1_CORE_WARM_RESET>,
565				 <&gcc WIFI1_CORE_COLD_RESET>;
566			reset-names = "wifi_cpu_init", "wifi_radio_srif",
567				      "wifi_radio_warm", "wifi_radio_cold",
568				      "wifi_core_warm", "wifi_core_cold";
569			clocks = <&gcc GCC_WCSS5G_CLK>,
570				 <&gcc GCC_WCSS5G_REF_CLK>,
571				 <&gcc GCC_WCSS5G_RTC_CLK>;
572			clock-names = "wifi_wcss_cmd", "wifi_wcss_ref",
573				      "wifi_wcss_rtc";
574			interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>,
575				     <GIC_SPI 49 IRQ_TYPE_EDGE_RISING>,
576				     <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>,
577				     <GIC_SPI 51 IRQ_TYPE_EDGE_RISING>,
578				     <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>,
579				     <GIC_SPI 53 IRQ_TYPE_EDGE_RISING>,
580				     <GIC_SPI 54 IRQ_TYPE_EDGE_RISING>,
581				     <GIC_SPI 55 IRQ_TYPE_EDGE_RISING>,
582				     <GIC_SPI 56 IRQ_TYPE_EDGE_RISING>,
583				     <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>,
584				     <GIC_SPI 58 IRQ_TYPE_EDGE_RISING>,
585				     <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>,
586				     <GIC_SPI 60 IRQ_TYPE_EDGE_RISING>,
587				     <GIC_SPI 61 IRQ_TYPE_EDGE_RISING>,
588				     <GIC_SPI 62 IRQ_TYPE_EDGE_RISING>,
589				     <GIC_SPI 63 IRQ_TYPE_EDGE_RISING>,
590				     <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
591			interrupt-names = "msi0",  "msi1",  "msi2",  "msi3",
592					  "msi4",  "msi5",  "msi6",  "msi7",
593					  "msi8",  "msi9", "msi10", "msi11",
594					  "msi12", "msi13", "msi14", "msi15",
595					  "legacy";
596			status = "disabled";
597		};
598
599		mdio: mdio@90000 {
600			#address-cells = <1>;
601			#size-cells = <0>;
602			compatible = "qcom,ipq4019-mdio";
603			reg = <0x90000 0x64>;
604			status = "disabled";
605
606			ethphy0: ethernet-phy@0 {
607				reg = <0>;
608			};
609
610			ethphy1: ethernet-phy@1 {
611				reg = <1>;
612			};
613
614			ethphy2: ethernet-phy@2 {
615				reg = <2>;
616			};
617
618			ethphy3: ethernet-phy@3 {
619				reg = <3>;
620			};
621
622			ethphy4: ethernet-phy@4 {
623				reg = <4>;
624			};
625		};
626
627		usb3_ss_phy: usb-phy@9a000 {
628			compatible = "qcom,usb-ss-ipq4019-phy";
629			#phy-cells = <0>;
630			reg = <0x9a000 0x800>;
631			reg-names = "phy_base";
632			resets = <&gcc USB3_UNIPHY_PHY_ARES>;
633			reset-names = "por_rst";
634			status = "disabled";
635		};
636
637		usb3_hs_phy: usb-phy@a6000 {
638			compatible = "qcom,usb-hs-ipq4019-phy";
639			#phy-cells = <0>;
640			reg = <0xa6000 0x40>;
641			reg-names = "phy_base";
642			resets = <&gcc USB3_HSPHY_POR_ARES>, <&gcc USB3_HSPHY_S_ARES>;
643			reset-names = "por_rst", "srif_rst";
644			status = "disabled";
645		};
646
647		usb3: usb@8af8800 {
648			compatible = "qcom,ipq4019-dwc3", "qcom,dwc3";
649			reg = <0x8af8800 0x100>;
650			#address-cells = <1>;
651			#size-cells = <1>;
652			clocks = <&gcc GCC_USB3_MASTER_CLK>,
653				 <&gcc GCC_USB3_SLEEP_CLK>,
654				 <&gcc GCC_USB3_MOCK_UTMI_CLK>;
655			clock-names = "core", "sleep", "mock_utmi";
656			ranges;
657			status = "disabled";
658
659			usb3_dwc: usb@8a00000 {
660				compatible = "snps,dwc3";
661				reg = <0x8a00000 0xf8000>;
662				interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
663				phys = <&usb3_hs_phy>, <&usb3_ss_phy>;
664				phy-names = "usb2-phy", "usb3-phy";
665				dr_mode = "host";
666			};
667		};
668
669		usb2_hs_phy: usb-phy@a8000 {
670			compatible = "qcom,usb-hs-ipq4019-phy";
671			#phy-cells = <0>;
672			reg = <0xa8000 0x40>;
673			reg-names = "phy_base";
674			resets = <&gcc USB2_HSPHY_POR_ARES>, <&gcc USB2_HSPHY_S_ARES>;
675			reset-names = "por_rst", "srif_rst";
676			status = "disabled";
677		};
678
679		usb2: usb@60f8800 {
680			compatible = "qcom,ipq4019-dwc3", "qcom,dwc3";
681			reg = <0x60f8800 0x100>;
682			#address-cells = <1>;
683			#size-cells = <1>;
684			clocks = <&gcc GCC_USB2_MASTER_CLK>,
685				 <&gcc GCC_USB2_SLEEP_CLK>,
686				 <&gcc GCC_USB2_MOCK_UTMI_CLK>;
687			clock-names = "master", "sleep", "mock_utmi";
688			ranges;
689			status = "disabled";
690
691			usb@6000000 {
692				compatible = "snps,dwc3";
693				reg = <0x6000000 0xf8000>;
694				interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
695				phys = <&usb2_hs_phy>;
696				phy-names = "usb2-phy";
697				dr_mode = "host";
698			};
699		};
700	};
701};
702