1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2018-2019 Intel Corporation */ 3 4 // clang-format off 5 // NOLINTBEGIN 6 7 #ifndef __PECI_IOCTL_H 8 #define __PECI_IOCTL_H 9 10 #ifdef __cplusplus 11 extern "C" { 12 #endif 13 14 #include <linux/ioctl.h> 15 #include <linux/types.h> 16 17 /* The PECI client's default address of 0x30 */ 18 #define PECI_BASE_ADDR 0x30 19 20 /* Max number of CPU clients */ 21 #define PECI_OFFSET_MAX 8 22 23 /* PECI read/write data buffer size max */ 24 #define PECI_BUFFER_SIZE 255 25 26 /* Device Specific Completion Code (CC) Definition */ 27 #define PECI_DEV_CC_SUCCESS 0x40 28 #define PECI_DEV_CC_NEED_RETRY 0x80 29 #define PECI_DEV_CC_OUT_OF_RESOURCE 0x81 30 #define PECI_DEV_CC_UNAVAIL_RESOURCE 0x82 31 #define PECI_DEV_CC_INVALID_REQ 0x90 32 #define PECI_DEV_CC_MCA_ERROR 0x91 33 #define PECI_DEV_CC_CATASTROPHIC_MCA_ERROR 0x93 34 #define PECI_DEV_CC_FATAL_MCA_DETECTED 0x94 35 #define PECI_DEV_CC_PARITY_ERROR_ON_GPSB_OR_PMSB 0x98 36 #define PECI_DEV_CC_PARITY_ERROR_ON_GPSB_OR_PMSB_IERR 0x9B 37 #define PECI_DEV_CC_PARITY_ERROR_ON_GPSB_OR_PMSB_MCA 0x9C 38 39 /* Completion Code mask to check retry needs */ 40 #define PECI_DEV_CC_RETRY_CHECK_MASK 0xf0 41 42 #define PECI_DEV_RETRY_TIMEOUT msecs_to_jiffies(700) 43 #define PECI_DEV_RETRY_INTERVAL_MIN_MSEC 1 44 #define PECI_DEV_RETRY_INTERVAL_MAX_MSEC 128 45 #define PECI_DEV_RETRY_BIT 0x01 46 47 /** 48 * enum peci_cmd - PECI client commands 49 * @PECI_CMD_XFER: raw PECI transfer 50 * @PECI_CMD_PING: ping, a required message for all PECI devices 51 * @PECI_CMD_GET_DIB: get DIB (Device Info Byte) 52 * @PECI_CMD_GET_TEMP: get maximum die temperature 53 * @PECI_CMD_RD_PKG_CFG: read access to the PCS (Package Configuration Space) 54 * @PECI_CMD_WR_PKG_CFG: write access to the PCS (Package Configuration Space) 55 * @PECI_CMD_RD_IA_MSR: read access to MSRs (Model Specific Registers) 56 * @PECI_CMD_WR_IA_MSR: write access to MSRs (Model Specific Registers) 57 * @PECI_CMD_RD_IA_MSREX: read access to MSRs (Model Specific Registers) 58 * @PECI_CMD_RD_PCI_CFG: sideband read access to the PCI configuration space 59 * maintained in downstream devices external to the processor 60 * @PECI_CMD_WR_PCI_CFG: sideband write access to the PCI configuration space 61 * maintained in downstream devices external to the processor 62 * @PECI_CMD_RD_PCI_CFG_LOCAL: sideband read access to the PCI configuration 63 * space that resides within the processor 64 * @PECI_CMD_WR_PCI_CFG_LOCAL: sideband write access to the PCI configuration 65 * space that resides within the processor 66 * 67 * Available commands depend on client's PECI revision. 68 */ 69 enum peci_cmd { 70 PECI_CMD_XFER = 0, 71 PECI_CMD_PING, 72 PECI_CMD_GET_DIB, 73 PECI_CMD_GET_TEMP, 74 PECI_CMD_RD_PKG_CFG, 75 PECI_CMD_WR_PKG_CFG, 76 PECI_CMD_RD_IA_MSR, 77 PECI_CMD_WR_IA_MSR, 78 PECI_CMD_RD_IA_MSREX, 79 PECI_CMD_RD_PCI_CFG, 80 PECI_CMD_WR_PCI_CFG, 81 PECI_CMD_RD_PCI_CFG_LOCAL, 82 PECI_CMD_WR_PCI_CFG_LOCAL, 83 PECI_CMD_RD_END_PT_CFG, 84 PECI_CMD_WR_END_PT_CFG, 85 PECI_CMD_CRASHDUMP_DISC, 86 PECI_CMD_CRASHDUMP_GET_FRAME, 87 PECI_CMD_MAX 88 }; 89 90 /** 91 * struct peci_xfer_msg - raw PECI transfer command 92 * @addr; address of the client 93 * @tx_len: number of data to be written in bytes 94 * @rx_len: number of data to be read in bytes 95 * @tx_buf: data to be written, or NULL 96 * @rx_buf: data to be read, or NULL 97 * 98 * raw PECI transfer 99 */ 100 struct peci_xfer_msg { 101 __u8 addr; 102 __u8 tx_len; 103 __u8 rx_len; 104 __u8 padding; 105 __u8 *tx_buf; 106 __u8 *rx_buf; 107 } __attribute__((__packed__)); 108 109 /** 110 * struct peci_ping_msg - ping command 111 * @addr: address of the client 112 * 113 * Ping() is a required message for all PECI devices. This message is used to 114 * enumerate devices or determine if a device has been removed, been 115 * powered-off, etc. 116 */ 117 struct peci_ping_msg { 118 __u8 addr; 119 __u8 padding[3]; 120 } __attribute__((__packed__)); 121 122 /** 123 * struct peci_get_dib_msg - GetDIB command 124 * @addr: address of the client 125 * @dib: DIB data to be read 126 * 127 * The processor PECI client implementation of GetDIB() includes an 8-byte 128 * response and provides information regarding client revision number and the 129 * number of supported domains. All processor PECI clients support the GetDIB() 130 * command. 131 */ 132 struct peci_get_dib_msg { 133 #define PECI_GET_DIB_WR_LEN 1 134 #define PECI_GET_DIB_RD_LEN 8 135 #define PECI_GET_DIB_CMD 0xf7 136 137 __u8 addr; 138 __u8 padding[3]; 139 __u64 dib; 140 } __attribute__((__packed__)); 141 142 /** 143 * struct peci_get_temp_msg - GetTemp command 144 * @addr: address of the client 145 * @temp_raw: raw temperature data to be read 146 * 147 * The GetTemp() command is used to retrieve the maximum die temperature from a 148 * target PECI address. The temperature is used by the external thermal 149 * management system to regulate the temperature on the die. The data is 150 * returned as a negative value representing the number of degrees centigrade 151 * below the maximum processor junction temperature. 152 */ 153 struct peci_get_temp_msg { 154 #define PECI_GET_TEMP_WR_LEN 1 155 #define PECI_GET_TEMP_RD_LEN 2 156 #define PECI_GET_TEMP_CMD 0x01 157 158 __u8 addr; 159 __u8 padding; 160 __s16 temp_raw; 161 } __attribute__((__packed__)); 162 163 /** 164 * struct peci_rd_pkg_cfg_msg - RdPkgConfig command 165 * @addr: address of the client 166 * @index: encoding index for the requested service 167 * @param: specific data being requested 168 * @rx_len: number of data to be read in bytes 169 * @cc: completion code 170 * @pkg_config: package config data to be read 171 * 172 * The RdPkgConfig() command provides read access to the Package Configuration 173 * Space (PCS) within the processor, including various power and thermal 174 * management functions. Typical PCS read services supported by the processor 175 * may include access to temperature data, energy status, run time information, 176 * DIMM temperatures and so on. 177 */ 178 struct peci_rd_pkg_cfg_msg { 179 #define PECI_RDPKGCFG_WRITE_LEN 5 180 #define PECI_RDPKGCFG_READ_LEN_BASE 1 181 #define PECI_RDPKGCFG_CMD 0xa1 182 183 __u8 addr; 184 __u8 index; 185 #define PECI_MBX_INDEX_CPU_ID 0 /* Package Identifier Read */ 186 #define PECI_MBX_INDEX_VR_DEBUG 1 /* VR Debug */ 187 #define PECI_MBX_INDEX_PKG_TEMP_READ 2 /* Package Temperature Read */ 188 #define PECI_MBX_INDEX_ENERGY_COUNTER 3 /* Energy counter */ 189 #define PECI_MBX_INDEX_ENERGY_STATUS 4 /* DDR Energy Status */ 190 #define PECI_MBX_INDEX_WAKE_MODE_BIT 5 /* "Wake on PECI" Mode bit */ 191 #define PECI_MBX_INDEX_EPI 6 /* Efficient Performance Indication */ 192 #define PECI_MBX_INDEX_PKG_RAPL_PERF 8 /* Pkg RAPL Performance Status Read */ 193 #define PECI_MBX_INDEX_PER_CORE_DTS_TEMP 9 /* Per Core DTS Temperature Read */ 194 #define PECI_MBX_INDEX_DTS_MARGIN 10 /* DTS thermal margin */ 195 #define PECI_MBX_INDEX_SKT_PWR_THRTL_DUR 11 /* Socket Power Throttled Duration */ 196 #define PECI_MBX_INDEX_CFG_TDP_CONTROL 12 /* TDP Config Control */ 197 #define PECI_MBX_INDEX_CFG_TDP_LEVELS 13 /* TDP Config Levels */ 198 #define PECI_MBX_INDEX_DDR_DIMM_TEMP 14 /* DDR DIMM Temperature */ 199 #define PECI_MBX_INDEX_CFG_ICCMAX 15 /* Configurable ICCMAX */ 200 #define PECI_MBX_INDEX_TEMP_TARGET 16 /* Temperature Target Read */ 201 #define PECI_MBX_INDEX_CURR_CFG_LIMIT 17 /* Current Config Limit */ 202 #define PECI_MBX_INDEX_DIMM_TEMP_READ 20 /* Package Thermal Status Read */ 203 #define PECI_MBX_INDEX_DRAM_IMC_TMP_READ 22 /* DRAM IMC Temperature Read */ 204 #define PECI_MBX_INDEX_DDR_CH_THERM_STAT 23 /* DDR Channel Thermal Status */ 205 #define PECI_MBX_INDEX_PKG_POWER_LIMIT1 26 /* Package Power Limit1 */ 206 #define PECI_MBX_INDEX_PKG_POWER_LIMIT2 27 /* Package Power Limit2 */ 207 #define PECI_MBX_INDEX_TDP 28 /* Thermal design power minimum */ 208 #define PECI_MBX_INDEX_TDP_HIGH 29 /* Thermal design power maximum */ 209 #define PECI_MBX_INDEX_TDP_UNITS 30 /* Units for power/energy registers */ 210 #define PECI_MBX_INDEX_RUN_TIME 31 /* Accumulated Run Time */ 211 #define PECI_MBX_INDEX_CONSTRAINED_TIME 32 /* Thermally Constrained Time Read */ 212 #define PECI_MBX_INDEX_TURBO_RATIO 33 /* Turbo Activation Ratio */ 213 #define PECI_MBX_INDEX_DDR_RAPL_PL1 34 /* DDR RAPL PL1 */ 214 #define PECI_MBX_INDEX_DDR_PWR_INFO_HIGH 35 /* DRAM Power Info Read (high) */ 215 #define PECI_MBX_INDEX_DDR_PWR_INFO_LOW 36 /* DRAM Power Info Read (low) */ 216 #define PECI_MBX_INDEX_DDR_RAPL_PL2 37 /* DDR RAPL PL2 */ 217 #define PECI_MBX_INDEX_DDR_RAPL_STATUS 38 /* DDR RAPL Performance Status */ 218 #define PECI_MBX_INDEX_DDR_HOT_ABSOLUTE 43 /* DDR Hottest Dimm Absolute Temp */ 219 #define PECI_MBX_INDEX_DDR_HOT_RELATIVE 44 /* DDR Hottest Dimm Relative Temp */ 220 #define PECI_MBX_INDEX_DDR_THROTTLE_TIME 45 /* DDR Throttle Time */ 221 #define PECI_MBX_INDEX_DDR_THERM_STATUS 46 /* DDR Thermal Status */ 222 #define PECI_MBX_INDEX_TIME_AVG_TEMP 47 /* Package time-averaged temperature */ 223 #define PECI_MBX_INDEX_TURBO_RATIO_LIMIT 49 /* Turbo Ratio Limit Read */ 224 #define PECI_MBX_INDEX_HWP_AUTO_OOB 53 /* HWP Autonomous Out-of-band */ 225 #define PECI_MBX_INDEX_DDR_WARM_BUDGET 55 /* DDR Warm Power Budget */ 226 #define PECI_MBX_INDEX_DDR_HOT_BUDGET 56 /* DDR Hot Power Budget */ 227 #define PECI_MBX_INDEX_PKG_PSYS_PWR_LIM3 57 /* Package/Psys Power Limit3 */ 228 #define PECI_MBX_INDEX_PKG_PSYS_PWR_LIM1 58 /* Package/Psys Power Limit1 */ 229 #define PECI_MBX_INDEX_PKG_PSYS_PWR_LIM2 59 /* Package/Psys Power Limit2 */ 230 #define PECI_MBX_INDEX_PKG_PSYS_PWR_LIM4 60 /* Package/Psys Power Limit4 */ 231 #define PECI_MBX_INDEX_PERF_LIMIT_REASON 65 /* Performance Limit Reasons */ 232 233 __u16 param; 234 /* When index is PECI_MBX_INDEX_CPU_ID */ 235 #define PECI_PKG_ID_CPU_ID 0x0000 /* CPUID Info */ 236 #define PECI_PKG_ID_PLATFORM_ID 0x0001 /* Platform ID */ 237 #define PECI_PKG_ID_UNCORE_ID 0x0002 /* Uncore Device ID */ 238 #define PECI_PKG_ID_MAX_THREAD_ID 0x0003 /* Max Thread ID */ 239 #define PECI_PKG_ID_MICROCODE_REV 0x0004 /* CPU Microcode Update Revision */ 240 #define PECI_PKG_ID_MACHINE_CHECK_STATUS 0x0005 /* Machine Check Status */ 241 242 __u8 rx_len; 243 __u8 cc; 244 __u8 padding[2]; 245 __u8 pkg_config[4]; 246 } __attribute__((__packed__)); 247 248 /** 249 * struct peci_wr_pkg_cfg_msg - WrPkgConfig command 250 * @addr: address of the client 251 * @index: encoding index for the requested service 252 * @param: specific data being requested 253 * @tx_len: number of data to be written in bytes 254 * @cc: completion code 255 * @value: package config data to be written 256 * 257 * The WrPkgConfig() command provides write access to the Package Configuration 258 * Space (PCS) within the processor, including various power and thermal 259 * management functions. Typical PCS write services supported by the processor 260 * may include power limiting, thermal averaging constant programming and so 261 * on. 262 */ 263 struct peci_wr_pkg_cfg_msg { 264 #define PECI_WRPKGCFG_WRITE_LEN_BASE 6 265 #define PECI_WRPKGCFG_READ_LEN 1 266 #define PECI_WRPKGCFG_CMD 0xa5 267 268 __u8 addr; 269 __u8 index; 270 #define PECI_MBX_INDEX_DIMM_AMBIENT 19 271 #define PECI_MBX_INDEX_DIMM_TEMP 24 272 273 __u16 param; 274 __u8 tx_len; 275 __u8 cc; 276 __u8 padding[2]; 277 __u32 value; 278 } __attribute__((__packed__)); 279 280 /** 281 * struct peci_rd_ia_msr_msg - RdIAMSR command 282 * @addr: address of the client 283 * @thread_id: ID of the specific logical processor 284 * @address: address of MSR to read from 285 * @cc: completion code 286 * @value: data to be read 287 * 288 * The RdIAMSR() PECI command provides read access to Model Specific Registers 289 * (MSRs) defined in the processor's Intel Architecture (IA). 290 */ 291 struct peci_rd_ia_msr_msg { 292 #define PECI_RDIAMSR_WRITE_LEN 5 293 #define PECI_RDIAMSR_READ_LEN 9 294 #define PECI_RDIAMSR_CMD 0xb1 295 296 __u8 addr; 297 __u8 thread_id; 298 __u16 address; 299 __u8 cc; 300 __u8 padding[3]; 301 __u64 value; 302 } __attribute__((__packed__)); 303 304 /** 305 * struct peci_wr_ia_msr_msg - WrIAMSR command 306 * @addr: address of the client 307 * @thread_id: ID of the specific logical processor 308 * @address: address of MSR to write to 309 * @tx_len: number of data to be written in bytes 310 * @cc: completion code 311 * @value: data to be written 312 * 313 * The WrIAMSR() PECI command provides write access to Model Specific Registers 314 * (MSRs) defined in the processor's Intel Architecture (IA). 315 */ 316 struct peci_wr_ia_msr_msg { 317 #define PECI_WRIAMSR_CMD 0xb5 318 319 __u8 addr; 320 __u8 thread_id; 321 __u16 address; 322 __u8 tx_len; 323 __u8 cc; 324 __u8 padding[2]; 325 __u64 value; 326 } __attribute__((__packed__)); 327 328 /** 329 * struct peci_rd_ia_msrex_msg - RdIAMSREX command 330 * @addr: address of the client 331 * @thread_id: ID of the specific logical processor 332 * @address: address of MSR to read from 333 * @cc: completion code 334 * @value: data to be read 335 * 336 * The RdIAMSREX() PECI command provides read access to Model Specific 337 * Registers (MSRs) defined in the processor's Intel Architecture (IA). 338 * The differences between RdIAMSREX() and RdIAMSR() are that: 339 * (1)RdIAMSR() can only read MC registers, RdIAMSREX() can read all MSRs 340 * (2)thread_id of RdIAMSR() is u8, thread_id of RdIAMSREX() is u16 341 */ 342 struct peci_rd_ia_msrex_msg { 343 #define PECI_RDIAMSREX_WRITE_LEN 6 344 #define PECI_RDIAMSREX_READ_LEN 9 345 #define PECI_RDIAMSREX_CMD 0xd1 346 347 __u8 addr; 348 __u8 padding0; 349 __u16 thread_id; 350 __u16 address; 351 __u8 cc; 352 __u8 padding1; 353 __u64 value; 354 } __attribute__((__packed__)); 355 356 /** 357 * struct peci_rd_pci_cfg_msg - RdPCIConfig command 358 * @addr: address of the client 359 * @bus: PCI bus number 360 * @device: PCI device number 361 * @function: specific function to read from 362 * @reg: specific register to read from 363 * @cc: completion code 364 * @pci_config: config data to be read 365 * 366 * The RdPCIConfig() command provides sideband read access to the PCI 367 * configuration space maintained in downstream devices external to the 368 * processor. 369 */ 370 struct peci_rd_pci_cfg_msg { 371 #define PECI_RDPCICFG_WRITE_LEN 6 372 #define PECI_RDPCICFG_READ_LEN 5 373 #define PECI_RDPCICFG_READ_LEN_MAX 24 374 #define PECI_RDPCICFG_CMD 0x61 375 376 __u8 addr; 377 __u8 bus; 378 #define PECI_PCI_BUS0_CPU0 0x00 379 #define PECI_PCI_BUS0_CPU1 0x80 380 #define PECI_PCI_CPUBUSNO_BUS 0x00 381 #define PECI_PCI_CPUBUSNO_DEV 0x08 382 #define PECI_PCI_CPUBUSNO_FUNC 0x02 383 #define PECI_PCI_CPUBUSNO 0xcc 384 #define PECI_PCI_CPUBUSNO_1 0xd0 385 #define PECI_PCI_CPUBUSNO_VALID 0xd4 386 387 __u8 device; 388 __u8 function; 389 __u16 reg; 390 __u8 cc; 391 __u8 padding[1]; 392 __u8 pci_config[4]; 393 } __attribute__((__packed__)); 394 395 /** 396 * struct peci_wr_pci_cfg_msg - WrPCIConfig command 397 * @addr: address of the client 398 * @bus: PCI bus number 399 * @device: PCI device number 400 * @function: specific function to write to 401 * @reg: specific register to write to 402 * @tx_len: number of data to be written in bytes 403 * @cc: completion code 404 * @pci_config: config data to be written 405 * 406 * The RdPCIConfig() command provides sideband write access to the PCI 407 * configuration space maintained in downstream devices external to the 408 * processor. 409 */ 410 struct peci_wr_pci_cfg_msg { 411 #define PECI_WRPCICFG_CMD 0x65 412 413 __u8 addr; 414 __u8 bus; 415 __u8 device; 416 __u8 function; 417 __u16 reg; 418 __u8 tx_len; 419 __u8 cc; 420 __u8 pci_config[4]; 421 } __attribute__((__packed__)); 422 423 /** 424 * struct peci_rd_pci_cfg_local_msg - RdPCIConfigLocal command 425 * @addr: address of the client 426 * @bus: PCI bus number 427 * @device: PCI device number 428 * @function: specific function to read from 429 * @reg: specific register to read from 430 * @rx_len: number of data to be read in bytes 431 * @cc: completion code 432 * @pci_config: config data to be read 433 * 434 * The RdPCIConfigLocal() command provides sideband read access to the PCI 435 * configuration space that resides within the processor. This includes all 436 * processor IIO and uncore registers within the PCI configuration space. 437 */ 438 struct peci_rd_pci_cfg_local_msg { 439 #define PECI_RDPCICFGLOCAL_WRITE_LEN 5 440 #define PECI_RDPCICFGLOCAL_READ_LEN_BASE 1 441 #define PECI_RDPCICFGLOCAL_CMD 0xe1 442 443 __u8 addr; 444 __u8 bus; 445 __u8 device; 446 __u8 function; 447 __u16 reg; 448 __u8 rx_len; 449 __u8 cc; 450 __u8 pci_config[4]; 451 } __attribute__((__packed__)); 452 453 /** 454 * struct peci_wr_pci_cfg_local_msg - WrPCIConfigLocal command 455 * @addr: address of the client 456 * @bus: PCI bus number 457 * @device: PCI device number 458 * @function: specific function to read from 459 * @reg: specific register to read from 460 * @tx_len: number of data to be written in bytes 461 * @cc: completion code 462 * @value: config data to be written 463 * 464 * The WrPCIConfigLocal() command provides sideband write access to the PCI 465 * configuration space that resides within the processor. PECI originators can 466 * access this space even before BIOS enumeration of the system buses. 467 */ 468 struct peci_wr_pci_cfg_local_msg { 469 #define PECI_WRPCICFGLOCAL_WRITE_LEN_BASE 6 470 #define PECI_WRPCICFGLOCAL_READ_LEN 1 471 #define PECI_WRPCICFGLOCAL_CMD 0xe5 472 473 __u8 addr; 474 __u8 bus; 475 __u8 device; 476 __u8 function; 477 __u16 reg; 478 __u8 tx_len; 479 __u8 cc; 480 __u32 value; 481 } __attribute__((__packed__)); 482 483 struct peci_rd_end_pt_cfg_msg { 484 #define PECI_RDENDPTCFG_PCI_WRITE_LEN 12 485 #define PECI_RDENDPTCFG_MMIO_D_WRITE_LEN 14 486 #define PECI_RDENDPTCFG_MMIO_Q_WRITE_LEN 18 487 #define PECI_RDENDPTCFG_READ_LEN_BASE 1 488 #define PECI_RDENDPTCFG_CMD 0xc1 489 490 __u8 addr; 491 __u8 msg_type; 492 #define PECI_ENDPTCFG_TYPE_LOCAL_PCI 0x03 493 #define PECI_ENDPTCFG_TYPE_PCI 0x04 494 #define PECI_ENDPTCFG_TYPE_MMIO 0x05 495 496 union { 497 struct { 498 __u8 seg; 499 __u8 bus; 500 __u8 device; 501 __u8 function; 502 __u16 reg; 503 } pci_cfg; 504 struct { 505 __u8 seg; 506 __u8 bus; 507 __u8 device; 508 __u8 function; 509 __u8 bar; 510 __u8 addr_type; 511 #define PECI_ENDPTCFG_ADDR_TYPE_PCI 0x04 512 #define PECI_ENDPTCFG_ADDR_TYPE_MMIO_D 0x05 513 #define PECI_ENDPTCFG_ADDR_TYPE_MMIO_Q 0x06 514 515 __u64 offset; 516 } mmio; 517 } params; 518 __u8 rx_len; 519 __u8 cc; 520 __u8 padding[2]; 521 __u8 data[8]; 522 } __attribute__((__packed__)); 523 524 struct peci_wr_end_pt_cfg_msg { 525 #define PECI_WRENDPTCFG_PCI_WRITE_LEN_BASE 13 526 #define PECI_WRENDPTCFG_MMIO_D_WRITE_LEN_BASE 15 527 #define PECI_WRENDPTCFG_MMIO_Q_WRITE_LEN_BASE 19 528 #define PECI_WRENDPTCFG_READ_LEN 1 529 #define PECI_WRENDPTCFG_CMD 0xc5 530 531 __u8 addr; 532 __u8 msg_type; 533 /* See msg_type in struct peci_rd_end_pt_cfg_msg */ 534 535 union { 536 struct { 537 __u8 seg; 538 __u8 bus; 539 __u8 device; 540 __u8 function; 541 __u16 reg; 542 } pci_cfg; 543 struct { 544 __u8 seg; 545 __u8 bus; 546 __u8 device; 547 __u8 function; 548 __u8 bar; 549 __u8 addr_type; 550 /* See addr_type in struct peci_rd_end_pt_cfg_msg */ 551 552 __u64 offset; 553 } mmio; 554 } params; 555 __u8 tx_len; 556 __u8 cc; 557 __u8 padding[2]; 558 __u64 value; 559 } __attribute__((__packed__)); 560 561 /* Crashdump Agent */ 562 #define PECI_CRASHDUMP_CORE 0x00 563 #define PECI_CRASHDUMP_TOR 0x01 564 565 /* Crashdump Agent Param */ 566 #define PECI_CRASHDUMP_PAYLOAD_SIZE 0x00 567 568 /* Crashdump Agent Data Param */ 569 #define PECI_CRASHDUMP_AGENT_ID 0x00 570 #define PECI_CRASHDUMP_AGENT_PARAM 0x01 571 572 struct peci_crashdump_disc_msg { 573 __u8 addr; 574 __u8 subopcode; 575 #define PECI_CRASHDUMP_ENABLED 0x00 576 #define PECI_CRASHDUMP_NUM_AGENTS 0x01 577 #define PECI_CRASHDUMP_AGENT_DATA 0x02 578 579 __u8 cc; 580 __u8 param0; 581 __u16 param1; 582 __u8 param2; 583 __u8 rx_len; 584 __u8 data[8]; 585 } __attribute__((__packed__)); 586 587 struct peci_crashdump_get_frame_msg { 588 #define PECI_CRASHDUMP_DISC_WRITE_LEN 9 589 #define PECI_CRASHDUMP_DISC_READ_LEN_BASE 1 590 #define PECI_CRASHDUMP_DISC_VERSION 0 591 #define PECI_CRASHDUMP_DISC_OPCODE 1 592 #define PECI_CRASHDUMP_GET_FRAME_WRITE_LEN 10 593 #define PECI_CRASHDUMP_GET_FRAME_READ_LEN_BASE 1 594 #define PECI_CRASHDUMP_GET_FRAME_VERSION 0 595 #define PECI_CRASHDUMP_GET_FRAME_OPCODE 3 596 #define PECI_CRASHDUMP_CMD 0x71 597 598 __u8 addr; 599 __u8 padding0; 600 __u16 param0; 601 __u16 param1; 602 __u16 param2; 603 __u8 rx_len; 604 __u8 cc; 605 __u8 padding1[2]; 606 __u8 data[16]; 607 } __attribute__((__packed__)); 608 609 #define PECI_IOC_BASE 0xb7 610 611 #define PECI_IOC_XFER \ 612 _IOWR(PECI_IOC_BASE, PECI_CMD_XFER, struct peci_xfer_msg) 613 614 #define PECI_IOC_PING \ 615 _IOWR(PECI_IOC_BASE, PECI_CMD_PING, struct peci_ping_msg) 616 617 #define PECI_IOC_GET_DIB \ 618 _IOWR(PECI_IOC_BASE, PECI_CMD_GET_DIB, struct peci_get_dib_msg) 619 620 #define PECI_IOC_GET_TEMP \ 621 _IOWR(PECI_IOC_BASE, PECI_CMD_GET_TEMP, struct peci_get_temp_msg) 622 623 #define PECI_IOC_RD_PKG_CFG \ 624 _IOWR(PECI_IOC_BASE, PECI_CMD_RD_PKG_CFG, struct peci_rd_pkg_cfg_msg) 625 626 #define PECI_IOC_WR_PKG_CFG \ 627 _IOWR(PECI_IOC_BASE, PECI_CMD_WR_PKG_CFG, struct peci_wr_pkg_cfg_msg) 628 629 #define PECI_IOC_RD_IA_MSR \ 630 _IOWR(PECI_IOC_BASE, PECI_CMD_RD_IA_MSR, struct peci_rd_ia_msr_msg) 631 632 #define PECI_IOC_WR_IA_MSR \ 633 _IOWR(PECI_IOC_BASE, PECI_CMD_WR_IA_MSR, struct peci_wr_ia_msr_msg) 634 635 #define PECI_IOC_RD_IA_MSREX \ 636 _IOWR(PECI_IOC_BASE, PECI_CMD_RD_IA_MSREX, struct peci_rd_ia_msrex_msg) 637 638 #define PECI_IOC_RD_PCI_CFG \ 639 _IOWR(PECI_IOC_BASE, PECI_CMD_RD_PCI_CFG, struct peci_rd_pci_cfg_msg) 640 641 #define PECI_IOC_WR_PCI_CFG \ 642 _IOWR(PECI_IOC_BASE, PECI_CMD_WR_PCI_CFG, struct peci_wr_pci_cfg_msg) 643 644 #define PECI_IOC_RD_PCI_CFG_LOCAL \ 645 _IOWR(PECI_IOC_BASE, PECI_CMD_RD_PCI_CFG_LOCAL, \ 646 struct peci_rd_pci_cfg_local_msg) 647 648 #define PECI_IOC_WR_PCI_CFG_LOCAL \ 649 _IOWR(PECI_IOC_BASE, PECI_CMD_WR_PCI_CFG_LOCAL, \ 650 struct peci_wr_pci_cfg_local_msg) 651 652 #define PECI_IOC_RD_END_PT_CFG \ 653 _IOWR(PECI_IOC_BASE, PECI_CMD_RD_END_PT_CFG, \ 654 struct peci_rd_end_pt_cfg_msg) 655 656 #define PECI_IOC_WR_END_PT_CFG \ 657 _IOWR(PECI_IOC_BASE, PECI_CMD_WR_END_PT_CFG, \ 658 struct peci_wr_end_pt_cfg_msg) 659 660 #define PECI_IOC_CRASHDUMP_DISC \ 661 _IOWR(PECI_IOC_BASE, PECI_CMD_CRASHDUMP_DISC, \ 662 struct peci_crashdump_disc_msg) 663 664 #define PECI_IOC_CRASHDUMP_GET_FRAME \ 665 _IOWR(PECI_IOC_BASE, PECI_CMD_CRASHDUMP_GET_FRAME, \ 666 struct peci_crashdump_get_frame_msg) 667 668 #ifdef __cplusplus 669 } 670 #endif 671 672 #endif /* __PECI_IOCTL_H */ 673 674 // NOLINTEND 675 // clang-format on 676