1 /* SPDX-License-Identifier: GPL-2.0 2 * 3 * Copyright 2016-2020 HabanaLabs, Ltd. 4 * All Rights Reserved. 5 * 6 */ 7 8 /************************************ 9 ** This is an auto-generated file ** 10 ** DO NOT EDIT BELOW ** 11 ************************************/ 12 13 #ifndef ASIC_REG_PCIE_WRAP_SPECIAL_REGS_H_ 14 #define ASIC_REG_PCIE_WRAP_SPECIAL_REGS_H_ 15 16 /* 17 ***************************************** 18 * PCIE_WRAP_SPECIAL 19 * (Prototype: SPECIAL_REGS) 20 ***************************************** 21 */ 22 23 #define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_0 0x4C01E80 24 25 #define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_1 0x4C01E84 26 27 #define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_2 0x4C01E88 28 29 #define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_3 0x4C01E8C 30 31 #define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_4 0x4C01E90 32 33 #define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_5 0x4C01E94 34 35 #define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_6 0x4C01E98 36 37 #define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_7 0x4C01E9C 38 39 #define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_8 0x4C01EA0 40 41 #define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_9 0x4C01EA4 42 43 #define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_10 0x4C01EA8 44 45 #define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_11 0x4C01EAC 46 47 #define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_12 0x4C01EB0 48 49 #define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_13 0x4C01EB4 50 51 #define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_14 0x4C01EB8 52 53 #define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_15 0x4C01EBC 54 55 #define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_16 0x4C01EC0 56 57 #define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_17 0x4C01EC4 58 59 #define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_18 0x4C01EC8 60 61 #define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_19 0x4C01ECC 62 63 #define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_20 0x4C01ED0 64 65 #define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_21 0x4C01ED4 66 67 #define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_22 0x4C01ED8 68 69 #define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_23 0x4C01EDC 70 71 #define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_24 0x4C01EE0 72 73 #define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_25 0x4C01EE4 74 75 #define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_26 0x4C01EE8 76 77 #define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_27 0x4C01EEC 78 79 #define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_28 0x4C01EF0 80 81 #define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_29 0x4C01EF4 82 83 #define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_30 0x4C01EF8 84 85 #define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_31 0x4C01EFC 86 87 #define mmPCIE_WRAP_SPECIAL_MEM_GW_DATA 0x4C01F00 88 89 #define mmPCIE_WRAP_SPECIAL_MEM_GW_REQ 0x4C01F04 90 91 #define mmPCIE_WRAP_SPECIAL_MEM_NUMOF 0x4C01F0C 92 93 #define mmPCIE_WRAP_SPECIAL_MEM_ECC_SEL 0x4C01F10 94 95 #define mmPCIE_WRAP_SPECIAL_MEM_ECC_CTL 0x4C01F14 96 97 #define mmPCIE_WRAP_SPECIAL_MEM_ECC_ERR_MASK 0x4C01F18 98 99 #define mmPCIE_WRAP_SPECIAL_MEM_ECC_GLBL_ERR_MASK 0x4C01F1C 100 101 #define mmPCIE_WRAP_SPECIAL_MEM_ECC_ERR_STS 0x4C01F20 102 103 #define mmPCIE_WRAP_SPECIAL_MEM_ECC_ERR_ADDR 0x4C01F24 104 105 #define mmPCIE_WRAP_SPECIAL_MEM_RM 0x4C01F28 106 107 #define mmPCIE_WRAP_SPECIAL_GLBL_ERR_MASK 0x4C01F40 108 109 #define mmPCIE_WRAP_SPECIAL_GLBL_ERR_ADDR 0x4C01F44 110 111 #define mmPCIE_WRAP_SPECIAL_GLBL_ERR_CAUSE 0x4C01F48 112 113 #define mmPCIE_WRAP_SPECIAL_GLBL_SPARE_0 0x4C01F60 114 115 #define mmPCIE_WRAP_SPECIAL_GLBL_SPARE_1 0x4C01F64 116 117 #define mmPCIE_WRAP_SPECIAL_GLBL_SPARE_2 0x4C01F68 118 119 #define mmPCIE_WRAP_SPECIAL_GLBL_SPARE_3 0x4C01F6C 120 121 #define mmPCIE_WRAP_SPECIAL_GLBL_SEC_0 0x4C01F80 122 123 #define mmPCIE_WRAP_SPECIAL_GLBL_SEC_1 0x4C01F84 124 125 #define mmPCIE_WRAP_SPECIAL_GLBL_SEC_2 0x4C01F88 126 127 #define mmPCIE_WRAP_SPECIAL_GLBL_SEC_3 0x4C01F8C 128 129 #define mmPCIE_WRAP_SPECIAL_GLBL_SEC_4 0x4C01F90 130 131 #define mmPCIE_WRAP_SPECIAL_GLBL_SEC_5 0x4C01F94 132 133 #define mmPCIE_WRAP_SPECIAL_GLBL_SEC_6 0x4C01F98 134 135 #define mmPCIE_WRAP_SPECIAL_GLBL_SEC_7 0x4C01F9C 136 137 #define mmPCIE_WRAP_SPECIAL_GLBL_SEC_8 0x4C01FA0 138 139 #define mmPCIE_WRAP_SPECIAL_GLBL_SEC_9 0x4C01FA4 140 141 #define mmPCIE_WRAP_SPECIAL_GLBL_SEC_10 0x4C01FA8 142 143 #define mmPCIE_WRAP_SPECIAL_GLBL_SEC_11 0x4C01FAC 144 145 #define mmPCIE_WRAP_SPECIAL_GLBL_SEC_12 0x4C01FB0 146 147 #define mmPCIE_WRAP_SPECIAL_GLBL_SEC_13 0x4C01FB4 148 149 #define mmPCIE_WRAP_SPECIAL_GLBL_SEC_14 0x4C01FB8 150 151 #define mmPCIE_WRAP_SPECIAL_GLBL_SEC_15 0x4C01FBC 152 153 #define mmPCIE_WRAP_SPECIAL_GLBL_SEC_16 0x4C01FC0 154 155 #define mmPCIE_WRAP_SPECIAL_GLBL_SEC_17 0x4C01FC4 156 157 #define mmPCIE_WRAP_SPECIAL_GLBL_SEC_18 0x4C01FC8 158 159 #define mmPCIE_WRAP_SPECIAL_GLBL_SEC_19 0x4C01FCC 160 161 #define mmPCIE_WRAP_SPECIAL_GLBL_SEC_20 0x4C01FD0 162 163 #define mmPCIE_WRAP_SPECIAL_GLBL_SEC_21 0x4C01FD4 164 165 #define mmPCIE_WRAP_SPECIAL_GLBL_SEC_22 0x4C01FD8 166 167 #define mmPCIE_WRAP_SPECIAL_GLBL_SEC_23 0x4C01FDC 168 169 #define mmPCIE_WRAP_SPECIAL_GLBL_SEC_24 0x4C01FE0 170 171 #define mmPCIE_WRAP_SPECIAL_GLBL_SEC_25 0x4C01FE4 172 173 #define mmPCIE_WRAP_SPECIAL_GLBL_SEC_26 0x4C01FE8 174 175 #define mmPCIE_WRAP_SPECIAL_GLBL_SEC_27 0x4C01FEC 176 177 #define mmPCIE_WRAP_SPECIAL_GLBL_SEC_28 0x4C01FF0 178 179 #define mmPCIE_WRAP_SPECIAL_GLBL_SEC_29 0x4C01FF4 180 181 #define mmPCIE_WRAP_SPECIAL_GLBL_SEC_30 0x4C01FF8 182 183 #define mmPCIE_WRAP_SPECIAL_GLBL_SEC_31 0x4C01FFC 184 185 #endif /* ASIC_REG_PCIE_WRAP_SPECIAL_REGS_H_ */ 186