xref: /openbmc/linux/drivers/acpi/pci_mcfg.c (revision cd89edda)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (C) 2016 Broadcom
4  *	Author: Jayachandran C <jchandra@broadcom.com>
5  * Copyright (C) 2016 Semihalf
6  * 	Author: Tomasz Nowicki <tn@semihalf.com>
7  */
8 
9 #define pr_fmt(fmt) "ACPI: " fmt
10 
11 #include <linux/kernel.h>
12 #include <linux/pci.h>
13 #include <linux/pci-acpi.h>
14 #include <linux/pci-ecam.h>
15 
16 /* Structure to hold entries from the MCFG table */
17 struct mcfg_entry {
18 	struct list_head	list;
19 	phys_addr_t		addr;
20 	u16			segment;
21 	u8			bus_start;
22 	u8			bus_end;
23 };
24 
25 #ifdef CONFIG_PCI_QUIRKS
26 struct mcfg_fixup {
27 	char oem_id[ACPI_OEM_ID_SIZE + 1];
28 	char oem_table_id[ACPI_OEM_TABLE_ID_SIZE + 1];
29 	u32 oem_revision;
30 	u16 segment;
31 	struct resource bus_range;
32 	const struct pci_ecam_ops *ops;
33 	struct resource cfgres;
34 };
35 
36 #define MCFG_BUS_RANGE(start, end)	DEFINE_RES_NAMED((start),	\
37 						((end) - (start) + 1),	\
38 						NULL, IORESOURCE_BUS)
39 #define MCFG_BUS_ANY			MCFG_BUS_RANGE(0x0, 0xff)
40 
41 static struct mcfg_fixup mcfg_quirks[] = {
42 /*	{ OEM_ID, OEM_TABLE_ID, REV, SEGMENT, BUS_RANGE, ops, cfgres }, */
43 
44 #ifdef CONFIG_ARM64
45 
46 #define AL_ECAM(table_id, rev, seg, ops) \
47 	{ "AMAZON", table_id, rev, seg, MCFG_BUS_ANY, ops }
48 
49 	AL_ECAM("GRAVITON", 0, 0, &al_pcie_ops),
50 	AL_ECAM("GRAVITON", 0, 1, &al_pcie_ops),
51 	AL_ECAM("GRAVITON", 0, 2, &al_pcie_ops),
52 	AL_ECAM("GRAVITON", 0, 3, &al_pcie_ops),
53 	AL_ECAM("GRAVITON", 0, 4, &al_pcie_ops),
54 	AL_ECAM("GRAVITON", 0, 5, &al_pcie_ops),
55 	AL_ECAM("GRAVITON", 0, 6, &al_pcie_ops),
56 	AL_ECAM("GRAVITON", 0, 7, &al_pcie_ops),
57 
58 #define QCOM_ECAM32(seg) \
59 	{ "QCOM  ", "QDF2432 ", 1, seg, MCFG_BUS_ANY, &pci_32b_ops }
60 
61 	QCOM_ECAM32(0),
62 	QCOM_ECAM32(1),
63 	QCOM_ECAM32(2),
64 	QCOM_ECAM32(3),
65 	QCOM_ECAM32(4),
66 	QCOM_ECAM32(5),
67 	QCOM_ECAM32(6),
68 	QCOM_ECAM32(7),
69 
70 #define HISI_QUAD_DOM(table_id, seg, ops) \
71 	{ "HISI  ", table_id, 0, (seg) + 0, MCFG_BUS_ANY, ops }, \
72 	{ "HISI  ", table_id, 0, (seg) + 1, MCFG_BUS_ANY, ops }, \
73 	{ "HISI  ", table_id, 0, (seg) + 2, MCFG_BUS_ANY, ops }, \
74 	{ "HISI  ", table_id, 0, (seg) + 3, MCFG_BUS_ANY, ops }
75 
76 	HISI_QUAD_DOM("HIP05   ",  0, &hisi_pcie_ops),
77 	HISI_QUAD_DOM("HIP06   ",  0, &hisi_pcie_ops),
78 	HISI_QUAD_DOM("HIP07   ",  0, &hisi_pcie_ops),
79 	HISI_QUAD_DOM("HIP07   ",  4, &hisi_pcie_ops),
80 	HISI_QUAD_DOM("HIP07   ",  8, &hisi_pcie_ops),
81 	HISI_QUAD_DOM("HIP07   ", 12, &hisi_pcie_ops),
82 
83 #define THUNDER_PEM_RES(addr, node) \
84 	DEFINE_RES_MEM((addr) + ((u64) (node) << 44), 0x39 * SZ_16M)
85 
86 #define THUNDER_PEM_QUIRK(rev, node) \
87 	{ "CAVIUM", "THUNDERX", rev, 4 + (10 * (node)), MCFG_BUS_ANY,	    \
88 	  &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x88001f000000UL, node) },  \
89 	{ "CAVIUM", "THUNDERX", rev, 5 + (10 * (node)), MCFG_BUS_ANY,	    \
90 	  &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x884057000000UL, node) },  \
91 	{ "CAVIUM", "THUNDERX", rev, 6 + (10 * (node)), MCFG_BUS_ANY,	    \
92 	  &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x88808f000000UL, node) },  \
93 	{ "CAVIUM", "THUNDERX", rev, 7 + (10 * (node)), MCFG_BUS_ANY,	    \
94 	  &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x89001f000000UL, node) },  \
95 	{ "CAVIUM", "THUNDERX", rev, 8 + (10 * (node)), MCFG_BUS_ANY,	    \
96 	  &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x894057000000UL, node) },  \
97 	{ "CAVIUM", "THUNDERX", rev, 9 + (10 * (node)), MCFG_BUS_ANY,	    \
98 	  &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x89808f000000UL, node) }
99 
100 #define THUNDER_ECAM_QUIRK(rev, seg)					\
101 	{ "CAVIUM", "THUNDERX", rev, seg, MCFG_BUS_ANY,			\
102 	&pci_thunder_ecam_ops }
103 
104 	/* SoC pass2.x */
105 	THUNDER_PEM_QUIRK(1, 0),
106 	THUNDER_PEM_QUIRK(1, 1),
107 	THUNDER_ECAM_QUIRK(1, 10),
108 
109 	/* SoC pass1.x */
110 	THUNDER_PEM_QUIRK(2, 0),	/* off-chip devices */
111 	THUNDER_PEM_QUIRK(2, 1),	/* off-chip devices */
112 	THUNDER_ECAM_QUIRK(2,  0),
113 	THUNDER_ECAM_QUIRK(2,  1),
114 	THUNDER_ECAM_QUIRK(2,  2),
115 	THUNDER_ECAM_QUIRK(2,  3),
116 	THUNDER_ECAM_QUIRK(2, 10),
117 	THUNDER_ECAM_QUIRK(2, 11),
118 	THUNDER_ECAM_QUIRK(2, 12),
119 	THUNDER_ECAM_QUIRK(2, 13),
120 
121 	{ "NVIDIA", "TEGRA194", 1, 0, MCFG_BUS_ANY, &tegra194_pcie_ops},
122 	{ "NVIDIA", "TEGRA194", 1, 1, MCFG_BUS_ANY, &tegra194_pcie_ops},
123 	{ "NVIDIA", "TEGRA194", 1, 2, MCFG_BUS_ANY, &tegra194_pcie_ops},
124 	{ "NVIDIA", "TEGRA194", 1, 3, MCFG_BUS_ANY, &tegra194_pcie_ops},
125 	{ "NVIDIA", "TEGRA194", 1, 4, MCFG_BUS_ANY, &tegra194_pcie_ops},
126 	{ "NVIDIA", "TEGRA194", 1, 5, MCFG_BUS_ANY, &tegra194_pcie_ops},
127 
128 #define XGENE_V1_ECAM_MCFG(rev, seg) \
129 	{"APM   ", "XGENE   ", rev, seg, MCFG_BUS_ANY, \
130 		&xgene_v1_pcie_ecam_ops }
131 
132 #define XGENE_V2_ECAM_MCFG(rev, seg) \
133 	{"APM   ", "XGENE   ", rev, seg, MCFG_BUS_ANY, \
134 		&xgene_v2_pcie_ecam_ops }
135 
136 	/* X-Gene SoC with v1 PCIe controller */
137 	XGENE_V1_ECAM_MCFG(1, 0),
138 	XGENE_V1_ECAM_MCFG(1, 1),
139 	XGENE_V1_ECAM_MCFG(1, 2),
140 	XGENE_V1_ECAM_MCFG(1, 3),
141 	XGENE_V1_ECAM_MCFG(1, 4),
142 	XGENE_V1_ECAM_MCFG(2, 0),
143 	XGENE_V1_ECAM_MCFG(2, 1),
144 	XGENE_V1_ECAM_MCFG(2, 2),
145 	XGENE_V1_ECAM_MCFG(2, 3),
146 	XGENE_V1_ECAM_MCFG(2, 4),
147 	/* X-Gene SoC with v2.1 PCIe controller */
148 	XGENE_V2_ECAM_MCFG(3, 0),
149 	XGENE_V2_ECAM_MCFG(3, 1),
150 	/* X-Gene SoC with v2.2 PCIe controller */
151 	XGENE_V2_ECAM_MCFG(4, 0),
152 	XGENE_V2_ECAM_MCFG(4, 1),
153 	XGENE_V2_ECAM_MCFG(4, 2),
154 
155 #define ALTRA_ECAM_QUIRK(rev, seg) \
156 	{ "Ampere", "Altra   ", rev, seg, MCFG_BUS_ANY, &pci_32b_read_ops }
157 
158 	ALTRA_ECAM_QUIRK(1, 0),
159 	ALTRA_ECAM_QUIRK(1, 1),
160 	ALTRA_ECAM_QUIRK(1, 2),
161 	ALTRA_ECAM_QUIRK(1, 3),
162 	ALTRA_ECAM_QUIRK(1, 4),
163 	ALTRA_ECAM_QUIRK(1, 5),
164 	ALTRA_ECAM_QUIRK(1, 6),
165 	ALTRA_ECAM_QUIRK(1, 7),
166 	ALTRA_ECAM_QUIRK(1, 8),
167 	ALTRA_ECAM_QUIRK(1, 9),
168 	ALTRA_ECAM_QUIRK(1, 10),
169 	ALTRA_ECAM_QUIRK(1, 11),
170 	ALTRA_ECAM_QUIRK(1, 12),
171 	ALTRA_ECAM_QUIRK(1, 13),
172 	ALTRA_ECAM_QUIRK(1, 14),
173 	ALTRA_ECAM_QUIRK(1, 15),
174 #endif /* ARM64 */
175 
176 #ifdef CONFIG_LOONGARCH
177 #define LOONGSON_ECAM_MCFG(table_id, seg) \
178 	{ "LOONGS", table_id, 1, seg, MCFG_BUS_ANY, &loongson_pci_ecam_ops }
179 
180 	LOONGSON_ECAM_MCFG("\0", 0),
181 	LOONGSON_ECAM_MCFG("LOONGSON", 0),
182 	LOONGSON_ECAM_MCFG("\0", 1),
183 	LOONGSON_ECAM_MCFG("LOONGSON", 1),
184 #endif /* LOONGARCH */
185 };
186 
187 static char mcfg_oem_id[ACPI_OEM_ID_SIZE];
188 static char mcfg_oem_table_id[ACPI_OEM_TABLE_ID_SIZE];
189 static u32 mcfg_oem_revision;
190 
pci_mcfg_quirk_matches(struct mcfg_fixup * f,u16 segment,struct resource * bus_range)191 static int pci_mcfg_quirk_matches(struct mcfg_fixup *f, u16 segment,
192 				  struct resource *bus_range)
193 {
194 	if (!memcmp(f->oem_id, mcfg_oem_id, ACPI_OEM_ID_SIZE) &&
195 	    !memcmp(f->oem_table_id, mcfg_oem_table_id,
196 		    ACPI_OEM_TABLE_ID_SIZE) &&
197 	    f->oem_revision == mcfg_oem_revision &&
198 	    f->segment == segment &&
199 	    resource_contains(&f->bus_range, bus_range))
200 		return 1;
201 
202 	return 0;
203 }
204 #endif
205 
pci_mcfg_apply_quirks(struct acpi_pci_root * root,struct resource * cfgres,const struct pci_ecam_ops ** ecam_ops)206 static void pci_mcfg_apply_quirks(struct acpi_pci_root *root,
207 				  struct resource *cfgres,
208 				  const struct pci_ecam_ops **ecam_ops)
209 {
210 #ifdef CONFIG_PCI_QUIRKS
211 	u16 segment = root->segment;
212 	struct resource *bus_range = &root->secondary;
213 	struct mcfg_fixup *f;
214 	int i;
215 
216 	for (i = 0, f = mcfg_quirks; i < ARRAY_SIZE(mcfg_quirks); i++, f++) {
217 		if (pci_mcfg_quirk_matches(f, segment, bus_range)) {
218 			if (f->cfgres.start)
219 				*cfgres = f->cfgres;
220 			if (f->ops)
221 				*ecam_ops =  f->ops;
222 			dev_info(&root->device->dev, "MCFG quirk: ECAM at %pR for %pR with %ps\n",
223 				 cfgres, bus_range, *ecam_ops);
224 			return;
225 		}
226 	}
227 #endif
228 }
229 
230 /* List to save MCFG entries */
231 static LIST_HEAD(pci_mcfg_list);
232 
pci_mcfg_lookup(struct acpi_pci_root * root,struct resource * cfgres,const struct pci_ecam_ops ** ecam_ops)233 int pci_mcfg_lookup(struct acpi_pci_root *root, struct resource *cfgres,
234 		    const struct pci_ecam_ops **ecam_ops)
235 {
236 	const struct pci_ecam_ops *ops = &pci_generic_ecam_ops;
237 	struct resource *bus_res = &root->secondary;
238 	u16 seg = root->segment;
239 	struct mcfg_entry *e;
240 	struct resource res;
241 
242 	/* Use address from _CBA if present, otherwise lookup MCFG */
243 	if (root->mcfg_addr)
244 		goto skip_lookup;
245 
246 	/*
247 	 * We expect the range in bus_res in the coverage of MCFG bus range.
248 	 */
249 	list_for_each_entry(e, &pci_mcfg_list, list) {
250 		if (e->segment == seg && e->bus_start <= bus_res->start &&
251 		    e->bus_end >= bus_res->end) {
252 			root->mcfg_addr = e->addr;
253 		}
254 
255 	}
256 
257 skip_lookup:
258 	memset(&res, 0, sizeof(res));
259 	if (root->mcfg_addr) {
260 		res.start = root->mcfg_addr + (bus_res->start << 20);
261 		res.end = res.start + (resource_size(bus_res) << 20) - 1;
262 		res.flags = IORESOURCE_MEM;
263 	}
264 
265 	/*
266 	 * Allow quirks to override default ECAM ops and CFG resource
267 	 * range.  This may even fabricate a CFG resource range in case
268 	 * MCFG does not have it.  Invalid CFG start address means MCFG
269 	 * firmware bug or we need another quirk in array.
270 	 */
271 	pci_mcfg_apply_quirks(root, &res, &ops);
272 	if (!res.start)
273 		return -ENXIO;
274 
275 	*cfgres = res;
276 	*ecam_ops = ops;
277 	return 0;
278 }
279 
pci_mcfg_parse(struct acpi_table_header * header)280 static __init int pci_mcfg_parse(struct acpi_table_header *header)
281 {
282 	struct acpi_table_mcfg *mcfg;
283 	struct acpi_mcfg_allocation *mptr;
284 	struct mcfg_entry *e, *arr;
285 	int i, n;
286 
287 	if (header->length < sizeof(struct acpi_table_mcfg))
288 		return -EINVAL;
289 
290 	n = (header->length - sizeof(struct acpi_table_mcfg)) /
291 					sizeof(struct acpi_mcfg_allocation);
292 	mcfg = (struct acpi_table_mcfg *)header;
293 	mptr = (struct acpi_mcfg_allocation *) &mcfg[1];
294 
295 	arr = kcalloc(n, sizeof(*arr), GFP_KERNEL);
296 	if (!arr)
297 		return -ENOMEM;
298 
299 	for (i = 0, e = arr; i < n; i++, mptr++, e++) {
300 		e->segment = mptr->pci_segment;
301 		e->addr =  mptr->address;
302 		e->bus_start = mptr->start_bus_number;
303 		e->bus_end = mptr->end_bus_number;
304 		list_add(&e->list, &pci_mcfg_list);
305 	}
306 
307 #ifdef CONFIG_PCI_QUIRKS
308 	/* Save MCFG IDs and revision for quirks matching */
309 	memcpy(mcfg_oem_id, header->oem_id, ACPI_OEM_ID_SIZE);
310 	memcpy(mcfg_oem_table_id, header->oem_table_id, ACPI_OEM_TABLE_ID_SIZE);
311 	mcfg_oem_revision = header->oem_revision;
312 #endif
313 
314 	pr_info("MCFG table detected, %d entries\n", n);
315 	return 0;
316 }
317 
318 /* Interface called by ACPI - parse and save MCFG table */
pci_mmcfg_late_init(void)319 void __init pci_mmcfg_late_init(void)
320 {
321 	int err = acpi_table_parse(ACPI_SIG_MCFG, pci_mcfg_parse);
322 	if (err)
323 		pr_debug("Failed to parse MCFG (%d)\n", err);
324 }
325