xref: /openbmc/u-boot/board/ti/panda/panda_mux_data.h (revision e8f80a5a)
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * (C) Copyright 2010
4  * Texas Instruments Incorporated, <www.ti.com>
5  *
6  *	Balaji Krishnamoorthy	<balajitk@ti.com>
7  *	Aneesh V		<aneesh@ti.com>
8  */
9 #ifndef _PANDA_MUX_DATA_H_
10 #define _PANDA_MUX_DATA_H_
11 
12 #include <asm/arch/mux_omap4.h>
13 
14 
15 const struct pad_conf_entry core_padconf_array_essential[] = {
16 
17 {GPMC_AD0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat0 */
18 {GPMC_AD1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat1 */
19 {GPMC_AD2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat2 */
20 {GPMC_AD3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat3 */
21 {GPMC_AD4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat4 */
22 {GPMC_AD5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat5 */
23 {GPMC_AD6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat6 */
24 {GPMC_AD7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat7 */
25 {GPMC_NOE, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M1)},	 /* sdmmc2_clk */
26 {GPMC_NWE, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_cmd */
27 {SDMMC1_CLK, (PTU | OFF_EN | OFF_OUT_PTD | M0)},	 /* sdmmc1_clk */
28 {SDMMC1_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_cmd */
29 {SDMMC1_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat0 */
30 {SDMMC1_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat1 */
31 {SDMMC1_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat2 */
32 {SDMMC1_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat3 */
33 {SDMMC1_DAT4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat4 */
34 {SDMMC1_DAT5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat5 */
35 {SDMMC1_DAT6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat6 */
36 {SDMMC1_DAT7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat7 */
37 {I2C1_SCL, (PTU | IEN | M0)},				/* i2c1_scl */
38 {I2C1_SDA, (PTU | IEN | M0)},				/* i2c1_sda */
39 {I2C2_SCL, (PTU | IEN | M0)},				/* i2c2_scl */
40 {I2C2_SDA, (PTU | IEN | M0)},				/* i2c2_sda */
41 {I2C3_SCL, (PTU | IEN | M0)},				/* i2c3_scl */
42 {I2C3_SDA, (PTU | IEN | M0)},				/* i2c3_sda */
43 {I2C4_SCL, (PTU | IEN | M0)},				/* i2c4_scl */
44 {I2C4_SDA, (PTU | IEN | M0)},				/* i2c4_sda */
45 {UART3_CTS_RCTX, (PTU | IEN | M0)},			/* uart3_tx */
46 {UART3_RTS_SD, (M0)},					/* uart3_rts_sd */
47 {UART3_RX_IRRX, (IEN | M0)},				/* uart3_rx */
48 {UART3_TX_IRTX, (M0)},					/* uart3_tx */
49 {USBB1_ULPITLL_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)},/* usbb1_ulpiphy_clk */
50 {USBB1_ULPITLL_STP, (OFF_EN | OFF_OUT_PTD | M4)},		/* usbb1_ulpiphy_stp */
51 {USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dir */
52 {USBB1_ULPITLL_NXT, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_nxt */
53 {USBB1_ULPITLL_DAT0, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat0 */
54 {USBB1_ULPITLL_DAT1, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat1 */
55 {USBB1_ULPITLL_DAT2, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat2 */
56 {USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat3 */
57 {USBB1_ULPITLL_DAT4, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat4 */
58 {USBB1_ULPITLL_DAT5, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat5 */
59 {USBB1_ULPITLL_DAT6, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat6 */
60 {USBB1_ULPITLL_DAT7, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat7 */
61 {USBB1_HSIC_DATA, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* usbb1_hsic_data */
62 {USBB1_HSIC_STROBE, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* usbb1_hsic_strobe */
63 {USBC1_ICUSB_DP, (IEN | M0)},					/* usbc1_icusb_dp */
64 {USBC1_ICUSB_DM, (IEN | M0)},					/* usbc1_icusb_dm */
65 {UNIPRO_TY2, (PTU | IEN | M3)},					/* gpio_1 */
66 {GPMC_WAIT1,  (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)},	/* gpio_62 */
67 {FREF_CLK2_OUT, (PTU | IEN | M3)},				/* gpio_182 */
68 
69 };
70 
71 const struct pad_conf_entry wkup_padconf_array_essential[] = {
72 
73 {PAD1_SR_SCL, (PTU | IEN | M0)}, /* sr_scl */
74 {PAD0_SR_SDA, (PTU | IEN | M0)}, /* sr_sda */
75 {PAD1_SYS_32K, (IEN | M0)},	 /* sys_32k */
76 {PAD0_FREF_CLK3_OUT, (M0)}, /* fref_clk3_out */
77 
78 };
79 
80 const struct pad_conf_entry wkup_padconf_array_essential_4460[] = {
81 
82 {PAD1_FREF_CLK4_REQ, (M3)}, /* gpio_wk7 for TPS: Mode 3 */
83 
84 };
85 
86 #endif /* _PANDA_MUX_DATA_H_ */
87