1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * (C) Copyright 2011
4  * Logic Product Development <www.logicpd.com>
5  *
6  * Author :
7  *	Peter Barada <peter.barada@logicpd.com>
8  *
9  * Derived from Beagle Board and 3430 SDP code by
10  *	Richard Woodruff <r-woodruff2@ti.com>
11  *	Syed Mohammed Khasim <khasim@ti.com>
12  */
13 #include <common.h>
14 #include <dm.h>
15 #include <ns16550.h>
16 #include <netdev.h>
17 #include <flash.h>
18 #include <nand.h>
19 #include <i2c.h>
20 #include <twl4030.h>
21 #include <asm/io.h>
22 #include <asm/arch/mmc_host_def.h>
23 #include <asm/arch/mux.h>
24 #include <asm/arch/mem.h>
25 #include <asm/arch/sys_proto.h>
26 #include <asm/gpio.h>
27 #include <asm/omap_mmc.h>
28 #include <asm/mach-types.h>
29 #include <linux/mtd/rawnand.h>
30 #include <asm/omap_musb.h>
31 #include <linux/errno.h>
32 #include <linux/usb/ch9.h>
33 #include <linux/usb/gadget.h>
34 #include <linux/usb/musb.h>
35 #include "omap3logic.h"
36 #ifdef CONFIG_USB_EHCI_HCD
37 #include <usb.h>
38 #include <asm/ehci-omap.h>
39 #endif
40 
41 DECLARE_GLOBAL_DATA_PTR;
42 
43 #define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG1	0x00011203
44 #define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG2	0x000A1302
45 #define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG3	0x000F1302
46 #define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG4	0x0A021303
47 #define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG5	0x00120F18
48 #define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG6	0x0A030000
49 #define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG7	0x00000C50
50 
51 #define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG1	0x00011203
52 #define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG2	0x00091102
53 #define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG3	0x000D1102
54 #define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG4	0x09021103
55 #define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG5	0x00100D15
56 #define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG6	0x09030000
57 #define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG7	0x00000C50
58 
59 #ifdef CONFIG_SPL_OS_BOOT
spl_start_uboot(void)60 int spl_start_uboot(void)
61 {
62 	/* break into full u-boot on 'c' */
63 	return serial_tstc() && serial_getc() == 'c';
64 }
65 #endif
66 
67 #if defined(CONFIG_SPL_BUILD)
68 /*
69  * Routine: get_board_mem_timings
70  * Description: If we use SPL then there is no x-loader nor config header
71  * so we have to setup the DDR timings ourself on the first bank.  This
72  * provides the timing values back to the function that configures
73  * the memory.
74  */
get_board_mem_timings(struct board_sdrc_timings * timings)75 void get_board_mem_timings(struct board_sdrc_timings *timings)
76 {
77 	timings->mr = MICRON_V_MR_165;
78 
79 	if (get_cpu_family() == CPU_OMAP36XX) {
80 		/* 200 MHz works for OMAP36/DM37 */
81 		/* 256MB DDR */
82 		timings->mcfg = MICRON_V_MCFG_200(256 << 20);
83 		timings->ctrla = MICRON_V_ACTIMA_200;
84 		timings->ctrlb = MICRON_V_ACTIMB_200;
85 		timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
86 	} else {
87 		/* 165 MHz works for OMAP35 */
88 		timings->mcfg = MICRON_V_MCFG_165(256 << 20);
89 		timings->ctrla = MICRON_V_ACTIMA_165;
90 		timings->ctrlb = MICRON_V_ACTIMB_165;
91 		timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
92 	}
93 }
94 
95 #define GPMC_NAND_COMMAND_0 (OMAP34XX_GPMC_BASE + 0x7c)
96 #define GPMC_NAND_DATA_0 (OMAP34XX_GPMC_BASE + 0x84)
97 #define GPMC_NAND_ADDRESS_0 (OMAP34XX_GPMC_BASE + 0x80)
98 
spl_board_prepare_for_linux(void)99 void spl_board_prepare_for_linux(void)
100 {
101 	/* The Micron NAND starts locked which
102 	 * prohibits mounting the NAND as RW
103 	 * The following commands are what unlocks
104 	 * the NAND to become RW Falcon Mode does not
105 	 * have as many smarts as U-Boot, but Logic PD
106 	 * only makes NAND with 512MB so these hard coded
107 	 * values should work for all current models
108 	 */
109 
110 	writeb(0x70, GPMC_NAND_COMMAND_0);
111 	writeb(-1, GPMC_NAND_DATA_0);
112 	writeb(0x7a, GPMC_NAND_COMMAND_0);
113 	writeb(0x00, GPMC_NAND_ADDRESS_0);
114 	writeb(0x00, GPMC_NAND_ADDRESS_0);
115 	writeb(0x00, GPMC_NAND_ADDRESS_0);
116 	writeb(-1, GPMC_NAND_COMMAND_0);
117 
118 	/* Begin address 0 */
119 	writeb(NAND_CMD_UNLOCK1, 0x6e00007c);
120 	writeb(0x00, GPMC_NAND_ADDRESS_0);
121 	writeb(0x00, GPMC_NAND_ADDRESS_0);
122 	writeb(0x00, GPMC_NAND_ADDRESS_0);
123 	writeb(-1, GPMC_NAND_DATA_0);
124 
125 	/* Ending address at the end of Flash */
126 	writeb(NAND_CMD_UNLOCK2, GPMC_NAND_COMMAND_0);
127 	writeb(0xc0, GPMC_NAND_ADDRESS_0);
128 	writeb(0xff, GPMC_NAND_ADDRESS_0);
129 	writeb(0x03, GPMC_NAND_ADDRESS_0);
130 	writeb(-1, GPMC_NAND_DATA_0);
131 	writeb(0x79, GPMC_NAND_COMMAND_0);
132 	writeb(-1, GPMC_NAND_DATA_0);
133 	writeb(-1, GPMC_NAND_DATA_0);
134 }
135 #endif
136 
137 /*
138  * Routine: misc_init_r
139  * Description: Configure board specific parts
140  */
misc_init_r(void)141 int misc_init_r(void)
142 {
143 	twl4030_power_init();
144 	omap_die_id_display();
145 	return 0;
146 }
147 
148 #if defined(CONFIG_FLASH_CFI_DRIVER)
149 static const u32 gpmc_dm37_c2nor_config[] = {
150 	LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG1,
151 	LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG2,
152 	LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG3,
153 	LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG4,
154 	LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG5,
155 	LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG6,
156 	LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG7
157 };
158 
159 static const u32 gpmc_omap35_c2nor_config[] = {
160 	LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG1,
161 	LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG2,
162 	LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG3,
163 	LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG4,
164 	LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG5,
165 	LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG6,
166 	LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG7
167 };
168 #endif
169 
170 /*
171  * Routine: board_init
172  * Description: Early hardware init.
173  */
board_init(void)174 int board_init(void)
175 {
176 	gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
177 
178 	/* boot param addr */
179 	gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
180 #if defined(CONFIG_FLASH_CFI_DRIVER)
181 	if (get_cpu_family() == CPU_OMAP36XX) {
182 		/* Enable CS2 for NOR Flash */
183 		enable_gpmc_cs_config(gpmc_dm37_c2nor_config, &gpmc_cfg->cs[2],
184 				      0x10000000, GPMC_SIZE_64M);
185 	} else {
186 		enable_gpmc_cs_config(gpmc_omap35_c2nor_config, &gpmc_cfg->cs[2],
187 				      0x10000000, GPMC_SIZE_64M);
188 	}
189 #endif
190 	return 0;
191 }
192 
193 #ifdef CONFIG_BOARD_LATE_INIT
194 
unlock_nand(void)195 static void unlock_nand(void)
196 {
197 	int dev = nand_curr_device;
198 	struct mtd_info *mtd;
199 
200 	mtd = get_nand_dev_by_index(dev);
201 	nand_unlock(mtd, 0, mtd->size, 0);
202 }
203 
board_late_init(void)204 int board_late_init(void)
205 {
206 #ifdef CONFIG_CMD_NAND_LOCK_UNLOCK
207 	unlock_nand();
208 #endif
209 	return 0;
210 }
211 #endif
212 
213 #if defined(CONFIG_MMC)
board_mmc_power_init(void)214 void board_mmc_power_init(void)
215 {
216 	twl4030_power_mmc_init(0);
217 }
218 #endif
219 
220 #ifdef CONFIG_SMC911X
221 /* GPMC CS1 settings for Logic SOM LV/Torpedo LAN92xx Ethernet chip */
222 static const u32 gpmc_lan92xx_config[] = {
223 	NET_LAN92XX_GPMC_CONFIG1,
224 	NET_LAN92XX_GPMC_CONFIG2,
225 	NET_LAN92XX_GPMC_CONFIG3,
226 	NET_LAN92XX_GPMC_CONFIG4,
227 	NET_LAN92XX_GPMC_CONFIG5,
228 	NET_LAN92XX_GPMC_CONFIG6,
229 };
230 
board_eth_init(bd_t * bis)231 int board_eth_init(bd_t *bis)
232 {
233 	enable_gpmc_cs_config(gpmc_lan92xx_config, &gpmc_cfg->cs[1],
234 			CONFIG_SMC911X_BASE, GPMC_SIZE_16M);
235 
236 	return smc911x_initialize(0, CONFIG_SMC911X_BASE);
237 }
238 #endif
239