1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright (C) 2014 Christoph Fritz <chf.fritzc@googlemail.com>
4 */
5
6#include "omap36xx.dtsi"
7
8/ {
9	model = "INCOstartec LILLY-A83X module (DM3730)";
10	compatible = "incostartec,omap3-lilly-a83x", "ti,omap3630", "ti,omap36xx", "ti,omap3";
11
12	chosen {
13			bootargs = "console=ttyO0,115200n8 vt.global_cursor_default=0 consoleblank=0";
14	};
15
16	memory@80000000 {
17		device_type = "memory";
18		reg = <0x80000000 0x8000000>;   /* 128 MB */
19	};
20
21	leds {
22		compatible = "gpio-leds";
23
24		led1 {
25			label = "lilly-a83x::led1";
26			gpios = <&gpio1 29 GPIO_ACTIVE_LOW>;
27			linux,default-trigger = "default-on";
28		};
29
30	};
31
32	sound {
33		compatible = "ti,omap-twl4030";
34		ti,model = "lilly-a83x";
35
36		ti,mcbsp = <&mcbsp2>;
37	};
38
39	reg_vcc3: vcc3 {
40		compatible = "regulator-fixed";
41		regulator-name = "VCC3";
42		regulator-min-microvolt = <3300000>;
43		regulator-max-microvolt = <3300000>;
44		regulator-always-on;
45	};
46
47	hsusb1_phy: hsusb1_phy {
48		compatible = "usb-nop-xceiv";
49		vcc-supply = <&reg_vcc3>;
50		#phy-cells = <0>;
51	};
52};
53
54&omap3_pmx_wkup {
55	pinctrl-names = "default";
56
57	lan9221_pins: lan9221-pins {
58		pinctrl-single,pins = <
59			OMAP3_WKUP_IOPAD(0x2a5a, PIN_INPUT | MUX_MODE4)   /* reserved.gpio_129 */
60		>;
61	};
62
63	tsc2048_pins: tsc2048-pins {
64		pinctrl-single,pins = <
65			OMAP3_WKUP_IOPAD(0x2a16, PIN_INPUT_PULLUP | MUX_MODE4)   /* sys_boot6.gpio_8 */
66		>;
67	};
68
69	mmc1cd_pins: mmc1cd-pins {
70		pinctrl-single,pins = <
71			OMAP3_WKUP_IOPAD(0x2a56, PIN_INPUT | MUX_MODE4)   /* reserved.gpio_126 */
72		>;
73	};
74};
75
76&omap3_pmx_core {
77	pinctrl-names = "default";
78
79	uart1_pins: uart1-pins {
80		pinctrl-single,pins = <
81			OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE0)   /* uart1_tx.uart1_tx */
82			OMAP3_CORE1_IOPAD(0x217e, PIN_OUTPUT | MUX_MODE0)   /* uart1_rts.uart1_rts */
83			OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT | MUX_MODE0)    /* uart1_cts.uart1_cts */
84			OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | MUX_MODE0)    /* uart1_rx.uart1_rx */
85		>;
86	};
87
88	uart2_pins: uart2-pins {
89		pinctrl-single,pins = <
90			OMAP3_CORE1_IOPAD(0x2170, PIN_OUTPUT | MUX_MODE1)   /* mcbsp3_clkx.uart2_tx */
91			OMAP3_CORE1_IOPAD(0x2172, PIN_INPUT | MUX_MODE1)    /* mcbsp3_fsx.uart2_rx */
92		>;
93	};
94
95	uart3_pins: uart3-pins {
96		pinctrl-single,pins = <
97			OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0)    /* uart3_rx_irrx.uart3_rx_irrx */
98			OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0)   /* uart3_tx_irtx.uart3_tx_irtx */
99		>;
100	};
101
102	i2c1_pins: i2c1-pins {
103		pinctrl-single,pins = <
104			OMAP3_CORE1_IOPAD(0x21ba ,PIN_INPUT_PULLUP | MUX_MODE0)    /* i2c1_scl.i2c1_scl */
105			OMAP3_CORE1_IOPAD(0x21bc ,PIN_INPUT_PULLUP | MUX_MODE0)    /* i2c1_sda.i2c1_sda */
106		>;
107	};
108
109	i2c2_pins: i2c2-pins {
110		pinctrl-single,pins = <
111			OMAP3_CORE1_IOPAD(0x21be, PIN_INPUT | MUX_MODE0)   /* i2c2_scl.i2c2_scl */
112			OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT | MUX_MODE0)   /* i2c2_sda.i2c2_sda */
113		>;
114	};
115
116	i2c3_pins: i2c3-pins {
117		pinctrl-single,pins = <
118			OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0)   /* i2c3_scl.i2c3_scl */
119			OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0)   /* i2c3_sda.i2c3_sda */
120		>;
121	};
122
123	hsusb1_pins: hsusb1-pins {
124		pinctrl-single,pins = <
125
126			/* GPIO 182 controls USB-Hub reset. But USB-Phy its
127			 * reset can't be controlled. So we clamp this GPIO to
128			 * high (PIN_OFF_OUTPUT_HIGH) to always enable USB-Hub.
129			 */
130
131			OMAP3_CORE1_IOPAD(0x21de, PIN_OUTPUT_PULLUP | PIN_OFF_OUTPUT_HIGH | MUX_MODE4)   /* mcspi2_cs1.gpio_182 */
132		>;
133	};
134
135	hsusb_otg_pins: hsusb-otg-pins {
136		pinctrl-single,pins = <
137			OMAP3_CORE1_IOPAD(0x21a2, PIN_INPUT | MUX_MODE0)   /* hsusb0_clk.hsusb0_clk */
138			OMAP3_CORE1_IOPAD(0x21a4, PIN_OUTPUT | MUX_MODE0)  /* hsusb0_stp.hsusb0_stp */
139			OMAP3_CORE1_IOPAD(0x21a6, PIN_INPUT | MUX_MODE0)   /* hsusb0_dir.hsusb0_dir */
140			OMAP3_CORE1_IOPAD(0x21a8, PIN_INPUT | MUX_MODE0)   /* hsusb0_nxt.hsusb0_nxt */
141			OMAP3_CORE1_IOPAD(0x21aa, PIN_INPUT | MUX_MODE0)   /* hsusb0_data0.hsusb0_data0 */
142			OMAP3_CORE1_IOPAD(0x21ac, PIN_INPUT | MUX_MODE0)   /* hsusb0_data1.hsusb0_data1 */
143			OMAP3_CORE1_IOPAD(0x21ae, PIN_INPUT | MUX_MODE0)   /* hsusb0_data2.hsusb0_data2 */
144			OMAP3_CORE1_IOPAD(0x21b0, PIN_INPUT | MUX_MODE0)   /* hsusb0_data3.hsusb0_data3 */
145			OMAP3_CORE1_IOPAD(0x21b2, PIN_INPUT | MUX_MODE0)   /* hsusb0_data4.hsusb0_data4 */
146			OMAP3_CORE1_IOPAD(0x21b4, PIN_INPUT | MUX_MODE0)   /* hsusb0_data5.hsusb0_data5 */
147			OMAP3_CORE1_IOPAD(0x21b6, PIN_INPUT | MUX_MODE0)   /* hsusb0_data6.hsusb0_data6 */
148			OMAP3_CORE1_IOPAD(0x21b8, PIN_INPUT | MUX_MODE0)   /* hsusb0_data7.hsusb0_data7 */
149		>;
150	};
151
152	mmc1_pins: mmc1-pins {
153		pinctrl-single,pins = <
154			OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0)   /* sdmmc1_clk.sdmmc1_clk */
155			OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0)   /* sdmmc1_cmd.sdmmc1_cmd */
156			OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0)   /* sdmmc1_dat0.sdmmc1_dat0 */
157			OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0)   /* sdmmc1_dat1.sdmmc1_dat1 */
158			OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0)   /* sdmmc1_dat2.sdmmc1_dat2 */
159			OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0)   /* sdmmc1_dat3.sdmmc1_dat3 */
160		>;
161	};
162
163	spi2_pins: spi2-pins {
164		pinctrl-single,pins = <
165			OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE0)   /* mcspi2_clk.mcspi2_clk */
166			OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE0)   /* mcspi2_simo.mcspi2_simo */
167			OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE0)   /* mcspi2_somi.mcspi2_somi */
168			OMAP3_CORE1_IOPAD(0x21dc, PIN_OUTPUT | MUX_MODE0)   /* mcspi2_cs0.mcspi2_cs0 */
169		>;
170	};
171};
172
173&omap3_pmx_core2 {
174	pinctrl-names = "default";
175
176	hsusb1_2_pins: hsusb1-2-pins {
177		pinctrl-single,pins = <
178			OMAP3630_CORE2_IOPAD(0x25d8, PIN_OUTPUT | MUX_MODE3)  /* etk_clk.hsusb1_stp */
179			OMAP3630_CORE2_IOPAD(0x25da, PIN_INPUT | MUX_MODE3)   /* etk_ctl.hsusb1_clk */
180			OMAP3630_CORE2_IOPAD(0x25dc, PIN_INPUT | MUX_MODE3)   /* etk_d0.hsusb1_data0 */
181			OMAP3630_CORE2_IOPAD(0x25de, PIN_INPUT | MUX_MODE3)   /* etk_d1.hsusb1_data1 */
182			OMAP3630_CORE2_IOPAD(0x25e0, PIN_INPUT | MUX_MODE3)   /* etk_d2.hsusb1_data2 */
183			OMAP3630_CORE2_IOPAD(0x25e2, PIN_INPUT | MUX_MODE3)   /* etk_d3.hsusb1_data7 */
184			OMAP3630_CORE2_IOPAD(0x25e4, PIN_INPUT | MUX_MODE3)   /* etk_d4.hsusb1_data4 */
185			OMAP3630_CORE2_IOPAD(0x25e6, PIN_INPUT | MUX_MODE3)   /* etk_d5.hsusb1_data5 */
186			OMAP3630_CORE2_IOPAD(0x25e8, PIN_INPUT | MUX_MODE3)   /* etk_d6.hsusb1_data6 */
187			OMAP3630_CORE2_IOPAD(0x25ea, PIN_INPUT | MUX_MODE3)   /* etk_d7.hsusb1_data3 */
188			OMAP3630_CORE2_IOPAD(0x25ec, PIN_INPUT | MUX_MODE3)   /* etk_d8.hsusb1_dir */
189			OMAP3630_CORE2_IOPAD(0x25ee, PIN_INPUT | MUX_MODE3)   /* etk_d9.hsusb1_nxt */
190		>;
191	};
192
193	gpio1_pins: gpio1-pins {
194		pinctrl-single,pins = <
195			OMAP3630_CORE2_IOPAD(0x25fa, PIN_OUTPUT_PULLDOWN | MUX_MODE4)   /* etk_d15.gpio_29 */
196		>;
197	};
198
199};
200
201&gpio1 {
202	pinctrl-names = "default";
203	pinctrl-0 = <&gpio1_pins>;
204};
205
206&gpio6 {
207	pinctrl-names = "default";
208	pinctrl-0 = <&hsusb1_pins>;
209};
210
211&i2c1 {
212	clock-frequency = <2600000>;
213	pinctrl-names = "default";
214	pinctrl-0 = <&i2c1_pins>;
215
216	twl: twl@48 {
217		reg = <0x48>;
218		interrupts = <7>;   /* SYS_NIRQ cascaded to intc */
219		interrupt-parent = <&intc>;
220
221		twl_audio: audio {
222			compatible = "ti,twl4030-audio";
223			codec {
224			};
225		};
226	};
227};
228
229#include "twl4030.dtsi"
230#include "twl4030_omap3.dtsi"
231
232&twl {
233	vmmc1: regulator-vmmc1 {
234		regulator-always-on;
235	};
236
237	vdd1: regulator-vdd1 {
238		regulator-always-on;
239	};
240
241	vdd2: regulator-vdd2 {
242		regulator-always-on;
243	};
244};
245
246&i2c2 {
247	clock-frequency = <2600000>;
248	pinctrl-names = "default";
249	pinctrl-0 = <&i2c2_pins>;
250};
251
252&i2c3 {
253	clock-frequency = <2600000>;
254	pinctrl-names = "default";
255	pinctrl-0 = <&i2c3_pins>;
256		gpiom1: gpio@20 {
257			compatible = "microchip,mcp23017";
258			gpio-controller;
259			#gpio-cells = <2>;
260			reg = <0x20>;
261		};
262};
263
264&uart1 {
265	pinctrl-names = "default";
266	pinctrl-0 = <&uart1_pins>;
267};
268
269&uart2 {
270	pinctrl-names = "default";
271	pinctrl-0 = <&uart2_pins>;
272};
273
274&uart3 {
275	pinctrl-names = "default";
276	pinctrl-0 = <&uart3_pins>;
277};
278
279&uart4 {
280	status = "disabled";
281};
282
283&mmc1 {
284	cd-gpios = <&gpio4 30 GPIO_ACTIVE_LOW>;
285	cd-inverted;
286	vmmc-supply = <&vmmc1>;
287	bus-width = <4>;
288	pinctrl-names = "default";
289	pinctrl-0 = <&mmc1_pins &mmc1cd_pins>;
290	cap-sdio-irq;
291	cap-sd-highspeed;
292	cap-mmc-highspeed;
293};
294
295&mmc2 {
296	status = "disabled";
297};
298
299&mmc3 {
300	status = "disabled";
301};
302
303&mcspi2 {
304	status = "okay";
305	pinctrl-names = "default";
306	pinctrl-0 = <&spi2_pins>;
307
308	tsc2046@0 {
309		reg = <0>;   /* CS0 */
310		compatible = "ti,tsc2046";
311		interrupt-parent = <&gpio1>;
312		interrupts = <8 0>;   /* boot6 / gpio_8 */
313		spi-max-frequency = <1000000>;
314		pendown-gpio = <&gpio1 8 GPIO_ACTIVE_LOW>;
315		vcc-supply = <&reg_vcc3>;
316		pinctrl-names = "default";
317		pinctrl-0 = <&tsc2048_pins>;
318
319		ti,x-min = /bits/ 16 <300>;
320		ti,x-max = /bits/ 16 <3000>;
321		ti,y-min = /bits/ 16 <600>;
322		ti,y-max = /bits/ 16 <3600>;
323		ti,x-plate-ohms = /bits/ 16 <80>;
324		ti,pressure-max = /bits/ 16 <255>;
325		ti,swap-xy;
326
327		wakeup-source;
328	};
329};
330
331&usbhsehci {
332	phys = <&hsusb1_phy>;
333};
334
335&usbhshost {
336	pinctrl-names = "default";
337	pinctrl-0 = <&hsusb1_2_pins>;
338	num-ports = <2>;
339	port1-mode = "ehci-phy";
340};
341
342&usb_otg_hs {
343	pinctrl-names = "default";
344	pinctrl-0 = <&hsusb_otg_pins>;
345	interface-type = <0>;
346	usb-phy = <&usb2_phy>;
347	phys = <&usb2_phy>;
348	phy-names = "usb2-phy";
349	mode = <3>;
350	power = <50>;
351};
352
353&mcbsp2 {
354	status = "okay";
355};
356
357&gpmc {
358	ranges = <0 0 0x30000000 0x1000000>,
359		<7 0 0x15000000 0x01000000>;
360
361	nand@0,0 {
362		compatible = "ti,omap2-nand";
363		reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
364		interrupt-parent = <&gpmc>;
365		interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
366			     <1 IRQ_TYPE_NONE>;	/* termcount */
367		nand-bus-width = <16>;
368		ti,nand-ecc-opt = "bch8";
369		/* no elm on omap3 */
370
371		gpmc,mux-add-data = <0>;
372		gpmc,device-width = <2>;
373		gpmc,wait-pin = <0>;
374		gpmc,wait-monitoring-ns = <0>;
375		gpmc,burst-length = <4>;
376		gpmc,cs-on-ns = <0>;
377		gpmc,cs-rd-off-ns = <100>;
378		gpmc,cs-wr-off-ns = <100>;
379		gpmc,adv-on-ns = <0>;
380		gpmc,adv-rd-off-ns = <100>;
381		gpmc,adv-wr-off-ns = <100>;
382		gpmc,oe-on-ns = <5>;
383		gpmc,oe-off-ns = <75>;
384		gpmc,we-on-ns = <5>;
385		gpmc,we-off-ns = <75>;
386		gpmc,rd-cycle-ns = <100>;
387		gpmc,wr-cycle-ns = <100>;
388		gpmc,access-ns = <60>;
389		gpmc,page-burst-access-ns = <5>;
390		gpmc,bus-turnaround-ns = <0>;
391		gpmc,cycle2cycle-samecsen;
392		gpmc,cycle2cycle-delay-ns = <50>;
393		gpmc,wr-data-mux-bus-ns = <75>;
394		gpmc,wr-access-ns = <155>;
395
396		#address-cells = <1>;
397		#size-cells = <1>;
398
399		partition@0 {
400			label = "MLO";
401			reg = <0 0x80000>;
402		};
403
404		partition@80000 {
405			label = "u-boot";
406			reg = <0x80000 0x1e0000>;
407		};
408
409		partition@260000 {
410			label = "u-boot-environment";
411			reg = <0x260000 0x20000>;
412		};
413
414		partition@280000 {
415			label = "kernel";
416			reg = <0x280000 0x500000>;
417		};
418
419		partition@780000 {
420			label = "filesystem";
421			reg = <0x780000 0xf880000>;
422		};
423	};
424
425	ethernet@7,0 {
426		compatible = "smsc,lan9221", "smsc,lan9115";
427		bank-width = <2>;
428		gpmc,mux-add-data = <2>;
429		gpmc,cs-on-ns = <10>;
430		gpmc,cs-rd-off-ns = <60>;
431		gpmc,cs-wr-off-ns = <60>;
432		gpmc,adv-on-ns = <0>;
433		gpmc,adv-rd-off-ns = <10>;
434		gpmc,adv-wr-off-ns = <10>;
435		gpmc,oe-on-ns = <10>;
436		gpmc,oe-off-ns = <60>;
437		gpmc,we-on-ns = <10>;
438		gpmc,we-off-ns = <60>;
439		gpmc,rd-cycle-ns = <100>;
440		gpmc,wr-cycle-ns = <100>;
441		gpmc,access-ns = <50>;
442		gpmc,page-burst-access-ns = <5>;
443		gpmc,bus-turnaround-ns = <0>;
444		gpmc,cycle2cycle-delay-ns = <75>;
445		gpmc,wr-data-mux-bus-ns = <15>;
446		gpmc,wr-access-ns = <75>;
447		gpmc,cycle2cycle-samecsen;
448		gpmc,cycle2cycle-diffcsen;
449		vddvario-supply = <&reg_vcc3>;
450		vdd33a-supply = <&reg_vcc3>;
451		reg-io-width = <4>;
452		interrupt-parent = <&gpio5>;
453		interrupts = <1 0x2>;
454		reg = <7 0 0xff>;
455		pinctrl-names = "default";
456		pinctrl-0 = <&lan9221_pins>;
457		phy-mode = "mii";
458	};
459};
460