1 /*
2  * ARM MemTag convenience functions.
3  *
4  * This code is licensed under the GNU GPL v2 or later.
5  *
6  * SPDX-License-Identifier: LGPL-2.1-or-later
7  */
8 
9 #ifndef AARCH64_MTE_USER_HELPER_H
10 #define AARCH64_MTE USER_HELPER_H
11 
12 #ifndef PR_MTE_TCF_SHIFT
13 # define PR_MTE_TCF_SHIFT       1
14 # define PR_MTE_TCF_NONE        (0UL << PR_MTE_TCF_SHIFT)
15 # define PR_MTE_TCF_SYNC        (1UL << PR_MTE_TCF_SHIFT)
16 # define PR_MTE_TCF_ASYNC       (2UL << PR_MTE_TCF_SHIFT)
17 # define PR_MTE_TCF_MASK        (3UL << PR_MTE_TCF_SHIFT)
18 # define PR_MTE_TAG_SHIFT       3
19 # define PR_MTE_TAG_MASK        (0xffffUL << PR_MTE_TAG_SHIFT)
20 #endif
21 
22 /**
23  * arm_set_mte_tcf0 - Set TCF0 field in SCTLR_EL1 register
24  * @env: The CPU environment
25  * @value: The value to be set for the Tag Check Fault in EL0 field.
26  *
27  * Only SYNC and ASYNC modes can be selected. If ASYMM mode is given, the SYNC
28  * mode is selected instead. So, there is no way to set the ASYMM mode.
29  */
30 void arm_set_mte_tcf0(CPUArchState *env, abi_long value);
31 
32 #endif /* AARCH64_MTE_USER_HELPER_H */
33