1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * (C) 2018 MediaTek Inc. 4 * Copyright (C) 2022 BayLibre SAS 5 * Fabien Parent <fparent@baylibre.com> 6 * Bernhard Rosenkränzer <bero@baylibre.com> 7 */ 8#include <dt-bindings/clock/mediatek,mt8365-clk.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/phy/phy.h> 12 13/ { 14 compatible = "mediatek,mt8365"; 15 interrupt-parent = <&sysirq>; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 cpus { 20 #address-cells = <1>; 21 #size-cells = <0>; 22 23 cluster0_opp: opp-table-0 { 24 compatible = "operating-points-v2"; 25 opp-shared; 26 27 opp-850000000 { 28 opp-hz = /bits/ 64 <850000000>; 29 opp-microvolt = <650000>; 30 }; 31 32 opp-918000000 { 33 opp-hz = /bits/ 64 <918000000>; 34 opp-microvolt = <668750>; 35 }; 36 37 opp-987000000 { 38 opp-hz = /bits/ 64 <987000000>; 39 opp-microvolt = <687500>; 40 }; 41 42 opp-1056000000 { 43 opp-hz = /bits/ 64 <1056000000>; 44 opp-microvolt = <706250>; 45 }; 46 47 opp-1125000000 { 48 opp-hz = /bits/ 64 <1125000000>; 49 opp-microvolt = <725000>; 50 }; 51 52 opp-1216000000 { 53 opp-hz = /bits/ 64 <1216000000>; 54 opp-microvolt = <750000>; 55 }; 56 57 opp-1308000000 { 58 opp-hz = /bits/ 64 <1308000000>; 59 opp-microvolt = <775000>; 60 }; 61 62 opp-1400000000 { 63 opp-hz = /bits/ 64 <1400000000>; 64 opp-microvolt = <800000>; 65 }; 66 67 opp-1466000000 { 68 opp-hz = /bits/ 64 <1466000000>; 69 opp-microvolt = <825000>; 70 }; 71 72 opp-1533000000 { 73 opp-hz = /bits/ 64 <1533000000>; 74 opp-microvolt = <850000>; 75 }; 76 77 opp-1633000000 { 78 opp-hz = /bits/ 64 <1633000000>; 79 opp-microvolt = <887500>; 80 }; 81 82 opp-1700000000 { 83 opp-hz = /bits/ 64 <1700000000>; 84 opp-microvolt = <912500>; 85 }; 86 87 opp-1767000000 { 88 opp-hz = /bits/ 64 <1767000000>; 89 opp-microvolt = <937500>; 90 }; 91 92 opp-1834000000 { 93 opp-hz = /bits/ 64 <1834000000>; 94 opp-microvolt = <962500>; 95 }; 96 97 opp-1917000000 { 98 opp-hz = /bits/ 64 <1917000000>; 99 opp-microvolt = <993750>; 100 }; 101 102 opp-2001000000 { 103 opp-hz = /bits/ 64 <2001000000>; 104 opp-microvolt = <1025000>; 105 }; 106 }; 107 108 cpu-map { 109 cluster0 { 110 core0 { 111 cpu = <&cpu0>; 112 }; 113 core1 { 114 cpu = <&cpu1>; 115 }; 116 core2 { 117 cpu = <&cpu2>; 118 }; 119 core3 { 120 cpu = <&cpu3>; 121 }; 122 }; 123 }; 124 125 cpu0: cpu@0 { 126 device_type = "cpu"; 127 compatible = "arm,cortex-a53"; 128 reg = <0x0>; 129 #cooling-cells = <2>; 130 enable-method = "psci"; 131 cpu-idle-states = <&CPU_MCDI &CLUSTER_MCDI &CLUSTER_DPIDLE>; 132 i-cache-size = <0x8000>; 133 i-cache-line-size = <64>; 134 i-cache-sets = <256>; 135 d-cache-size = <0x8000>; 136 d-cache-line-size = <64>; 137 d-cache-sets = <256>; 138 next-level-cache = <&l2>; 139 clocks = <&mcucfg CLK_MCU_BUS_SEL>, 140 <&apmixedsys CLK_APMIXED_MAINPLL>; 141 clock-names = "cpu", "intermediate"; 142 operating-points-v2 = <&cluster0_opp>; 143 }; 144 145 cpu1: cpu@1 { 146 device_type = "cpu"; 147 compatible = "arm,cortex-a53"; 148 reg = <0x1>; 149 #cooling-cells = <2>; 150 enable-method = "psci"; 151 cpu-idle-states = <&CPU_MCDI &CLUSTER_MCDI &CLUSTER_DPIDLE>; 152 i-cache-size = <0x8000>; 153 i-cache-line-size = <64>; 154 i-cache-sets = <256>; 155 d-cache-size = <0x8000>; 156 d-cache-line-size = <64>; 157 d-cache-sets = <256>; 158 next-level-cache = <&l2>; 159 clocks = <&mcucfg CLK_MCU_BUS_SEL>, 160 <&apmixedsys CLK_APMIXED_MAINPLL>; 161 clock-names = "cpu", "intermediate", "armpll"; 162 operating-points-v2 = <&cluster0_opp>; 163 }; 164 165 cpu2: cpu@2 { 166 device_type = "cpu"; 167 compatible = "arm,cortex-a53"; 168 reg = <0x2>; 169 #cooling-cells = <2>; 170 enable-method = "psci"; 171 cpu-idle-states = <&CPU_MCDI &CLUSTER_MCDI &CLUSTER_DPIDLE>; 172 i-cache-size = <0x8000>; 173 i-cache-line-size = <64>; 174 i-cache-sets = <256>; 175 d-cache-size = <0x8000>; 176 d-cache-line-size = <64>; 177 d-cache-sets = <256>; 178 next-level-cache = <&l2>; 179 clocks = <&mcucfg CLK_MCU_BUS_SEL>, 180 <&apmixedsys CLK_APMIXED_MAINPLL>; 181 clock-names = "cpu", "intermediate", "armpll"; 182 operating-points-v2 = <&cluster0_opp>; 183 }; 184 185 cpu3: cpu@3 { 186 device_type = "cpu"; 187 compatible = "arm,cortex-a53"; 188 reg = <0x3>; 189 #cooling-cells = <2>; 190 enable-method = "psci"; 191 cpu-idle-states = <&CPU_MCDI &CLUSTER_MCDI &CLUSTER_DPIDLE>; 192 i-cache-size = <0x8000>; 193 i-cache-line-size = <64>; 194 i-cache-sets = <256>; 195 d-cache-size = <0x8000>; 196 d-cache-line-size = <64>; 197 d-cache-sets = <256>; 198 next-level-cache = <&l2>; 199 clocks = <&mcucfg CLK_MCU_BUS_SEL>, 200 <&apmixedsys CLK_APMIXED_MAINPLL>; 201 clock-names = "cpu", "intermediate", "armpll"; 202 operating-points-v2 = <&cluster0_opp>; 203 }; 204 205 idle-states { 206 entry-method = "psci"; 207 208 CPU_MCDI: cpu-mcdi { 209 compatible = "arm,idle-state"; 210 local-timer-stop; 211 arm,psci-suspend-param = <0x00010001>; 212 entry-latency-us = <300>; 213 exit-latency-us = <200>; 214 min-residency-us = <1000>; 215 }; 216 217 CLUSTER_MCDI: cluster-mcdi { 218 compatible = "arm,idle-state"; 219 local-timer-stop; 220 arm,psci-suspend-param = <0x01010001>; 221 entry-latency-us = <350>; 222 exit-latency-us = <250>; 223 min-residency-us = <1200>; 224 }; 225 226 CLUSTER_DPIDLE: cluster-dpidle { 227 compatible = "arm,idle-state"; 228 local-timer-stop; 229 arm,psci-suspend-param = <0x01010004>; 230 entry-latency-us = <300>; 231 exit-latency-us = <800>; 232 min-residency-us = <3300>; 233 }; 234 }; 235 236 l2: l2-cache { 237 compatible = "cache"; 238 cache-level = <2>; 239 cache-size = <0x80000>; 240 cache-line-size = <64>; 241 cache-sets = <512>; 242 cache-unified; 243 }; 244 }; 245 246 clk26m: oscillator { 247 compatible = "fixed-clock"; 248 #clock-cells = <0>; 249 clock-frequency = <26000000>; 250 clock-output-names = "clk26m"; 251 }; 252 253 psci { 254 compatible = "arm,psci-1.0"; 255 method = "smc"; 256 }; 257 258 soc { 259 #address-cells = <2>; 260 #size-cells = <2>; 261 compatible = "simple-bus"; 262 ranges; 263 264 gic: interrupt-controller@c000000 { 265 compatible = "arm,gic-v3"; 266 #interrupt-cells = <3>; 267 interrupt-parent = <&gic>; 268 interrupt-controller; 269 reg = <0 0x0c000000 0 0x10000>, /* GICD */ 270 <0 0x0c080000 0 0x80000>, /* GICR */ 271 <0 0x0c400000 0 0x2000>, /* GICC */ 272 <0 0x0c410000 0 0x1000>, /* GICH */ 273 <0 0x0c420000 0 0x2000>; /* GICV */ 274 275 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 276 }; 277 278 topckgen: syscon@10000000 { 279 compatible = "mediatek,mt8365-topckgen", "syscon"; 280 reg = <0 0x10000000 0 0x1000>; 281 #clock-cells = <1>; 282 }; 283 284 infracfg: syscon@10001000 { 285 compatible = "mediatek,mt8365-infracfg", "syscon"; 286 reg = <0 0x10001000 0 0x1000>; 287 #clock-cells = <1>; 288 }; 289 290 pericfg: syscon@10003000 { 291 compatible = "mediatek,mt8365-pericfg", "syscon"; 292 reg = <0 0x10003000 0 0x1000>; 293 #clock-cells = <1>; 294 }; 295 296 syscfg_pctl: syscfg-pctl@10005000 { 297 compatible = "mediatek,mt8365-syscfg", "syscon"; 298 reg = <0 0x10005000 0 0x1000>; 299 }; 300 301 watchdog: watchdog@10007000 { 302 compatible = "mediatek,mt8365-wdt", "mediatek,mt6589-wdt"; 303 reg = <0 0x10007000 0 0x100>; 304 #reset-cells = <1>; 305 }; 306 307 pio: pinctrl@1000b000 { 308 compatible = "mediatek,mt8365-pinctrl"; 309 reg = <0 0x1000b000 0 0x1000>; 310 mediatek,pctl-regmap = <&syscfg_pctl>; 311 gpio-controller; 312 #gpio-cells = <2>; 313 interrupt-controller; 314 #interrupt-cells = <2>; 315 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 316 }; 317 318 apmixedsys: syscon@1000c000 { 319 compatible = "mediatek,mt8365-apmixedsys", "syscon"; 320 reg = <0 0x1000c000 0 0x1000>; 321 #clock-cells = <1>; 322 }; 323 324 pwrap: pwrap@1000d000 { 325 compatible = "mediatek,mt8365-pwrap"; 326 reg = <0 0x1000d000 0 0x1000>; 327 reg-names = "pwrap"; 328 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 329 clocks = <&infracfg CLK_IFR_PWRAP_SPI>, 330 <&infracfg CLK_IFR_PMIC_AP>, 331 <&infracfg CLK_IFR_PWRAP_SYS>, 332 <&infracfg CLK_IFR_PWRAP_TMR>; 333 clock-names = "spi", "wrap", "sys", "tmr"; 334 }; 335 336 keypad: keypad@10010000 { 337 compatible = "mediatek,mt8365-keypad", 338 "mediatek,mt6779-keypad"; 339 reg = <0 0x10010000 0 0x1000>; 340 wakeup-source; 341 interrupts = <GIC_SPI 124 IRQ_TYPE_EDGE_FALLING>; 342 clocks = <&clk26m>; 343 clock-names = "kpd"; 344 status = "disabled"; 345 }; 346 347 mcucfg: syscon@10200000 { 348 compatible = "mediatek,mt8365-mcucfg", "syscon"; 349 reg = <0 0x10200000 0 0x2000>; 350 #clock-cells = <1>; 351 }; 352 353 sysirq: interrupt-controller@10200a80 { 354 compatible = "mediatek,mt8365-sysirq", "mediatek,mt6577-sysirq"; 355 interrupt-controller; 356 #interrupt-cells = <3>; 357 interrupt-parent = <&gic>; 358 reg = <0 0x10200a80 0 0x20>; 359 }; 360 361 infracfg_nao: infracfg@1020e000 { 362 compatible = "mediatek,mt8365-infracfg", "syscon"; 363 reg = <0 0x1020e000 0 0x1000>; 364 #clock-cells = <1>; 365 }; 366 367 rng: rng@1020f000 { 368 compatible = "mediatek,mt8365-rng", "mediatek,mt7623-rng"; 369 reg = <0 0x1020f000 0 0x100>; 370 clocks = <&infracfg CLK_IFR_TRNG>; 371 clock-names = "rng"; 372 }; 373 374 apdma: dma-controller@11000280 { 375 compatible = "mediatek,mt8365-uart-dma", "mediatek,mt6577-uart-dma"; 376 reg = <0 0x11000280 0 0x80>, 377 <0 0x11000300 0 0x80>, 378 <0 0x11000380 0 0x80>, 379 <0 0x11000400 0 0x80>, 380 <0 0x11000580 0 0x80>, 381 <0 0x11000600 0 0x80>; 382 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_LOW>, 383 <GIC_SPI 46 IRQ_TYPE_LEVEL_LOW>, 384 <GIC_SPI 47 IRQ_TYPE_LEVEL_LOW>, 385 <GIC_SPI 48 IRQ_TYPE_LEVEL_LOW>, 386 <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>, 387 <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>; 388 dma-requests = <6>; 389 clocks = <&infracfg CLK_IFR_AP_DMA>; 390 clock-names = "apdma"; 391 #dma-cells = <1>; 392 }; 393 394 uart0: serial@11002000 { 395 compatible = "mediatek,mt8365-uart", "mediatek,mt6577-uart"; 396 reg = <0 0x11002000 0 0x1000>; 397 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_LOW>; 398 clocks = <&clk26m>, <&infracfg CLK_IFR_UART0>; 399 clock-names = "baud", "bus"; 400 dmas = <&apdma 0>, <&apdma 1>; 401 dma-names = "tx", "rx"; 402 status = "disabled"; 403 }; 404 405 uart1: serial@11003000 { 406 compatible = "mediatek,mt8365-uart", "mediatek,mt6577-uart"; 407 reg = <0 0x11003000 0 0x1000>; 408 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_LOW>; 409 clocks = <&clk26m>, <&infracfg CLK_IFR_UART1>; 410 clock-names = "baud", "bus"; 411 dmas = <&apdma 2>, <&apdma 3>; 412 dma-names = "tx", "rx"; 413 status = "disabled"; 414 }; 415 416 uart2: serial@11004000 { 417 compatible = "mediatek,mt8365-uart", "mediatek,mt6577-uart"; 418 reg = <0 0x11004000 0 0x1000>; 419 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_LOW>; 420 clocks = <&clk26m>, <&infracfg CLK_IFR_UART2>; 421 clock-names = "baud", "bus"; 422 dmas = <&apdma 4>, <&apdma 5>; 423 dma-names = "tx", "rx"; 424 status = "disabled"; 425 }; 426 427 pwm: pwm@11006000 { 428 compatible = "mediatek,mt8365-pwm"; 429 reg = <0 0x11006000 0 0x1000>; 430 #pwm-cells = <2>; 431 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>; 432 clocks = <&infracfg CLK_IFR_PWM_HCLK>, 433 <&infracfg CLK_IFR_PWM>, 434 <&infracfg CLK_IFR_PWM1>, 435 <&infracfg CLK_IFR_PWM2>, 436 <&infracfg CLK_IFR_PWM3>; 437 clock-names = "top", "main", "pwm1", "pwm2", "pwm3"; 438 }; 439 440 i2c0: i2c@11007000 { 441 compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c"; 442 reg = <0 0x11007000 0 0xa0>, <0 0x11000080 0 0x80>; 443 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_LOW>; 444 clock-div = <1>; 445 clocks = <&infracfg CLK_IFR_I2C0_AXI>, <&infracfg CLK_IFR_AP_DMA>; 446 clock-names = "main", "dma"; 447 #address-cells = <1>; 448 #size-cells = <0>; 449 status = "disabled"; 450 }; 451 452 i2c1: i2c@11008000 { 453 compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c"; 454 reg = <0 0x11008000 0 0xa0>, <0 0x11000100 0 0x80>; 455 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_LOW>; 456 clock-div = <1>; 457 clocks = <&infracfg CLK_IFR_I2C1_AXI>, <&infracfg CLK_IFR_AP_DMA>; 458 clock-names = "main", "dma"; 459 #address-cells = <1>; 460 #size-cells = <0>; 461 status = "disabled"; 462 }; 463 464 i2c2: i2c@11009000 { 465 compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c"; 466 reg = <0 0x11009000 0 0xa0>, <0 0x11000180 0 0x80>; 467 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_LOW>; 468 clock-div = <1>; 469 clocks = <&infracfg CLK_IFR_I2C2_AXI>, <&infracfg CLK_IFR_AP_DMA>; 470 clock-names = "main", "dma"; 471 #address-cells = <1>; 472 #size-cells = <0>; 473 status = "disabled"; 474 }; 475 476 spi: spi@1100a000 { 477 compatible = "mediatek,mt8365-spi", "mediatek,mt7622-spi"; 478 reg = <0 0x1100a000 0 0x100>; 479 #address-cells = <1>; 480 #size-cells = <0>; 481 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_LOW>; 482 clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>, 483 <&topckgen CLK_TOP_SPI_SEL>, 484 <&infracfg CLK_IFR_SPI0>; 485 clock-names = "parent-clk", "sel-clk", "spi-clk"; 486 status = "disabled"; 487 }; 488 489 i2c3: i2c@1100f000 { 490 compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c"; 491 reg = <0 0x1100f000 0 0xa0>, <0 0x11000200 0 0x80>; 492 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_LOW>; 493 clock-div = <1>; 494 clocks = <&infracfg CLK_IFR_I2C3_AXI>, <&infracfg CLK_IFR_AP_DMA>; 495 clock-names = "main", "dma"; 496 #address-cells = <1>; 497 #size-cells = <0>; 498 status = "disabled"; 499 }; 500 501 ssusb: usb@11201000 { 502 compatible = "mediatek,mt8365-mtu3", "mediatek,mtu3"; 503 reg = <0 0x11201000 0 0x2e00>, <0 0x11203e00 0 0x0100>; 504 reg-names = "mac", "ippc"; 505 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_LOW>; 506 phys = <&u2port0 PHY_TYPE_USB2>, 507 <&u2port1 PHY_TYPE_USB2>; 508 clocks = <&topckgen CLK_TOP_SSUSB_TOP_CK_EN>, 509 <&infracfg CLK_IFR_SSUSB_REF>, 510 <&infracfg CLK_IFR_SSUSB_SYS>, 511 <&infracfg CLK_IFR_ICUSB>; 512 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck"; 513 #address-cells = <2>; 514 #size-cells = <2>; 515 ranges; 516 status = "disabled"; 517 518 usb_host: usb@11200000 { 519 compatible = "mediatek,mt8365-xhci", "mediatek,mtk-xhci"; 520 reg = <0 0x11200000 0 0x1000>; 521 reg-names = "mac"; 522 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_LOW>; 523 clocks = <&topckgen CLK_TOP_SSUSB_TOP_CK_EN>, 524 <&infracfg CLK_IFR_SSUSB_REF>, 525 <&infracfg CLK_IFR_SSUSB_SYS>, 526 <&infracfg CLK_IFR_ICUSB>, 527 <&infracfg CLK_IFR_SSUSB_XHCI>; 528 clock-names = "sys_ck", "ref_ck", "mcu_ck", 529 "dma_ck", "xhci_ck"; 530 status = "disabled"; 531 }; 532 }; 533 534 mmc0: mmc@11230000 { 535 compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc"; 536 reg = <0 0x11230000 0 0x1000>, 537 <0 0x11cd0000 0 0x1000>; 538 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_LOW>; 539 clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>, 540 <&infracfg CLK_IFR_MSDC0_HCLK>, 541 <&infracfg CLK_IFR_MSDC0_SRC>; 542 clock-names = "source", "hclk", "source_cg"; 543 status = "disabled"; 544 }; 545 546 mmc1: mmc@11240000 { 547 compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc"; 548 reg = <0 0x11240000 0 0x1000>, 549 <0 0x11c90000 0 0x1000>; 550 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_LOW>; 551 clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>, 552 <&infracfg CLK_IFR_MSDC1_HCLK>, 553 <&infracfg CLK_IFR_MSDC1_SRC>; 554 clock-names = "source", "hclk", "source_cg"; 555 status = "disabled"; 556 }; 557 558 mmc2: mmc@11250000 { 559 compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc"; 560 reg = <0 0x11250000 0 0x1000>, 561 <0 0x11c60000 0 0x1000>; 562 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_LOW>; 563 clocks = <&topckgen CLK_TOP_MSDC50_2_SEL>, 564 <&infracfg CLK_IFR_MSDC2_HCLK>, 565 <&infracfg CLK_IFR_MSDC2_SRC>, 566 <&infracfg CLK_IFR_MSDC2_BK>, 567 <&infracfg CLK_IFR_AP_MSDC0>; 568 clock-names = "source", "hclk", "source_cg", 569 "bus_clk", "sys_cg"; 570 status = "disabled"; 571 }; 572 573 ethernet: ethernet@112a0000 { 574 compatible = "mediatek,mt8365-eth"; 575 reg = <0 0x112a0000 0 0x1000>; 576 mediatek,pericfg = <&infracfg>; 577 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 578 clocks = <&topckgen CLK_TOP_ETH_SEL>, 579 <&infracfg CLK_IFR_NIC_AXI>, 580 <&infracfg CLK_IFR_NIC_SLV_AXI>; 581 clock-names = "core", "reg", "trans"; 582 status = "disabled"; 583 }; 584 585 u3phy: t-phy@11cc0000 { 586 compatible = "mediatek,mt8365-tphy", "mediatek,generic-tphy-v2"; 587 #address-cells = <1>; 588 #size-cells = <1>; 589 ranges = <0 0 0x11cc0000 0x9000>; 590 591 u2port0: usb-phy@0 { 592 reg = <0x0 0x400>; 593 clocks = <&topckgen CLK_TOP_SSUSB_PHY_CK_EN>, 594 <&topckgen CLK_TOP_USB20_48M_EN>; 595 clock-names = "ref", "da_ref"; 596 #phy-cells = <1>; 597 }; 598 599 u2port1: usb-phy@1000 { 600 reg = <0x1000 0x400>; 601 clocks = <&topckgen CLK_TOP_SSUSB_PHY_CK_EN>, 602 <&topckgen CLK_TOP_USB20_48M_EN>; 603 clock-names = "ref", "da_ref"; 604 #phy-cells = <1>; 605 }; 606 }; 607 }; 608 609 timer { 610 compatible = "arm,armv8-timer"; 611 interrupt-parent = <&gic>; 612 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 613 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 614 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 615 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 616 }; 617 618 system_clk: dummy13m { 619 compatible = "fixed-clock"; 620 clock-frequency = <13000000>; 621 #clock-cells = <0>; 622 }; 623 624 systimer: timer@10017000 { 625 compatible = "mediatek,mt8365-systimer", "mediatek,mt6765-timer"; 626 reg = <0 0x10017000 0 0x100>; 627 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 628 clocks = <&system_clk>; 629 clock-names = "clk13m"; 630 }; 631}; 632