1 /*
2 * PCI code for the Freescale MPC52xx embedded CPU.
3 *
4 * Copyright (C) 2006 Secret Lab Technologies Ltd.
5 * Grant Likely <grant.likely@secretlab.ca>
6 * Copyright (C) 2004 Sylvain Munaut <tnt@246tNt.com>
7 *
8 * This file is licensed under the terms of the GNU General Public License
9 * version 2. This program is licensed "as is" without any warranty of any
10 * kind, whether express or implied.
11 */
12
13 #undef DEBUG
14
15 #include <linux/pci.h>
16 #include <linux/of_address.h>
17 #include <asm/mpc52xx.h>
18 #include <asm/delay.h>
19 #include <asm/machdep.h>
20 #include <linux/kernel.h>
21
22
23 /* ======================================================================== */
24 /* Structures mapping & Defines for PCI Unit */
25 /* ======================================================================== */
26
27 #define MPC52xx_PCI_GSCR_BM 0x40000000
28 #define MPC52xx_PCI_GSCR_PE 0x20000000
29 #define MPC52xx_PCI_GSCR_SE 0x10000000
30 #define MPC52xx_PCI_GSCR_XLB2PCI_MASK 0x07000000
31 #define MPC52xx_PCI_GSCR_XLB2PCI_SHIFT 24
32 #define MPC52xx_PCI_GSCR_IPG2PCI_MASK 0x00070000
33 #define MPC52xx_PCI_GSCR_IPG2PCI_SHIFT 16
34 #define MPC52xx_PCI_GSCR_BME 0x00004000
35 #define MPC52xx_PCI_GSCR_PEE 0x00002000
36 #define MPC52xx_PCI_GSCR_SEE 0x00001000
37 #define MPC52xx_PCI_GSCR_PR 0x00000001
38
39
40 #define MPC52xx_PCI_IWBTAR_TRANSLATION(proc_ad,pci_ad,size) \
41 ( ( (proc_ad) & 0xff000000 ) | \
42 ( (((size) - 1) >> 8) & 0x00ff0000 ) | \
43 ( ((pci_ad) >> 16) & 0x0000ff00 ) )
44
45 #define MPC52xx_PCI_IWCR_PACK(win0,win1,win2) (((win0) << 24) | \
46 ((win1) << 16) | \
47 ((win2) << 8))
48
49 #define MPC52xx_PCI_IWCR_DISABLE 0x0
50 #define MPC52xx_PCI_IWCR_ENABLE 0x1
51 #define MPC52xx_PCI_IWCR_READ 0x0
52 #define MPC52xx_PCI_IWCR_READ_LINE 0x2
53 #define MPC52xx_PCI_IWCR_READ_MULTI 0x4
54 #define MPC52xx_PCI_IWCR_MEM 0x0
55 #define MPC52xx_PCI_IWCR_IO 0x8
56
57 #define MPC52xx_PCI_TCR_P 0x01000000
58 #define MPC52xx_PCI_TCR_LD 0x00010000
59 #define MPC52xx_PCI_TCR_WCT8 0x00000008
60
61 #define MPC52xx_PCI_TBATR_DISABLE 0x0
62 #define MPC52xx_PCI_TBATR_ENABLE 0x1
63
64 struct mpc52xx_pci {
65 u32 idr; /* PCI + 0x00 */
66 u32 scr; /* PCI + 0x04 */
67 u32 ccrir; /* PCI + 0x08 */
68 u32 cr1; /* PCI + 0x0C */
69 u32 bar0; /* PCI + 0x10 */
70 u32 bar1; /* PCI + 0x14 */
71 u8 reserved1[16]; /* PCI + 0x18 */
72 u32 ccpr; /* PCI + 0x28 */
73 u32 sid; /* PCI + 0x2C */
74 u32 erbar; /* PCI + 0x30 */
75 u32 cpr; /* PCI + 0x34 */
76 u8 reserved2[4]; /* PCI + 0x38 */
77 u32 cr2; /* PCI + 0x3C */
78 u8 reserved3[32]; /* PCI + 0x40 */
79 u32 gscr; /* PCI + 0x60 */
80 u32 tbatr0; /* PCI + 0x64 */
81 u32 tbatr1; /* PCI + 0x68 */
82 u32 tcr; /* PCI + 0x6C */
83 u32 iw0btar; /* PCI + 0x70 */
84 u32 iw1btar; /* PCI + 0x74 */
85 u32 iw2btar; /* PCI + 0x78 */
86 u8 reserved4[4]; /* PCI + 0x7C */
87 u32 iwcr; /* PCI + 0x80 */
88 u32 icr; /* PCI + 0x84 */
89 u32 isr; /* PCI + 0x88 */
90 u32 arb; /* PCI + 0x8C */
91 u8 reserved5[104]; /* PCI + 0x90 */
92 u32 car; /* PCI + 0xF8 */
93 u8 reserved6[4]; /* PCI + 0xFC */
94 };
95
96 /* MPC5200 device tree match tables */
97 const struct of_device_id mpc52xx_pci_ids[] __initconst = {
98 { .type = "pci", .compatible = "fsl,mpc5200-pci", },
99 { .type = "pci", .compatible = "mpc5200-pci", },
100 {}
101 };
102
103 /* ======================================================================== */
104 /* PCI configuration access */
105 /* ======================================================================== */
106
107 static int
mpc52xx_pci_read_config(struct pci_bus * bus,unsigned int devfn,int offset,int len,u32 * val)108 mpc52xx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
109 int offset, int len, u32 *val)
110 {
111 struct pci_controller *hose = pci_bus_to_host(bus);
112 u32 value;
113
114 if (ppc_md.pci_exclude_device)
115 if (ppc_md.pci_exclude_device(hose, bus->number, devfn))
116 return PCIBIOS_DEVICE_NOT_FOUND;
117
118 out_be32(hose->cfg_addr,
119 (1 << 31) |
120 (bus->number << 16) |
121 (devfn << 8) |
122 (offset & 0xfc));
123 mb();
124
125 #if defined(CONFIG_PPC_MPC5200_BUGFIX)
126 if (bus->number) {
127 /* workaround for the bug 435 of the MPC5200 (L25R);
128 * Don't do 32 bits config access during type-1 cycles */
129 switch (len) {
130 case 1:
131 value = in_8(((u8 __iomem *)hose->cfg_data) +
132 (offset & 3));
133 break;
134 case 2:
135 value = in_le16(((u16 __iomem *)hose->cfg_data) +
136 ((offset>>1) & 1));
137 break;
138
139 default:
140 value = in_le16((u16 __iomem *)hose->cfg_data) |
141 (in_le16(((u16 __iomem *)hose->cfg_data) + 1) << 16);
142 break;
143 }
144 }
145 else
146 #endif
147 {
148 value = in_le32(hose->cfg_data);
149
150 if (len != 4) {
151 value >>= ((offset & 0x3) << 3);
152 value &= 0xffffffff >> (32 - (len << 3));
153 }
154 }
155
156 *val = value;
157
158 out_be32(hose->cfg_addr, 0);
159 mb();
160
161 return PCIBIOS_SUCCESSFUL;
162 }
163
164 static int
mpc52xx_pci_write_config(struct pci_bus * bus,unsigned int devfn,int offset,int len,u32 val)165 mpc52xx_pci_write_config(struct pci_bus *bus, unsigned int devfn,
166 int offset, int len, u32 val)
167 {
168 struct pci_controller *hose = pci_bus_to_host(bus);
169 u32 value, mask;
170
171 if (ppc_md.pci_exclude_device)
172 if (ppc_md.pci_exclude_device(hose, bus->number, devfn))
173 return PCIBIOS_DEVICE_NOT_FOUND;
174
175 out_be32(hose->cfg_addr,
176 (1 << 31) |
177 (bus->number << 16) |
178 (devfn << 8) |
179 (offset & 0xfc));
180 mb();
181
182 #if defined(CONFIG_PPC_MPC5200_BUGFIX)
183 if (bus->number) {
184 /* workaround for the bug 435 of the MPC5200 (L25R);
185 * Don't do 32 bits config access during type-1 cycles */
186 switch (len) {
187 case 1:
188 out_8(((u8 __iomem *)hose->cfg_data) +
189 (offset & 3), val);
190 break;
191 case 2:
192 out_le16(((u16 __iomem *)hose->cfg_data) +
193 ((offset>>1) & 1), val);
194 break;
195
196 default:
197 out_le16((u16 __iomem *)hose->cfg_data,
198 (u16)val);
199 out_le16(((u16 __iomem *)hose->cfg_data) + 1,
200 (u16)(val>>16));
201 break;
202 }
203 }
204 else
205 #endif
206 {
207 if (len != 4) {
208 value = in_le32(hose->cfg_data);
209
210 offset = (offset & 0x3) << 3;
211 mask = (0xffffffff >> (32 - (len << 3)));
212 mask <<= offset;
213
214 value &= ~mask;
215 val = value | ((val << offset) & mask);
216 }
217
218 out_le32(hose->cfg_data, val);
219 }
220 mb();
221
222 out_be32(hose->cfg_addr, 0);
223 mb();
224
225 return PCIBIOS_SUCCESSFUL;
226 }
227
228 static struct pci_ops mpc52xx_pci_ops = {
229 .read = mpc52xx_pci_read_config,
230 .write = mpc52xx_pci_write_config
231 };
232
233
234 /* ======================================================================== */
235 /* PCI setup */
236 /* ======================================================================== */
237
238 static void __init
mpc52xx_pci_setup(struct pci_controller * hose,struct mpc52xx_pci __iomem * pci_regs,phys_addr_t pci_phys)239 mpc52xx_pci_setup(struct pci_controller *hose,
240 struct mpc52xx_pci __iomem *pci_regs, phys_addr_t pci_phys)
241 {
242 struct resource *res;
243 u32 tmp;
244 int iwcr0 = 0, iwcr1 = 0, iwcr2 = 0;
245
246 pr_debug("%s(hose=%p, pci_regs=%p)\n", __func__, hose, pci_regs);
247
248 /* pci_process_bridge_OF_ranges() found all our addresses for us;
249 * now store them in the right places */
250 hose->cfg_addr = &pci_regs->car;
251 hose->cfg_data = hose->io_base_virt;
252
253 /* Control regs */
254 tmp = in_be32(&pci_regs->scr);
255 tmp |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
256 out_be32(&pci_regs->scr, tmp);
257
258 /* Memory windows */
259 res = &hose->mem_resources[0];
260 if (res->flags) {
261 pr_debug("mem_resource[0] = %pr\n", res);
262 out_be32(&pci_regs->iw0btar,
263 MPC52xx_PCI_IWBTAR_TRANSLATION(res->start, res->start,
264 resource_size(res)));
265 iwcr0 = MPC52xx_PCI_IWCR_ENABLE | MPC52xx_PCI_IWCR_MEM;
266 if (res->flags & IORESOURCE_PREFETCH)
267 iwcr0 |= MPC52xx_PCI_IWCR_READ_MULTI;
268 else
269 iwcr0 |= MPC52xx_PCI_IWCR_READ;
270 }
271
272 res = &hose->mem_resources[1];
273 if (res->flags) {
274 pr_debug("mem_resource[1] = %pr\n", res);
275 out_be32(&pci_regs->iw1btar,
276 MPC52xx_PCI_IWBTAR_TRANSLATION(res->start, res->start,
277 resource_size(res)));
278 iwcr1 = MPC52xx_PCI_IWCR_ENABLE | MPC52xx_PCI_IWCR_MEM;
279 if (res->flags & IORESOURCE_PREFETCH)
280 iwcr1 |= MPC52xx_PCI_IWCR_READ_MULTI;
281 else
282 iwcr1 |= MPC52xx_PCI_IWCR_READ;
283 }
284
285 /* IO resources */
286 res = &hose->io_resource;
287 if (!res) {
288 printk(KERN_ERR "%s: Didn't find IO resources\n", __FILE__);
289 return;
290 }
291 pr_debug(".io_resource = %pr .io_base_phys=0x%pa\n",
292 res, &hose->io_base_phys);
293 out_be32(&pci_regs->iw2btar,
294 MPC52xx_PCI_IWBTAR_TRANSLATION(hose->io_base_phys,
295 res->start,
296 resource_size(res)));
297 iwcr2 = MPC52xx_PCI_IWCR_ENABLE | MPC52xx_PCI_IWCR_IO;
298
299 /* Set all the IWCR fields at once; they're in the same reg */
300 out_be32(&pci_regs->iwcr, MPC52xx_PCI_IWCR_PACK(iwcr0, iwcr1, iwcr2));
301
302 /* Map IMMR onto PCI bus */
303 pci_phys &= 0xfffc0000; /* bar0 has only 14 significant bits */
304 out_be32(&pci_regs->tbatr0, MPC52xx_PCI_TBATR_ENABLE | pci_phys);
305 out_be32(&pci_regs->bar0, PCI_BASE_ADDRESS_MEM_PREFETCH | pci_phys);
306
307 /* Map memory onto PCI bus */
308 out_be32(&pci_regs->tbatr1, MPC52xx_PCI_TBATR_ENABLE);
309 out_be32(&pci_regs->bar1, PCI_BASE_ADDRESS_MEM_PREFETCH);
310
311 out_be32(&pci_regs->tcr, MPC52xx_PCI_TCR_LD | MPC52xx_PCI_TCR_WCT8);
312
313 tmp = in_be32(&pci_regs->gscr);
314 #if 0
315 /* Reset the exteral bus ( internal PCI controller is NOT reset ) */
316 /* Not necessary and can be a bad thing if for example the bootloader
317 is displaying a splash screen or ... Just left here for
318 documentation purpose if anyone need it */
319 out_be32(&pci_regs->gscr, tmp | MPC52xx_PCI_GSCR_PR);
320 udelay(50);
321 #endif
322
323 /* Make sure the PCI bridge is out of reset */
324 out_be32(&pci_regs->gscr, tmp & ~MPC52xx_PCI_GSCR_PR);
325 }
326
327 static void
mpc52xx_pci_fixup_resources(struct pci_dev * dev)328 mpc52xx_pci_fixup_resources(struct pci_dev *dev)
329 {
330 struct resource *res;
331
332 pr_debug("%s() %.4x:%.4x\n", __func__, dev->vendor, dev->device);
333
334 /* We don't rely on boot loader for PCI and resets all
335 devices */
336 pci_dev_for_each_resource(dev, res) {
337 if (res->end > res->start) { /* Only valid resources */
338 res->end -= res->start;
339 res->start = 0;
340 res->flags |= IORESOURCE_UNSET;
341 }
342 }
343
344 /* The PCI Host bridge of MPC52xx has a prefetch memory resource
345 fixed to 1Gb. Doesn't fit in the resource system so we remove it */
346 if ( (dev->vendor == PCI_VENDOR_ID_MOTOROLA) &&
347 ( dev->device == PCI_DEVICE_ID_MOTOROLA_MPC5200
348 || dev->device == PCI_DEVICE_ID_MOTOROLA_MPC5200B) ) {
349 struct resource *res = &dev->resource[1];
350 res->start = res->end = res->flags = 0;
351 }
352 }
353
354 int __init
mpc52xx_add_bridge(struct device_node * node)355 mpc52xx_add_bridge(struct device_node *node)
356 {
357 int len;
358 struct mpc52xx_pci __iomem *pci_regs;
359 struct pci_controller *hose;
360 const int *bus_range;
361 struct resource rsrc;
362
363 pr_debug("Adding MPC52xx PCI host bridge %pOF\n", node);
364
365 pci_add_flags(PCI_REASSIGN_ALL_BUS);
366
367 if (of_address_to_resource(node, 0, &rsrc) != 0) {
368 printk(KERN_ERR "Can't get %pOF resources\n", node);
369 return -EINVAL;
370 }
371
372 bus_range = of_get_property(node, "bus-range", &len);
373 if (bus_range == NULL || len < 2 * sizeof(int)) {
374 printk(KERN_WARNING "Can't get %pOF bus-range, assume bus 0\n",
375 node);
376 bus_range = NULL;
377 }
378
379 /* There are some PCI quirks on the 52xx, register the hook to
380 * fix them. */
381 ppc_md.pcibios_fixup_resources = mpc52xx_pci_fixup_resources;
382
383 /* Alloc and initialize the pci controller. Values in the device
384 * tree are needed to configure the 52xx PCI controller. Rather
385 * than parse the tree here, let pci_process_bridge_OF_ranges()
386 * do it for us and extract the values after the fact */
387 hose = pcibios_alloc_controller(node);
388 if (!hose)
389 return -ENOMEM;
390
391 hose->first_busno = bus_range ? bus_range[0] : 0;
392 hose->last_busno = bus_range ? bus_range[1] : 0xff;
393
394 hose->ops = &mpc52xx_pci_ops;
395
396 pci_regs = ioremap(rsrc.start, resource_size(&rsrc));
397 if (!pci_regs)
398 return -ENOMEM;
399
400 pci_process_bridge_OF_ranges(hose, node, 1);
401
402 /* Finish setting up PCI using values obtained by
403 * pci_proces_bridge_OF_ranges */
404 mpc52xx_pci_setup(hose, pci_regs, rsrc.start);
405
406 return 0;
407 }
408
mpc52xx_setup_pci(void)409 void __init mpc52xx_setup_pci(void)
410 {
411 struct device_node *pci;
412
413 pci = of_find_matching_node(NULL, mpc52xx_pci_ids);
414 if (!pci)
415 return;
416
417 mpc52xx_add_bridge(pci);
418 of_node_put(pci);
419 }
420