1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #ifndef _mmhub_3_0_0_OFFSET_HEADER 24 #define _mmhub_3_0_0_OFFSET_HEADER 25 26 27 28 // addressBlock: mmhub_dagbdec 29 // base address: 0x68000 30 #define regDAGB0_RDCLI0 0x0000 31 #define regDAGB0_RDCLI0_BASE_IDX 0 32 #define regDAGB0_RDCLI1 0x0001 33 #define regDAGB0_RDCLI1_BASE_IDX 0 34 #define regDAGB0_RDCLI2 0x0002 35 #define regDAGB0_RDCLI2_BASE_IDX 0 36 #define regDAGB0_RDCLI3 0x0003 37 #define regDAGB0_RDCLI3_BASE_IDX 0 38 #define regDAGB0_RDCLI4 0x0004 39 #define regDAGB0_RDCLI4_BASE_IDX 0 40 #define regDAGB0_RDCLI5 0x0005 41 #define regDAGB0_RDCLI5_BASE_IDX 0 42 #define regDAGB0_RDCLI6 0x0006 43 #define regDAGB0_RDCLI6_BASE_IDX 0 44 #define regDAGB0_RDCLI7 0x0007 45 #define regDAGB0_RDCLI7_BASE_IDX 0 46 #define regDAGB0_RDCLI8 0x0008 47 #define regDAGB0_RDCLI8_BASE_IDX 0 48 #define regDAGB0_RDCLI9 0x0009 49 #define regDAGB0_RDCLI9_BASE_IDX 0 50 #define regDAGB0_RDCLI10 0x000a 51 #define regDAGB0_RDCLI10_BASE_IDX 0 52 #define regDAGB0_RDCLI11 0x000b 53 #define regDAGB0_RDCLI11_BASE_IDX 0 54 #define regDAGB0_RDCLI12 0x000c 55 #define regDAGB0_RDCLI12_BASE_IDX 0 56 #define regDAGB0_RDCLI13 0x000d 57 #define regDAGB0_RDCLI13_BASE_IDX 0 58 #define regDAGB0_RDCLI14 0x000e 59 #define regDAGB0_RDCLI14_BASE_IDX 0 60 #define regDAGB0_RDCLI15 0x000f 61 #define regDAGB0_RDCLI15_BASE_IDX 0 62 #define regDAGB0_RDCLI16 0x0010 63 #define regDAGB0_RDCLI16_BASE_IDX 0 64 #define regDAGB0_RDCLI17 0x0011 65 #define regDAGB0_RDCLI17_BASE_IDX 0 66 #define regDAGB0_RDCLI18 0x0012 67 #define regDAGB0_RDCLI18_BASE_IDX 0 68 #define regDAGB0_RDCLI19 0x0013 69 #define regDAGB0_RDCLI19_BASE_IDX 0 70 #define regDAGB0_RDCLI20 0x0014 71 #define regDAGB0_RDCLI20_BASE_IDX 0 72 #define regDAGB0_RDCLI21 0x0015 73 #define regDAGB0_RDCLI21_BASE_IDX 0 74 #define regDAGB0_RDCLI22 0x0016 75 #define regDAGB0_RDCLI22_BASE_IDX 0 76 #define regDAGB0_RDCLI23 0x0017 77 #define regDAGB0_RDCLI23_BASE_IDX 0 78 #define regDAGB0_RD_CNTL 0x0018 79 #define regDAGB0_RD_CNTL_BASE_IDX 0 80 #define regDAGB0_RD_IO_CNTL 0x0019 81 #define regDAGB0_RD_IO_CNTL_BASE_IDX 0 82 #define regDAGB0_RD_GMI_CNTL 0x001a 83 #define regDAGB0_RD_GMI_CNTL_BASE_IDX 0 84 #define regDAGB0_RD_ADDR_DAGB 0x001b 85 #define regDAGB0_RD_ADDR_DAGB_BASE_IDX 0 86 #define regDAGB0_RD_CGTT_CLK_CTRL 0x001c 87 #define regDAGB0_RD_CGTT_CLK_CTRL_BASE_IDX 0 88 #define regDAGB0_L1TLB_RD_CGTT_CLK_CTRL 0x001d 89 #define regDAGB0_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX 0 90 #define regDAGB0_RD_ADDR_DAGB_MAX_BURST0 0x001e 91 #define regDAGB0_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX 0 92 #define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER0 0x001f 93 #define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0 94 #define regDAGB0_RD_ADDR_DAGB_MAX_BURST1 0x0020 95 #define regDAGB0_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX 0 96 #define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER1 0x0021 97 #define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0 98 #define regDAGB0_RD_ADDR_DAGB_MAX_BURST2 0x0022 99 #define regDAGB0_RD_ADDR_DAGB_MAX_BURST2_BASE_IDX 0 100 #define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER2 0x0023 101 #define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER2_BASE_IDX 0 102 #define regDAGB0_RD_VC0_CNTL 0x0024 103 #define regDAGB0_RD_VC0_CNTL_BASE_IDX 0 104 #define regDAGB0_RD_VC1_CNTL 0x0025 105 #define regDAGB0_RD_VC1_CNTL_BASE_IDX 0 106 #define regDAGB0_RD_VC2_CNTL 0x0026 107 #define regDAGB0_RD_VC2_CNTL_BASE_IDX 0 108 #define regDAGB0_RD_VC3_CNTL 0x0027 109 #define regDAGB0_RD_VC3_CNTL_BASE_IDX 0 110 #define regDAGB0_RD_VC4_CNTL 0x0028 111 #define regDAGB0_RD_VC4_CNTL_BASE_IDX 0 112 #define regDAGB0_RD_VC5_CNTL 0x0029 113 #define regDAGB0_RD_VC5_CNTL_BASE_IDX 0 114 #define regDAGB0_RD_IO_VC_CNTL 0x002a 115 #define regDAGB0_RD_IO_VC_CNTL_BASE_IDX 0 116 #define regDAGB0_RD_GMI_VC_CNTL 0x002b 117 #define regDAGB0_RD_GMI_VC_CNTL_BASE_IDX 0 118 #define regDAGB0_RD_CNTL_MISC 0x002c 119 #define regDAGB0_RD_CNTL_MISC_BASE_IDX 0 120 #define regDAGB0_RD_TLB_CREDIT 0x002d 121 #define regDAGB0_RD_TLB_CREDIT_BASE_IDX 0 122 #define regDAGB0_RD_RDRET_CREDIT_CNTL 0x002e 123 #define regDAGB0_RD_RDRET_CREDIT_CNTL_BASE_IDX 0 124 #define regDAGB0_RD_RDRET_CREDIT_CNTL2 0x002f 125 #define regDAGB0_RD_RDRET_CREDIT_CNTL2_BASE_IDX 0 126 #define regDAGB0_RDCLI_ASK_PENDING 0x0030 127 #define regDAGB0_RDCLI_ASK_PENDING_BASE_IDX 0 128 #define regDAGB0_RDCLI_GO_PENDING 0x0031 129 #define regDAGB0_RDCLI_GO_PENDING_BASE_IDX 0 130 #define regDAGB0_RDCLI_GBLSEND_PENDING 0x0032 131 #define regDAGB0_RDCLI_GBLSEND_PENDING_BASE_IDX 0 132 #define regDAGB0_RDCLI_TLB_PENDING 0x0033 133 #define regDAGB0_RDCLI_TLB_PENDING_BASE_IDX 0 134 #define regDAGB0_RDCLI_OARB_PENDING 0x0034 135 #define regDAGB0_RDCLI_OARB_PENDING_BASE_IDX 0 136 #define regDAGB0_RDCLI_ASK2ARB_PENDING 0x0035 137 #define regDAGB0_RDCLI_ASK2ARB_PENDING_BASE_IDX 0 138 #define regDAGB0_RDCLI_ASK2DF_PENDING 0x0036 139 #define regDAGB0_RDCLI_ASK2DF_PENDING_BASE_IDX 0 140 #define regDAGB0_RDCLI_OSD_PENDING 0x0037 141 #define regDAGB0_RDCLI_OSD_PENDING_BASE_IDX 0 142 #define regDAGB0_RDCLI_ASK_OSD_PENDING 0x0038 143 #define regDAGB0_RDCLI_ASK_OSD_PENDING_BASE_IDX 0 144 #define regDAGB0_RDCLI_NOALLOC_OVERRIDE 0x0039 145 #define regDAGB0_RDCLI_NOALLOC_OVERRIDE_BASE_IDX 0 146 #define regDAGB0_RDCLI_NOALLOC_OVERRIDE_VALUE 0x003a 147 #define regDAGB0_RDCLI_NOALLOC_OVERRIDE_VALUE_BASE_IDX 0 148 #define regDAGB0_WRCLI0 0x003b 149 #define regDAGB0_WRCLI0_BASE_IDX 0 150 #define regDAGB0_WRCLI1 0x003c 151 #define regDAGB0_WRCLI1_BASE_IDX 0 152 #define regDAGB0_WRCLI2 0x003d 153 #define regDAGB0_WRCLI2_BASE_IDX 0 154 #define regDAGB0_WRCLI3 0x003e 155 #define regDAGB0_WRCLI3_BASE_IDX 0 156 #define regDAGB0_WRCLI4 0x003f 157 #define regDAGB0_WRCLI4_BASE_IDX 0 158 #define regDAGB0_WRCLI5 0x0040 159 #define regDAGB0_WRCLI5_BASE_IDX 0 160 #define regDAGB0_WRCLI6 0x0041 161 #define regDAGB0_WRCLI6_BASE_IDX 0 162 #define regDAGB0_WRCLI7 0x0042 163 #define regDAGB0_WRCLI7_BASE_IDX 0 164 #define regDAGB0_WRCLI8 0x0043 165 #define regDAGB0_WRCLI8_BASE_IDX 0 166 #define regDAGB0_WRCLI9 0x0044 167 #define regDAGB0_WRCLI9_BASE_IDX 0 168 #define regDAGB0_WRCLI10 0x0045 169 #define regDAGB0_WRCLI10_BASE_IDX 0 170 #define regDAGB0_WRCLI11 0x0046 171 #define regDAGB0_WRCLI11_BASE_IDX 0 172 #define regDAGB0_WRCLI12 0x0047 173 #define regDAGB0_WRCLI12_BASE_IDX 0 174 #define regDAGB0_WRCLI13 0x0048 175 #define regDAGB0_WRCLI13_BASE_IDX 0 176 #define regDAGB0_WRCLI14 0x0049 177 #define regDAGB0_WRCLI14_BASE_IDX 0 178 #define regDAGB0_WRCLI15 0x004a 179 #define regDAGB0_WRCLI15_BASE_IDX 0 180 #define regDAGB0_WRCLI16 0x004b 181 #define regDAGB0_WRCLI16_BASE_IDX 0 182 #define regDAGB0_WRCLI17 0x004c 183 #define regDAGB0_WRCLI17_BASE_IDX 0 184 #define regDAGB0_WRCLI18 0x004d 185 #define regDAGB0_WRCLI18_BASE_IDX 0 186 #define regDAGB0_WRCLI19 0x004e 187 #define regDAGB0_WRCLI19_BASE_IDX 0 188 #define regDAGB0_WRCLI20 0x004f 189 #define regDAGB0_WRCLI20_BASE_IDX 0 190 #define regDAGB0_WRCLI21 0x0050 191 #define regDAGB0_WRCLI21_BASE_IDX 0 192 #define regDAGB0_WRCLI22 0x0051 193 #define regDAGB0_WRCLI22_BASE_IDX 0 194 #define regDAGB0_WRCLI23 0x0052 195 #define regDAGB0_WRCLI23_BASE_IDX 0 196 #define regDAGB0_WR_CNTL 0x0053 197 #define regDAGB0_WR_CNTL_BASE_IDX 0 198 #define regDAGB0_WR_IO_CNTL 0x0054 199 #define regDAGB0_WR_IO_CNTL_BASE_IDX 0 200 #define regDAGB0_WR_GMI_CNTL 0x0055 201 #define regDAGB0_WR_GMI_CNTL_BASE_IDX 0 202 #define regDAGB0_WR_ADDR_DAGB 0x0056 203 #define regDAGB0_WR_ADDR_DAGB_BASE_IDX 0 204 #define regDAGB0_WR_CGTT_CLK_CTRL 0x0057 205 #define regDAGB0_WR_CGTT_CLK_CTRL_BASE_IDX 0 206 #define regDAGB0_L1TLB_WR_CGTT_CLK_CTRL 0x0058 207 #define regDAGB0_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX 0 208 #define regDAGB0_WR_ADDR_DAGB_MAX_BURST0 0x0059 209 #define regDAGB0_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX 0 210 #define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER0 0x005a 211 #define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0 212 #define regDAGB0_WR_ADDR_DAGB_MAX_BURST1 0x005b 213 #define regDAGB0_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX 0 214 #define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER1 0x005c 215 #define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0 216 #define regDAGB0_WR_ADDR_DAGB_MAX_BURST2 0x005d 217 #define regDAGB0_WR_ADDR_DAGB_MAX_BURST2_BASE_IDX 0 218 #define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER2 0x005e 219 #define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER2_BASE_IDX 0 220 #define regDAGB0_WR_DATA_DAGB 0x005f 221 #define regDAGB0_WR_DATA_DAGB_BASE_IDX 0 222 #define regDAGB0_WR_DATA_DAGB_MAX_BURST0 0x0060 223 #define regDAGB0_WR_DATA_DAGB_MAX_BURST0_BASE_IDX 0 224 #define regDAGB0_WR_DATA_DAGB_LAZY_TIMER0 0x0061 225 #define regDAGB0_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX 0 226 #define regDAGB0_WR_DATA_DAGB_MAX_BURST1 0x0062 227 #define regDAGB0_WR_DATA_DAGB_MAX_BURST1_BASE_IDX 0 228 #define regDAGB0_WR_DATA_DAGB_LAZY_TIMER1 0x0063 229 #define regDAGB0_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX 0 230 #define regDAGB0_WR_DATA_DAGB_MAX_BURST2 0x0064 231 #define regDAGB0_WR_DATA_DAGB_MAX_BURST2_BASE_IDX 0 232 #define regDAGB0_WR_DATA_DAGB_LAZY_TIMER2 0x0065 233 #define regDAGB0_WR_DATA_DAGB_LAZY_TIMER2_BASE_IDX 0 234 #define regDAGB0_WR_VC0_CNTL 0x0066 235 #define regDAGB0_WR_VC0_CNTL_BASE_IDX 0 236 #define regDAGB0_WR_VC1_CNTL 0x0067 237 #define regDAGB0_WR_VC1_CNTL_BASE_IDX 0 238 #define regDAGB0_WR_VC2_CNTL 0x0068 239 #define regDAGB0_WR_VC2_CNTL_BASE_IDX 0 240 #define regDAGB0_WR_VC3_CNTL 0x0069 241 #define regDAGB0_WR_VC3_CNTL_BASE_IDX 0 242 #define regDAGB0_WR_VC4_CNTL 0x006a 243 #define regDAGB0_WR_VC4_CNTL_BASE_IDX 0 244 #define regDAGB0_WR_VC5_CNTL 0x006b 245 #define regDAGB0_WR_VC5_CNTL_BASE_IDX 0 246 #define regDAGB0_WR_IO_VC_CNTL 0x006c 247 #define regDAGB0_WR_IO_VC_CNTL_BASE_IDX 0 248 #define regDAGB0_WR_GMI_VC_CNTL 0x006d 249 #define regDAGB0_WR_GMI_VC_CNTL_BASE_IDX 0 250 #define regDAGB0_WR_CNTL_MISC 0x006e 251 #define regDAGB0_WR_CNTL_MISC_BASE_IDX 0 252 #define regDAGB0_WR_TLB_CREDIT 0x006f 253 #define regDAGB0_WR_TLB_CREDIT_BASE_IDX 0 254 #define regDAGB0_WR_DATA_CREDIT 0x0070 255 #define regDAGB0_WR_DATA_CREDIT_BASE_IDX 0 256 #define regDAGB0_WR_MISC_CREDIT 0x0071 257 #define regDAGB0_WR_MISC_CREDIT_BASE_IDX 0 258 #define regDAGB0_WR_DATA_FIFO_CREDIT_CNTL1 0x0072 259 #define regDAGB0_WR_DATA_FIFO_CREDIT_CNTL1_BASE_IDX 0 260 #define regDAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1 0x0073 261 #define regDAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1_BASE_IDX 0 262 #define regDAGB0_WRCLI_ASK_PENDING 0x0074 263 #define regDAGB0_WRCLI_ASK_PENDING_BASE_IDX 0 264 #define regDAGB0_WRCLI_GO_PENDING 0x0075 265 #define regDAGB0_WRCLI_GO_PENDING_BASE_IDX 0 266 #define regDAGB0_WRCLI_GBLSEND_PENDING 0x0076 267 #define regDAGB0_WRCLI_GBLSEND_PENDING_BASE_IDX 0 268 #define regDAGB0_WRCLI_TLB_PENDING 0x0077 269 #define regDAGB0_WRCLI_TLB_PENDING_BASE_IDX 0 270 #define regDAGB0_WRCLI_OARB_PENDING 0x0078 271 #define regDAGB0_WRCLI_OARB_PENDING_BASE_IDX 0 272 #define regDAGB0_WRCLI_ASK2ARB_PENDING 0x0079 273 #define regDAGB0_WRCLI_ASK2ARB_PENDING_BASE_IDX 0 274 #define regDAGB0_WRCLI_ASK2DF_PENDING 0x007a 275 #define regDAGB0_WRCLI_ASK2DF_PENDING_BASE_IDX 0 276 #define regDAGB0_WRCLI_OSD_PENDING 0x007b 277 #define regDAGB0_WRCLI_OSD_PENDING_BASE_IDX 0 278 #define regDAGB0_WRCLI_ASK_OSD_PENDING 0x007c 279 #define regDAGB0_WRCLI_ASK_OSD_PENDING_BASE_IDX 0 280 #define regDAGB0_WRCLI_DBUS_ASK_PENDING 0x007d 281 #define regDAGB0_WRCLI_DBUS_ASK_PENDING_BASE_IDX 0 282 #define regDAGB0_WRCLI_DBUS_GO_PENDING 0x007e 283 #define regDAGB0_WRCLI_DBUS_GO_PENDING_BASE_IDX 0 284 #define regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE 0x007f 285 #define regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_BASE_IDX 0 286 #define regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE 0x0080 287 #define regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE_BASE_IDX 0 288 #define regDAGB0_WRCLI_NOALLOC_OVERRIDE 0x0081 289 #define regDAGB0_WRCLI_NOALLOC_OVERRIDE_BASE_IDX 0 290 #define regDAGB0_WRCLI_NOALLOC_OVERRIDE_VALUE 0x0082 291 #define regDAGB0_WRCLI_NOALLOC_OVERRIDE_VALUE_BASE_IDX 0 292 #define regDAGB0_DAGB_DLY 0x0083 293 #define regDAGB0_DAGB_DLY_BASE_IDX 0 294 #define regDAGB0_CNTL_MISC 0x0084 295 #define regDAGB0_CNTL_MISC_BASE_IDX 0 296 #define regDAGB0_CNTL_MISC2 0x0085 297 #define regDAGB0_CNTL_MISC2_BASE_IDX 0 298 #define regDAGB0_FIFO_EMPTY 0x0086 299 #define regDAGB0_FIFO_EMPTY_BASE_IDX 0 300 #define regDAGB0_FIFO_FULL 0x0087 301 #define regDAGB0_FIFO_FULL_BASE_IDX 0 302 #define regDAGB0_RD_CREDITS_FULL 0x0088 303 #define regDAGB0_RD_CREDITS_FULL_BASE_IDX 0 304 #define regDAGB0_WR_CREDITS_FULL 0x0089 305 #define regDAGB0_WR_CREDITS_FULL_BASE_IDX 0 306 #define regDAGB0_PERFCOUNTER_LO 0x008a 307 #define regDAGB0_PERFCOUNTER_LO_BASE_IDX 0 308 #define regDAGB0_PERFCOUNTER_HI 0x008b 309 #define regDAGB0_PERFCOUNTER_HI_BASE_IDX 0 310 #define regDAGB0_PERFCOUNTER0_CFG 0x008c 311 #define regDAGB0_PERFCOUNTER0_CFG_BASE_IDX 0 312 #define regDAGB0_PERFCOUNTER1_CFG 0x008d 313 #define regDAGB0_PERFCOUNTER1_CFG_BASE_IDX 0 314 #define regDAGB0_PERFCOUNTER2_CFG 0x008e 315 #define regDAGB0_PERFCOUNTER2_CFG_BASE_IDX 0 316 #define regDAGB0_PERFCOUNTER_RSLT_CNTL 0x008f 317 #define regDAGB0_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 318 #define regDAGB0_L1TLB_REG_RW 0x0090 319 #define regDAGB0_L1TLB_REG_RW_BASE_IDX 0 320 #define regDAGB0_RESERVE1 0x0091 321 #define regDAGB0_RESERVE1_BASE_IDX 0 322 #define regDAGB0_RESERVE2 0x0092 323 #define regDAGB0_RESERVE2_BASE_IDX 0 324 #define regDAGB0_RESERVE3 0x0093 325 #define regDAGB0_RESERVE3_BASE_IDX 0 326 #define regDAGB0_RESERVE4 0x0094 327 #define regDAGB0_RESERVE4_BASE_IDX 0 328 #define regDAGB0_SDP_RD_BW_CNTL 0x0095 329 #define regDAGB0_SDP_RD_BW_CNTL_BASE_IDX 0 330 #define regDAGB0_SDP_PRIORITY_OVERRIDE 0x0096 331 #define regDAGB0_SDP_PRIORITY_OVERRIDE_BASE_IDX 0 332 #define regDAGB0_SDP_RD_PRIORITY 0x0097 333 #define regDAGB0_SDP_RD_PRIORITY_BASE_IDX 0 334 #define regDAGB0_SDP_WR_PRIORITY 0x0098 335 #define regDAGB0_SDP_WR_PRIORITY_BASE_IDX 0 336 #define regDAGB0_SDP_RD_CLI2SDP_VC_MAP 0x0099 337 #define regDAGB0_SDP_RD_CLI2SDP_VC_MAP_BASE_IDX 0 338 #define regDAGB0_SDP_WR_CLI2SDP_VC_MAP 0x009a 339 #define regDAGB0_SDP_WR_CLI2SDP_VC_MAP_BASE_IDX 0 340 #define regDAGB0_SDP_ENABLE 0x009b 341 #define regDAGB0_SDP_ENABLE_BASE_IDX 0 342 #define regDAGB0_SDP_CREDITS 0x009c 343 #define regDAGB0_SDP_CREDITS_BASE_IDX 0 344 #define regDAGB0_SDP_TAG_RESERVE0 0x009d 345 #define regDAGB0_SDP_TAG_RESERVE0_BASE_IDX 0 346 #define regDAGB0_SDP_TAG_RESERVE1 0x009e 347 #define regDAGB0_SDP_TAG_RESERVE1_BASE_IDX 0 348 #define regDAGB0_SDP_VCC_RESERVE0 0x009f 349 #define regDAGB0_SDP_VCC_RESERVE0_BASE_IDX 0 350 #define regDAGB0_SDP_VCC_RESERVE1 0x00a0 351 #define regDAGB0_SDP_VCC_RESERVE1_BASE_IDX 0 352 #define regDAGB0_SDP_ERR_STATUS 0x00a1 353 #define regDAGB0_SDP_ERR_STATUS_BASE_IDX 0 354 #define regDAGB0_SDP_REQ_CNTL 0x00a2 355 #define regDAGB0_SDP_REQ_CNTL_BASE_IDX 0 356 #define regDAGB0_SDP_MISC 0x00a4 357 #define regDAGB0_SDP_MISC_BASE_IDX 0 358 #define regDAGB0_SDP_MISC2 0x00a5 359 #define regDAGB0_SDP_MISC2_BASE_IDX 0 360 #define regDAGB0_SDP_VCD_RESERVE0 0x00a7 361 #define regDAGB0_SDP_VCD_RESERVE0_BASE_IDX 0 362 #define regDAGB0_SDP_VCD_RESERVE1 0x00a8 363 #define regDAGB0_SDP_VCD_RESERVE1_BASE_IDX 0 364 #define regDAGB0_SDP_ARB_CNTL0 0x00a9 365 #define regDAGB0_SDP_ARB_CNTL0_BASE_IDX 0 366 #define regDAGB0_SDP_ARB_CNTL1 0x00aa 367 #define regDAGB0_SDP_ARB_CNTL1_BASE_IDX 0 368 #define regDAGB0_FATAL_ERROR_CNTL 0x00ab 369 #define regDAGB0_FATAL_ERROR_CNTL_BASE_IDX 0 370 #define regDAGB0_FATAL_ERROR_CLEAR 0x00ac 371 #define regDAGB0_FATAL_ERROR_CLEAR_BASE_IDX 0 372 #define regDAGB0_FATAL_ERROR_STATUS0 0x00ad 373 #define regDAGB0_FATAL_ERROR_STATUS0_BASE_IDX 0 374 #define regDAGB0_FATAL_ERROR_STATUS1 0x00ae 375 #define regDAGB0_FATAL_ERROR_STATUS1_BASE_IDX 0 376 #define regDAGB0_FATAL_ERROR_STATUS2 0x00af 377 #define regDAGB0_FATAL_ERROR_STATUS2_BASE_IDX 0 378 #define regDAGB0_FATAL_ERROR_STATUS3 0x00b0 379 #define regDAGB0_FATAL_ERROR_STATUS3_BASE_IDX 0 380 #define regDAGB0_FATAL_ERROR_STATUS4 0x00b1 381 #define regDAGB0_FATAL_ERROR_STATUS4_BASE_IDX 0 382 #define regDAGB0_SDP_CGTT_CLK_CTRL 0x00b6 383 #define regDAGB0_SDP_CGTT_CLK_CTRL_BASE_IDX 0 384 #define regDAGB0_SDP_LATENCY_SAMPLING 0x00b7 385 #define regDAGB0_SDP_LATENCY_SAMPLING_BASE_IDX 0 386 #define regDAGB1_RDCLI0 0x00b8 387 #define regDAGB1_RDCLI0_BASE_IDX 0 388 #define regDAGB1_RDCLI1 0x00b9 389 #define regDAGB1_RDCLI1_BASE_IDX 0 390 #define regDAGB1_RDCLI2 0x00ba 391 #define regDAGB1_RDCLI2_BASE_IDX 0 392 #define regDAGB1_RDCLI3 0x00bb 393 #define regDAGB1_RDCLI3_BASE_IDX 0 394 #define regDAGB1_RDCLI4 0x00bc 395 #define regDAGB1_RDCLI4_BASE_IDX 0 396 #define regDAGB1_RDCLI5 0x00bd 397 #define regDAGB1_RDCLI5_BASE_IDX 0 398 #define regDAGB1_RDCLI6 0x00be 399 #define regDAGB1_RDCLI6_BASE_IDX 0 400 #define regDAGB1_RDCLI7 0x00bf 401 #define regDAGB1_RDCLI7_BASE_IDX 0 402 #define regDAGB1_RDCLI8 0x00c0 403 #define regDAGB1_RDCLI8_BASE_IDX 0 404 #define regDAGB1_RDCLI9 0x00c1 405 #define regDAGB1_RDCLI9_BASE_IDX 0 406 #define regDAGB1_RDCLI10 0x00c2 407 #define regDAGB1_RDCLI10_BASE_IDX 0 408 #define regDAGB1_RDCLI11 0x00c3 409 #define regDAGB1_RDCLI11_BASE_IDX 0 410 #define regDAGB1_RDCLI12 0x00c4 411 #define regDAGB1_RDCLI12_BASE_IDX 0 412 #define regDAGB1_RDCLI13 0x00c5 413 #define regDAGB1_RDCLI13_BASE_IDX 0 414 #define regDAGB1_RDCLI14 0x00c6 415 #define regDAGB1_RDCLI14_BASE_IDX 0 416 #define regDAGB1_RDCLI15 0x00c7 417 #define regDAGB1_RDCLI15_BASE_IDX 0 418 #define regDAGB1_RDCLI16 0x00c8 419 #define regDAGB1_RDCLI16_BASE_IDX 0 420 #define regDAGB1_RDCLI17 0x00c9 421 #define regDAGB1_RDCLI17_BASE_IDX 0 422 #define regDAGB1_RDCLI18 0x00ca 423 #define regDAGB1_RDCLI18_BASE_IDX 0 424 #define regDAGB1_RDCLI19 0x00cb 425 #define regDAGB1_RDCLI19_BASE_IDX 0 426 #define regDAGB1_RDCLI20 0x00cc 427 #define regDAGB1_RDCLI20_BASE_IDX 0 428 #define regDAGB1_RDCLI21 0x00cd 429 #define regDAGB1_RDCLI21_BASE_IDX 0 430 #define regDAGB1_RDCLI22 0x00ce 431 #define regDAGB1_RDCLI22_BASE_IDX 0 432 #define regDAGB1_RDCLI23 0x00cf 433 #define regDAGB1_RDCLI23_BASE_IDX 0 434 #define regDAGB1_RD_CNTL 0x00d0 435 #define regDAGB1_RD_CNTL_BASE_IDX 0 436 #define regDAGB1_RD_IO_CNTL 0x00d1 437 #define regDAGB1_RD_IO_CNTL_BASE_IDX 0 438 #define regDAGB1_RD_GMI_CNTL 0x00d2 439 #define regDAGB1_RD_GMI_CNTL_BASE_IDX 0 440 #define regDAGB1_RD_ADDR_DAGB 0x00d3 441 #define regDAGB1_RD_ADDR_DAGB_BASE_IDX 0 442 #define regDAGB1_RD_CGTT_CLK_CTRL 0x00d4 443 #define regDAGB1_RD_CGTT_CLK_CTRL_BASE_IDX 0 444 #define regDAGB1_L1TLB_RD_CGTT_CLK_CTRL 0x00d5 445 #define regDAGB1_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX 0 446 #define regDAGB1_RD_ADDR_DAGB_MAX_BURST0 0x00d6 447 #define regDAGB1_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX 0 448 #define regDAGB1_RD_ADDR_DAGB_LAZY_TIMER0 0x00d7 449 #define regDAGB1_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0 450 #define regDAGB1_RD_ADDR_DAGB_MAX_BURST1 0x00d8 451 #define regDAGB1_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX 0 452 #define regDAGB1_RD_ADDR_DAGB_LAZY_TIMER1 0x00d9 453 #define regDAGB1_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0 454 #define regDAGB1_RD_ADDR_DAGB_MAX_BURST2 0x00da 455 #define regDAGB1_RD_ADDR_DAGB_MAX_BURST2_BASE_IDX 0 456 #define regDAGB1_RD_ADDR_DAGB_LAZY_TIMER2 0x00db 457 #define regDAGB1_RD_ADDR_DAGB_LAZY_TIMER2_BASE_IDX 0 458 #define regDAGB1_RD_VC0_CNTL 0x00dc 459 #define regDAGB1_RD_VC0_CNTL_BASE_IDX 0 460 #define regDAGB1_RD_VC1_CNTL 0x00dd 461 #define regDAGB1_RD_VC1_CNTL_BASE_IDX 0 462 #define regDAGB1_RD_VC2_CNTL 0x00de 463 #define regDAGB1_RD_VC2_CNTL_BASE_IDX 0 464 #define regDAGB1_RD_VC3_CNTL 0x00df 465 #define regDAGB1_RD_VC3_CNTL_BASE_IDX 0 466 #define regDAGB1_RD_VC4_CNTL 0x00e0 467 #define regDAGB1_RD_VC4_CNTL_BASE_IDX 0 468 #define regDAGB1_RD_VC5_CNTL 0x00e1 469 #define regDAGB1_RD_VC5_CNTL_BASE_IDX 0 470 #define regDAGB1_RD_IO_VC_CNTL 0x00e2 471 #define regDAGB1_RD_IO_VC_CNTL_BASE_IDX 0 472 #define regDAGB1_RD_GMI_VC_CNTL 0x00e3 473 #define regDAGB1_RD_GMI_VC_CNTL_BASE_IDX 0 474 #define regDAGB1_RD_CNTL_MISC 0x00e4 475 #define regDAGB1_RD_CNTL_MISC_BASE_IDX 0 476 #define regDAGB1_RD_TLB_CREDIT 0x00e5 477 #define regDAGB1_RD_TLB_CREDIT_BASE_IDX 0 478 #define regDAGB1_RD_RDRET_CREDIT_CNTL 0x00e6 479 #define regDAGB1_RD_RDRET_CREDIT_CNTL_BASE_IDX 0 480 #define regDAGB1_RD_RDRET_CREDIT_CNTL2 0x00e7 481 #define regDAGB1_RD_RDRET_CREDIT_CNTL2_BASE_IDX 0 482 #define regDAGB1_RDCLI_ASK_PENDING 0x00e8 483 #define regDAGB1_RDCLI_ASK_PENDING_BASE_IDX 0 484 #define regDAGB1_RDCLI_GO_PENDING 0x00e9 485 #define regDAGB1_RDCLI_GO_PENDING_BASE_IDX 0 486 #define regDAGB1_RDCLI_GBLSEND_PENDING 0x00ea 487 #define regDAGB1_RDCLI_GBLSEND_PENDING_BASE_IDX 0 488 #define regDAGB1_RDCLI_TLB_PENDING 0x00eb 489 #define regDAGB1_RDCLI_TLB_PENDING_BASE_IDX 0 490 #define regDAGB1_RDCLI_OARB_PENDING 0x00ec 491 #define regDAGB1_RDCLI_OARB_PENDING_BASE_IDX 0 492 #define regDAGB1_RDCLI_ASK2ARB_PENDING 0x00ed 493 #define regDAGB1_RDCLI_ASK2ARB_PENDING_BASE_IDX 0 494 #define regDAGB1_RDCLI_ASK2DF_PENDING 0x00ee 495 #define regDAGB1_RDCLI_ASK2DF_PENDING_BASE_IDX 0 496 #define regDAGB1_RDCLI_OSD_PENDING 0x00ef 497 #define regDAGB1_RDCLI_OSD_PENDING_BASE_IDX 0 498 #define regDAGB1_RDCLI_ASK_OSD_PENDING 0x00f0 499 #define regDAGB1_RDCLI_ASK_OSD_PENDING_BASE_IDX 0 500 #define regDAGB1_RDCLI_NOALLOC_OVERRIDE 0x00f1 501 #define regDAGB1_RDCLI_NOALLOC_OVERRIDE_BASE_IDX 0 502 #define regDAGB1_RDCLI_NOALLOC_OVERRIDE_VALUE 0x00f2 503 #define regDAGB1_RDCLI_NOALLOC_OVERRIDE_VALUE_BASE_IDX 0 504 #define regDAGB1_DAGB_DLY 0x00f3 505 #define regDAGB1_DAGB_DLY_BASE_IDX 0 506 #define regDAGB1_CNTL_MISC 0x00f4 507 #define regDAGB1_CNTL_MISC_BASE_IDX 0 508 #define regDAGB1_CNTL_MISC2 0x00f5 509 #define regDAGB1_CNTL_MISC2_BASE_IDX 0 510 #define regDAGB1_FIFO_EMPTY 0x00f6 511 #define regDAGB1_FIFO_EMPTY_BASE_IDX 0 512 #define regDAGB1_FIFO_FULL 0x00f7 513 #define regDAGB1_FIFO_FULL_BASE_IDX 0 514 #define regDAGB1_RD_CREDITS_FULL 0x00f8 515 #define regDAGB1_RD_CREDITS_FULL_BASE_IDX 0 516 #define regDAGB1_PERFCOUNTER_LO 0x00f9 517 #define regDAGB1_PERFCOUNTER_LO_BASE_IDX 0 518 #define regDAGB1_PERFCOUNTER_HI 0x00fa 519 #define regDAGB1_PERFCOUNTER_HI_BASE_IDX 0 520 #define regDAGB1_PERFCOUNTER0_CFG 0x00fb 521 #define regDAGB1_PERFCOUNTER0_CFG_BASE_IDX 0 522 #define regDAGB1_PERFCOUNTER1_CFG 0x00fc 523 #define regDAGB1_PERFCOUNTER1_CFG_BASE_IDX 0 524 #define regDAGB1_PERFCOUNTER2_CFG 0x00fd 525 #define regDAGB1_PERFCOUNTER2_CFG_BASE_IDX 0 526 #define regDAGB1_PERFCOUNTER_RSLT_CNTL 0x00fe 527 #define regDAGB1_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 528 #define regDAGB1_L1TLB_REG_RW 0x00ff 529 #define regDAGB1_L1TLB_REG_RW_BASE_IDX 0 530 #define regDAGB1_RESERVE1 0x0100 531 #define regDAGB1_RESERVE1_BASE_IDX 0 532 #define regDAGB1_RESERVE2 0x0101 533 #define regDAGB1_RESERVE2_BASE_IDX 0 534 #define regDAGB1_RESERVE3 0x0102 535 #define regDAGB1_RESERVE3_BASE_IDX 0 536 #define regDAGB1_RESERVE4 0x0103 537 #define regDAGB1_RESERVE4_BASE_IDX 0 538 #define regDAGB1_SDP_RD_BW_CNTL 0x0104 539 #define regDAGB1_SDP_RD_BW_CNTL_BASE_IDX 0 540 #define regDAGB1_SDP_PRIORITY_OVERRIDE 0x0105 541 #define regDAGB1_SDP_PRIORITY_OVERRIDE_BASE_IDX 0 542 #define regDAGB1_SDP_RD_PRIORITY 0x0106 543 #define regDAGB1_SDP_RD_PRIORITY_BASE_IDX 0 544 #define regDAGB1_SDP_RD_CLI2SDP_VC_MAP 0x0107 545 #define regDAGB1_SDP_RD_CLI2SDP_VC_MAP_BASE_IDX 0 546 #define regDAGB1_SDP_ENABLE 0x0108 547 #define regDAGB1_SDP_ENABLE_BASE_IDX 0 548 #define regDAGB1_SDP_CREDITS 0x0109 549 #define regDAGB1_SDP_CREDITS_BASE_IDX 0 550 #define regDAGB1_SDP_TAG_RESERVE0 0x010a 551 #define regDAGB1_SDP_TAG_RESERVE0_BASE_IDX 0 552 #define regDAGB1_SDP_TAG_RESERVE1 0x010b 553 #define regDAGB1_SDP_TAG_RESERVE1_BASE_IDX 0 554 #define regDAGB1_SDP_VCC_RESERVE0 0x010c 555 #define regDAGB1_SDP_VCC_RESERVE0_BASE_IDX 0 556 #define regDAGB1_SDP_VCC_RESERVE1 0x010d 557 #define regDAGB1_SDP_VCC_RESERVE1_BASE_IDX 0 558 #define regDAGB1_SDP_ERR_STATUS 0x010e 559 #define regDAGB1_SDP_ERR_STATUS_BASE_IDX 0 560 #define regDAGB1_SDP_REQ_CNTL 0x010f 561 #define regDAGB1_SDP_REQ_CNTL_BASE_IDX 0 562 #define regDAGB1_SDP_MISC 0x0111 563 #define regDAGB1_SDP_MISC_BASE_IDX 0 564 #define regDAGB1_SDP_MISC2 0x0112 565 #define regDAGB1_SDP_MISC2_BASE_IDX 0 566 #define regDAGB1_SDP_ARB_CNTL0 0x0114 567 #define regDAGB1_SDP_ARB_CNTL0_BASE_IDX 0 568 #define regDAGB1_SDP_ARB_CNTL1 0x0115 569 #define regDAGB1_SDP_ARB_CNTL1_BASE_IDX 0 570 #define regDAGB1_SDP_CGTT_CLK_CTRL 0x0116 571 #define regDAGB1_SDP_CGTT_CLK_CTRL_BASE_IDX 0 572 #define regDAGB1_SDP_LATENCY_SAMPLING 0x0117 573 #define regDAGB1_SDP_LATENCY_SAMPLING_BASE_IDX 0 574 575 576 // addressBlock: mmhub_pctldec 577 // base address: 0x68e00 578 #define regPCTL_CTRL 0x0380 579 #define regPCTL_CTRL_BASE_IDX 0 580 #define regPCTL_MMHUB_DEEPSLEEP_IB 0x0381 581 #define regPCTL_MMHUB_DEEPSLEEP_IB_BASE_IDX 0 582 #define regPCTL_MMHUB_DEEPSLEEP_OVERRIDE 0x0382 583 #define regPCTL_MMHUB_DEEPSLEEP_OVERRIDE_BASE_IDX 0 584 #define regPCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB 0x0383 585 #define regPCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB_BASE_IDX 0 586 #define regPCTL_PG_IGNORE_DEEPSLEEP 0x0384 587 #define regPCTL_PG_IGNORE_DEEPSLEEP_BASE_IDX 0 588 #define regPCTL_PG_IGNORE_DEEPSLEEP_IB 0x0385 589 #define regPCTL_PG_IGNORE_DEEPSLEEP_IB_BASE_IDX 0 590 #define regPCTL_SLICE0_CFG_DAGB_WRBUSY 0x0386 591 #define regPCTL_SLICE0_CFG_DAGB_WRBUSY_BASE_IDX 0 592 #define regPCTL_SLICE0_CFG_DAGB_RDBUSY 0x0387 593 #define regPCTL_SLICE0_CFG_DAGB_RDBUSY_BASE_IDX 0 594 #define regPCTL_SLICE0_CFG_DS_ALLOW 0x0388 595 #define regPCTL_SLICE0_CFG_DS_ALLOW_BASE_IDX 0 596 #define regPCTL_SLICE0_CFG_DS_ALLOW_IB 0x0389 597 #define regPCTL_SLICE0_CFG_DS_ALLOW_IB_BASE_IDX 0 598 #define regPCTL_SLICE1_CFG_DAGB_WRBUSY 0x038a 599 #define regPCTL_SLICE1_CFG_DAGB_WRBUSY_BASE_IDX 0 600 #define regPCTL_SLICE1_CFG_DAGB_RDBUSY 0x038b 601 #define regPCTL_SLICE1_CFG_DAGB_RDBUSY_BASE_IDX 0 602 #define regPCTL_SLICE1_CFG_DS_ALLOW 0x038c 603 #define regPCTL_SLICE1_CFG_DS_ALLOW_BASE_IDX 0 604 #define regPCTL_SLICE1_CFG_DS_ALLOW_IB 0x038d 605 #define regPCTL_SLICE1_CFG_DS_ALLOW_IB_BASE_IDX 0 606 #define regPCTL_UTCL2_MISC 0x038e 607 #define regPCTL_UTCL2_MISC_BASE_IDX 0 608 #define regPCTL_SLICE0_MISC 0x038f 609 #define regPCTL_SLICE0_MISC_BASE_IDX 0 610 #define regPCTL_SLICE1_MISC 0x0390 611 #define regPCTL_SLICE1_MISC_BASE_IDX 0 612 #define regPCTL_RENG_CTRL 0x0391 613 #define regPCTL_RENG_CTRL_BASE_IDX 0 614 #define regPCTL_UTCL2_RENG_EXECUTE 0x0392 615 #define regPCTL_UTCL2_RENG_EXECUTE_BASE_IDX 0 616 #define regPCTL_SLICE0_RENG_EXECUTE 0x0393 617 #define regPCTL_SLICE0_RENG_EXECUTE_BASE_IDX 0 618 #define regPCTL_SLICE1_RENG_EXECUTE 0x0394 619 #define regPCTL_SLICE1_RENG_EXECUTE_BASE_IDX 0 620 #define regPCTL_UTCL2_RENG_RAM_INDEX 0x0395 621 #define regPCTL_UTCL2_RENG_RAM_INDEX_BASE_IDX 0 622 #define regPCTL_UTCL2_RENG_RAM_DATA 0x0396 623 #define regPCTL_UTCL2_RENG_RAM_DATA_BASE_IDX 0 624 #define regPCTL_SLICE0_RENG_RAM_INDEX 0x0397 625 #define regPCTL_SLICE0_RENG_RAM_INDEX_BASE_IDX 0 626 #define regPCTL_SLICE0_RENG_RAM_DATA 0x0398 627 #define regPCTL_SLICE0_RENG_RAM_DATA_BASE_IDX 0 628 #define regPCTL_SLICE1_RENG_RAM_INDEX 0x0399 629 #define regPCTL_SLICE1_RENG_RAM_INDEX_BASE_IDX 0 630 #define regPCTL_SLICE1_RENG_RAM_DATA 0x039a 631 #define regPCTL_SLICE1_RENG_RAM_DATA_BASE_IDX 0 632 #define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0 0x039b 633 #define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 0 634 #define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1 0x039c 635 #define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 0 636 #define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2 0x039d 637 #define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 0 638 #define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3 0x039e 639 #define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX 0 640 #define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4 0x039f 641 #define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX 0 642 #define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0 0x03a0 643 #define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX 0 644 #define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1 0x03a1 645 #define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 0 646 #define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0 0x03a2 647 #define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 0 648 #define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1 0x03a3 649 #define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 0 650 #define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2 0x03a4 651 #define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 0 652 #define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3 0x03a5 653 #define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX 0 654 #define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4 0x03a6 655 #define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX 0 656 #define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0 0x03a7 657 #define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX 0 658 #define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1 0x03a8 659 #define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 0 660 #define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0 0x03a9 661 #define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 0 662 #define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1 0x03aa 663 #define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 0 664 #define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2 0x03ab 665 #define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 0 666 #define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3 0x03ac 667 #define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX 0 668 #define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4 0x03ad 669 #define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX 0 670 #define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0 0x03ae 671 #define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX 0 672 #define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1 0x03af 673 #define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 0 674 #define regPCTL_STATUS 0x03b0 675 #define regPCTL_STATUS_BASE_IDX 0 676 #define regPCTL_PERFCOUNTER_LO 0x03b1 677 #define regPCTL_PERFCOUNTER_LO_BASE_IDX 0 678 #define regPCTL_PERFCOUNTER_HI 0x03b2 679 #define regPCTL_PERFCOUNTER_HI_BASE_IDX 0 680 #define regPCTL_PERFCOUNTER0_CFG 0x03b3 681 #define regPCTL_PERFCOUNTER0_CFG_BASE_IDX 0 682 #define regPCTL_PERFCOUNTER1_CFG 0x03b4 683 #define regPCTL_PERFCOUNTER1_CFG_BASE_IDX 0 684 #define regPCTL_PERFCOUNTER_RSLT_CNTL 0x03b5 685 #define regPCTL_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 686 #define regPCTL_RESERVED_0 0x03b6 687 #define regPCTL_RESERVED_0_BASE_IDX 0 688 #define regPCTL_RESERVED_1 0x03b7 689 #define regPCTL_RESERVED_1_BASE_IDX 0 690 #define regPCTL_RESERVED_2 0x03b8 691 #define regPCTL_RESERVED_2_BASE_IDX 0 692 #define regPCTL_RESERVED_3 0x03b9 693 #define regPCTL_RESERVED_3_BASE_IDX 0 694 695 696 // addressBlock: mmhub_l1tlb_mmutcl1pfdec 697 // base address: 0x69600 698 #define regMMMC_VM_MX_L1_TLB0_STATUS 0x0586 699 #define regMMMC_VM_MX_L1_TLB0_STATUS_BASE_IDX 0 700 #define regMMMC_VM_MX_L1_TLB1_STATUS 0x0587 701 #define regMMMC_VM_MX_L1_TLB1_STATUS_BASE_IDX 0 702 #define regMMMC_VM_MX_L1_TLB2_STATUS 0x0588 703 #define regMMMC_VM_MX_L1_TLB2_STATUS_BASE_IDX 0 704 #define regMMMC_VM_MX_L1_TLB3_STATUS 0x0589 705 #define regMMMC_VM_MX_L1_TLB3_STATUS_BASE_IDX 0 706 #define regMMMC_VM_MX_L1_TLB4_STATUS 0x058a 707 #define regMMMC_VM_MX_L1_TLB4_STATUS_BASE_IDX 0 708 #define regMMMC_VM_MX_L1_TLB5_STATUS 0x058b 709 #define regMMMC_VM_MX_L1_TLB5_STATUS_BASE_IDX 0 710 711 712 // addressBlock: mmhub_l1tlb_mmutcl1pldec 713 // base address: 0x69670 714 #define regMMMC_VM_MX_L1_PERFCOUNTER0_CFG 0x059c 715 #define regMMMC_VM_MX_L1_PERFCOUNTER0_CFG_BASE_IDX 0 716 #define regMMMC_VM_MX_L1_PERFCOUNTER1_CFG 0x059d 717 #define regMMMC_VM_MX_L1_PERFCOUNTER1_CFG_BASE_IDX 0 718 #define regMMMC_VM_MX_L1_PERFCOUNTER2_CFG 0x059e 719 #define regMMMC_VM_MX_L1_PERFCOUNTER2_CFG_BASE_IDX 0 720 #define regMMMC_VM_MX_L1_PERFCOUNTER3_CFG 0x059f 721 #define regMMMC_VM_MX_L1_PERFCOUNTER3_CFG_BASE_IDX 0 722 #define regMMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL 0x05a0 723 #define regMMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 724 725 726 // addressBlock: mmhub_l1tlb_mmutcl1prdec 727 // base address: 0x69690 728 #define regMMMC_VM_MX_L1_PERFCOUNTER_LO 0x05a4 729 #define regMMMC_VM_MX_L1_PERFCOUNTER_LO_BASE_IDX 0 730 #define regMMMC_VM_MX_L1_PERFCOUNTER_HI 0x05a5 731 #define regMMMC_VM_MX_L1_PERFCOUNTER_HI_BASE_IDX 0 732 733 734 // addressBlock: mmhub_mmutcl2_mmatcl2dec 735 // base address: 0x69b00 736 #define regMM_ATC_L2_CNTL 0x06c0 737 #define regMM_ATC_L2_CNTL_BASE_IDX 0 738 #define regMM_ATC_L2_CNTL2 0x06c1 739 #define regMM_ATC_L2_CNTL2_BASE_IDX 0 740 #define regMM_ATC_L2_CACHE_DATA0 0x06c4 741 #define regMM_ATC_L2_CACHE_DATA0_BASE_IDX 0 742 #define regMM_ATC_L2_CACHE_DATA1 0x06c5 743 #define regMM_ATC_L2_CACHE_DATA1_BASE_IDX 0 744 #define regMM_ATC_L2_CACHE_DATA2 0x06c6 745 #define regMM_ATC_L2_CACHE_DATA2_BASE_IDX 0 746 #define regMM_ATC_L2_CNTL3 0x06c7 747 #define regMM_ATC_L2_CNTL3_BASE_IDX 0 748 #define regMM_ATC_L2_CNTL4 0x06c8 749 #define regMM_ATC_L2_CNTL4_BASE_IDX 0 750 #define regMM_ATC_L2_CNTL5 0x06c9 751 #define regMM_ATC_L2_CNTL5_BASE_IDX 0 752 #define regMM_ATC_L2_MM_GROUP_RT_CLASSES 0x06ca 753 #define regMM_ATC_L2_MM_GROUP_RT_CLASSES_BASE_IDX 0 754 #define regMM_ATC_L2_STATUS 0x06cb 755 #define regMM_ATC_L2_STATUS_BASE_IDX 0 756 #define regMM_ATC_L2_STATUS2 0x06cc 757 #define regMM_ATC_L2_STATUS2_BASE_IDX 0 758 #define regMM_ATC_L2_MISC_CG 0x06cd 759 #define regMM_ATC_L2_MISC_CG_BASE_IDX 0 760 #define regMM_ATC_L2_MEM_POWER_LS 0x06ce 761 #define regMM_ATC_L2_MEM_POWER_LS_BASE_IDX 0 762 #define regMM_ATC_L2_CGTT_CLK_CTRL 0x06cf 763 #define regMM_ATC_L2_CGTT_CLK_CTRL_BASE_IDX 0 764 #define regMM_ATC_L2_SDPPORT_CTRL 0x06d2 765 #define regMM_ATC_L2_SDPPORT_CTRL_BASE_IDX 0 766 #define regMMUTCL2_FFBM_CONFIG 0x06d4 767 #define regMMUTCL2_FFBM_CONFIG_BASE_IDX 0 768 #define regMMUTCL2_FFBM_ACCESS_CNTL 0x06d5 769 #define regMMUTCL2_FFBM_ACCESS_CNTL_BASE_IDX 0 770 #define regMMUTCL2_FFBM_ADDRESS 0x06d6 771 #define regMMUTCL2_FFBM_ADDRESS_BASE_IDX 0 772 #define regMMUTCL2_FFBM_DATA 0x06d7 773 #define regMMUTCL2_FFBM_DATA_BASE_IDX 0 774 #define regMMUTCL2_FFBM_INVALIDATE_REQUEST 0x06d8 775 #define regMMUTCL2_FFBM_INVALIDATE_REQUEST_BASE_IDX 0 776 #define regMMUTCL2_FFBM_INVALIDATE_RESPONSE 0x06d9 777 #define regMMUTCL2_FFBM_INVALIDATE_RESPONSE_BASE_IDX 0 778 779 780 // addressBlock: mmhub_mmutcl2_mmvml2pfdec 781 // base address: 0x69c00 782 #define regMMVM_L2_CNTL 0x0700 783 #define regMMVM_L2_CNTL_BASE_IDX 0 784 #define regMMVM_L2_CNTL2 0x0701 785 #define regMMVM_L2_CNTL2_BASE_IDX 0 786 #define regMMVM_L2_CNTL3 0x0702 787 #define regMMVM_L2_CNTL3_BASE_IDX 0 788 #define regMMVM_L2_STATUS 0x0703 789 #define regMMVM_L2_STATUS_BASE_IDX 0 790 #define regMMVM_DUMMY_PAGE_FAULT_CNTL 0x0704 791 #define regMMVM_DUMMY_PAGE_FAULT_CNTL_BASE_IDX 0 792 #define regMMVM_DUMMY_PAGE_FAULT_ADDR_LO32 0x0705 793 #define regMMVM_DUMMY_PAGE_FAULT_ADDR_LO32_BASE_IDX 0 794 #define regMMVM_DUMMY_PAGE_FAULT_ADDR_HI32 0x0706 795 #define regMMVM_DUMMY_PAGE_FAULT_ADDR_HI32_BASE_IDX 0 796 #define regMMVM_INVALIDATE_CNTL 0x0707 797 #define regMMVM_INVALIDATE_CNTL_BASE_IDX 0 798 #define regMMVM_L2_PROTECTION_FAULT_CNTL 0x0708 799 #define regMMVM_L2_PROTECTION_FAULT_CNTL_BASE_IDX 0 800 #define regMMVM_L2_PROTECTION_FAULT_CNTL2 0x0709 801 #define regMMVM_L2_PROTECTION_FAULT_CNTL2_BASE_IDX 0 802 #define regMMVM_L2_PROTECTION_FAULT_MM_CNTL3 0x070a 803 #define regMMVM_L2_PROTECTION_FAULT_MM_CNTL3_BASE_IDX 0 804 #define regMMVM_L2_PROTECTION_FAULT_MM_CNTL4 0x070b 805 #define regMMVM_L2_PROTECTION_FAULT_MM_CNTL4_BASE_IDX 0 806 #define regMMVM_L2_PROTECTION_FAULT_STATUS 0x070c 807 #define regMMVM_L2_PROTECTION_FAULT_STATUS_BASE_IDX 0 808 #define regMMVM_L2_PROTECTION_FAULT_ADDR_LO32 0x070d 809 #define regMMVM_L2_PROTECTION_FAULT_ADDR_LO32_BASE_IDX 0 810 #define regMMVM_L2_PROTECTION_FAULT_ADDR_HI32 0x070e 811 #define regMMVM_L2_PROTECTION_FAULT_ADDR_HI32_BASE_IDX 0 812 #define regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 0x070f 813 #define regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_BASE_IDX 0 814 #define regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 0x0710 815 #define regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_BASE_IDX 0 816 #define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 0x0712 817 #define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_BASE_IDX 0 818 #define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 0x0713 819 #define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_BASE_IDX 0 820 #define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 0x0714 821 #define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_BASE_IDX 0 822 #define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 0x0715 823 #define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_BASE_IDX 0 824 #define regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 0x0716 825 #define regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_BASE_IDX 0 826 #define regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 0x0717 827 #define regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_BASE_IDX 0 828 #define regMMVM_L2_CNTL4 0x0718 829 #define regMMVM_L2_CNTL4_BASE_IDX 0 830 #define regMMVM_L2_MM_GROUP_RT_CLASSES 0x0719 831 #define regMMVM_L2_MM_GROUP_RT_CLASSES_BASE_IDX 0 832 #define regMMVM_L2_BANK_SELECT_RESERVED_CID 0x071a 833 #define regMMVM_L2_BANK_SELECT_RESERVED_CID_BASE_IDX 0 834 #define regMMVM_L2_BANK_SELECT_RESERVED_CID2 0x071b 835 #define regMMVM_L2_BANK_SELECT_RESERVED_CID2_BASE_IDX 0 836 #define regMMVM_L2_CACHE_PARITY_CNTL 0x071c 837 #define regMMVM_L2_CACHE_PARITY_CNTL_BASE_IDX 0 838 #define regMMVM_L2_CGTT_CLK_CTRL 0x071d 839 #define regMMVM_L2_CGTT_CLK_CTRL_BASE_IDX 0 840 #define regMMVM_L2_CNTL5 0x071e 841 #define regMMVM_L2_CNTL5_BASE_IDX 0 842 #define regMMVM_L2_GCR_CNTL 0x071f 843 #define regMMVM_L2_GCR_CNTL_BASE_IDX 0 844 #define regMMVM_L2_CGTT_BUSY_CTRL 0x0720 845 #define regMMVM_L2_CGTT_BUSY_CTRL_BASE_IDX 0 846 #define regMMVM_L2_PTE_CACHE_DUMP_CNTL 0x0721 847 #define regMMVM_L2_PTE_CACHE_DUMP_CNTL_BASE_IDX 0 848 #define regMMVM_L2_PTE_CACHE_DUMP_READ 0x0722 849 #define regMMVM_L2_PTE_CACHE_DUMP_READ_BASE_IDX 0 850 #define regMMVM_L2_BANK_SELECT_MASKS 0x0725 851 #define regMMVM_L2_BANK_SELECT_MASKS_BASE_IDX 0 852 #define regMMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC 0x0726 853 #define regMMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC_BASE_IDX 0 854 #define regMMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC 0x0727 855 #define regMMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC_BASE_IDX 0 856 #define regMMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC 0x0728 857 #define regMMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC_BASE_IDX 0 858 #define regMMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT 0x0729 859 #define regMMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT_BASE_IDX 0 860 #define regMMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ 0x072a 861 #define regMMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ_BASE_IDX 0 862 863 864 // addressBlock: mmhub_mmutcl2_mmvml2vcdec 865 // base address: 0x69d00 866 #define regMMVM_CONTEXT0_CNTL 0x0740 867 #define regMMVM_CONTEXT0_CNTL_BASE_IDX 0 868 #define regMMVM_CONTEXT1_CNTL 0x0741 869 #define regMMVM_CONTEXT1_CNTL_BASE_IDX 0 870 #define regMMVM_CONTEXT2_CNTL 0x0742 871 #define regMMVM_CONTEXT2_CNTL_BASE_IDX 0 872 #define regMMVM_CONTEXT3_CNTL 0x0743 873 #define regMMVM_CONTEXT3_CNTL_BASE_IDX 0 874 #define regMMVM_CONTEXT4_CNTL 0x0744 875 #define regMMVM_CONTEXT4_CNTL_BASE_IDX 0 876 #define regMMVM_CONTEXT5_CNTL 0x0745 877 #define regMMVM_CONTEXT5_CNTL_BASE_IDX 0 878 #define regMMVM_CONTEXT6_CNTL 0x0746 879 #define regMMVM_CONTEXT6_CNTL_BASE_IDX 0 880 #define regMMVM_CONTEXT7_CNTL 0x0747 881 #define regMMVM_CONTEXT7_CNTL_BASE_IDX 0 882 #define regMMVM_CONTEXT8_CNTL 0x0748 883 #define regMMVM_CONTEXT8_CNTL_BASE_IDX 0 884 #define regMMVM_CONTEXT9_CNTL 0x0749 885 #define regMMVM_CONTEXT9_CNTL_BASE_IDX 0 886 #define regMMVM_CONTEXT10_CNTL 0x074a 887 #define regMMVM_CONTEXT10_CNTL_BASE_IDX 0 888 #define regMMVM_CONTEXT11_CNTL 0x074b 889 #define regMMVM_CONTEXT11_CNTL_BASE_IDX 0 890 #define regMMVM_CONTEXT12_CNTL 0x074c 891 #define regMMVM_CONTEXT12_CNTL_BASE_IDX 0 892 #define regMMVM_CONTEXT13_CNTL 0x074d 893 #define regMMVM_CONTEXT13_CNTL_BASE_IDX 0 894 #define regMMVM_CONTEXT14_CNTL 0x074e 895 #define regMMVM_CONTEXT14_CNTL_BASE_IDX 0 896 #define regMMVM_CONTEXT15_CNTL 0x074f 897 #define regMMVM_CONTEXT15_CNTL_BASE_IDX 0 898 #define regMMVM_CONTEXTS_DISABLE 0x0750 899 #define regMMVM_CONTEXTS_DISABLE_BASE_IDX 0 900 #define regMMVM_INVALIDATE_ENG0_SEM 0x0751 901 #define regMMVM_INVALIDATE_ENG0_SEM_BASE_IDX 0 902 #define regMMVM_INVALIDATE_ENG1_SEM 0x0752 903 #define regMMVM_INVALIDATE_ENG1_SEM_BASE_IDX 0 904 #define regMMVM_INVALIDATE_ENG2_SEM 0x0753 905 #define regMMVM_INVALIDATE_ENG2_SEM_BASE_IDX 0 906 #define regMMVM_INVALIDATE_ENG3_SEM 0x0754 907 #define regMMVM_INVALIDATE_ENG3_SEM_BASE_IDX 0 908 #define regMMVM_INVALIDATE_ENG4_SEM 0x0755 909 #define regMMVM_INVALIDATE_ENG4_SEM_BASE_IDX 0 910 #define regMMVM_INVALIDATE_ENG5_SEM 0x0756 911 #define regMMVM_INVALIDATE_ENG5_SEM_BASE_IDX 0 912 #define regMMVM_INVALIDATE_ENG6_SEM 0x0757 913 #define regMMVM_INVALIDATE_ENG6_SEM_BASE_IDX 0 914 #define regMMVM_INVALIDATE_ENG7_SEM 0x0758 915 #define regMMVM_INVALIDATE_ENG7_SEM_BASE_IDX 0 916 #define regMMVM_INVALIDATE_ENG8_SEM 0x0759 917 #define regMMVM_INVALIDATE_ENG8_SEM_BASE_IDX 0 918 #define regMMVM_INVALIDATE_ENG9_SEM 0x075a 919 #define regMMVM_INVALIDATE_ENG9_SEM_BASE_IDX 0 920 #define regMMVM_INVALIDATE_ENG10_SEM 0x075b 921 #define regMMVM_INVALIDATE_ENG10_SEM_BASE_IDX 0 922 #define regMMVM_INVALIDATE_ENG11_SEM 0x075c 923 #define regMMVM_INVALIDATE_ENG11_SEM_BASE_IDX 0 924 #define regMMVM_INVALIDATE_ENG12_SEM 0x075d 925 #define regMMVM_INVALIDATE_ENG12_SEM_BASE_IDX 0 926 #define regMMVM_INVALIDATE_ENG13_SEM 0x075e 927 #define regMMVM_INVALIDATE_ENG13_SEM_BASE_IDX 0 928 #define regMMVM_INVALIDATE_ENG14_SEM 0x075f 929 #define regMMVM_INVALIDATE_ENG14_SEM_BASE_IDX 0 930 #define regMMVM_INVALIDATE_ENG15_SEM 0x0760 931 #define regMMVM_INVALIDATE_ENG15_SEM_BASE_IDX 0 932 #define regMMVM_INVALIDATE_ENG16_SEM 0x0761 933 #define regMMVM_INVALIDATE_ENG16_SEM_BASE_IDX 0 934 #define regMMVM_INVALIDATE_ENG17_SEM 0x0762 935 #define regMMVM_INVALIDATE_ENG17_SEM_BASE_IDX 0 936 #define regMMVM_INVALIDATE_ENG0_REQ 0x0763 937 #define regMMVM_INVALIDATE_ENG0_REQ_BASE_IDX 0 938 #define regMMVM_INVALIDATE_ENG1_REQ 0x0764 939 #define regMMVM_INVALIDATE_ENG1_REQ_BASE_IDX 0 940 #define regMMVM_INVALIDATE_ENG2_REQ 0x0765 941 #define regMMVM_INVALIDATE_ENG2_REQ_BASE_IDX 0 942 #define regMMVM_INVALIDATE_ENG3_REQ 0x0766 943 #define regMMVM_INVALIDATE_ENG3_REQ_BASE_IDX 0 944 #define regMMVM_INVALIDATE_ENG4_REQ 0x0767 945 #define regMMVM_INVALIDATE_ENG4_REQ_BASE_IDX 0 946 #define regMMVM_INVALIDATE_ENG5_REQ 0x0768 947 #define regMMVM_INVALIDATE_ENG5_REQ_BASE_IDX 0 948 #define regMMVM_INVALIDATE_ENG6_REQ 0x0769 949 #define regMMVM_INVALIDATE_ENG6_REQ_BASE_IDX 0 950 #define regMMVM_INVALIDATE_ENG7_REQ 0x076a 951 #define regMMVM_INVALIDATE_ENG7_REQ_BASE_IDX 0 952 #define regMMVM_INVALIDATE_ENG8_REQ 0x076b 953 #define regMMVM_INVALIDATE_ENG8_REQ_BASE_IDX 0 954 #define regMMVM_INVALIDATE_ENG9_REQ 0x076c 955 #define regMMVM_INVALIDATE_ENG9_REQ_BASE_IDX 0 956 #define regMMVM_INVALIDATE_ENG10_REQ 0x076d 957 #define regMMVM_INVALIDATE_ENG10_REQ_BASE_IDX 0 958 #define regMMVM_INVALIDATE_ENG11_REQ 0x076e 959 #define regMMVM_INVALIDATE_ENG11_REQ_BASE_IDX 0 960 #define regMMVM_INVALIDATE_ENG12_REQ 0x076f 961 #define regMMVM_INVALIDATE_ENG12_REQ_BASE_IDX 0 962 #define regMMVM_INVALIDATE_ENG13_REQ 0x0770 963 #define regMMVM_INVALIDATE_ENG13_REQ_BASE_IDX 0 964 #define regMMVM_INVALIDATE_ENG14_REQ 0x0771 965 #define regMMVM_INVALIDATE_ENG14_REQ_BASE_IDX 0 966 #define regMMVM_INVALIDATE_ENG15_REQ 0x0772 967 #define regMMVM_INVALIDATE_ENG15_REQ_BASE_IDX 0 968 #define regMMVM_INVALIDATE_ENG16_REQ 0x0773 969 #define regMMVM_INVALIDATE_ENG16_REQ_BASE_IDX 0 970 #define regMMVM_INVALIDATE_ENG17_REQ 0x0774 971 #define regMMVM_INVALIDATE_ENG17_REQ_BASE_IDX 0 972 #define regMMVM_INVALIDATE_ENG0_ACK 0x0775 973 #define regMMVM_INVALIDATE_ENG0_ACK_BASE_IDX 0 974 #define regMMVM_INVALIDATE_ENG1_ACK 0x0776 975 #define regMMVM_INVALIDATE_ENG1_ACK_BASE_IDX 0 976 #define regMMVM_INVALIDATE_ENG2_ACK 0x0777 977 #define regMMVM_INVALIDATE_ENG2_ACK_BASE_IDX 0 978 #define regMMVM_INVALIDATE_ENG3_ACK 0x0778 979 #define regMMVM_INVALIDATE_ENG3_ACK_BASE_IDX 0 980 #define regMMVM_INVALIDATE_ENG4_ACK 0x0779 981 #define regMMVM_INVALIDATE_ENG4_ACK_BASE_IDX 0 982 #define regMMVM_INVALIDATE_ENG5_ACK 0x077a 983 #define regMMVM_INVALIDATE_ENG5_ACK_BASE_IDX 0 984 #define regMMVM_INVALIDATE_ENG6_ACK 0x077b 985 #define regMMVM_INVALIDATE_ENG6_ACK_BASE_IDX 0 986 #define regMMVM_INVALIDATE_ENG7_ACK 0x077c 987 #define regMMVM_INVALIDATE_ENG7_ACK_BASE_IDX 0 988 #define regMMVM_INVALIDATE_ENG8_ACK 0x077d 989 #define regMMVM_INVALIDATE_ENG8_ACK_BASE_IDX 0 990 #define regMMVM_INVALIDATE_ENG9_ACK 0x077e 991 #define regMMVM_INVALIDATE_ENG9_ACK_BASE_IDX 0 992 #define regMMVM_INVALIDATE_ENG10_ACK 0x077f 993 #define regMMVM_INVALIDATE_ENG10_ACK_BASE_IDX 0 994 #define regMMVM_INVALIDATE_ENG11_ACK 0x0780 995 #define regMMVM_INVALIDATE_ENG11_ACK_BASE_IDX 0 996 #define regMMVM_INVALIDATE_ENG12_ACK 0x0781 997 #define regMMVM_INVALIDATE_ENG12_ACK_BASE_IDX 0 998 #define regMMVM_INVALIDATE_ENG13_ACK 0x0782 999 #define regMMVM_INVALIDATE_ENG13_ACK_BASE_IDX 0 1000 #define regMMVM_INVALIDATE_ENG14_ACK 0x0783 1001 #define regMMVM_INVALIDATE_ENG14_ACK_BASE_IDX 0 1002 #define regMMVM_INVALIDATE_ENG15_ACK 0x0784 1003 #define regMMVM_INVALIDATE_ENG15_ACK_BASE_IDX 0 1004 #define regMMVM_INVALIDATE_ENG16_ACK 0x0785 1005 #define regMMVM_INVALIDATE_ENG16_ACK_BASE_IDX 0 1006 #define regMMVM_INVALIDATE_ENG17_ACK 0x0786 1007 #define regMMVM_INVALIDATE_ENG17_ACK_BASE_IDX 0 1008 #define regMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32 0x0787 1009 #define regMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32_BASE_IDX 0 1010 #define regMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32 0x0788 1011 #define regMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32_BASE_IDX 0 1012 #define regMMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 0x0789 1013 #define regMMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32_BASE_IDX 0 1014 #define regMMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32 0x078a 1015 #define regMMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32_BASE_IDX 0 1016 #define regMMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32 0x078b 1017 #define regMMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32_BASE_IDX 0 1018 #define regMMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32 0x078c 1019 #define regMMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32_BASE_IDX 0 1020 #define regMMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32 0x078d 1021 #define regMMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32_BASE_IDX 0 1022 #define regMMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32 0x078e 1023 #define regMMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32_BASE_IDX 0 1024 #define regMMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32 0x078f 1025 #define regMMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32_BASE_IDX 0 1026 #define regMMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32 0x0790 1027 #define regMMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32_BASE_IDX 0 1028 #define regMMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32 0x0791 1029 #define regMMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32_BASE_IDX 0 1030 #define regMMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32 0x0792 1031 #define regMMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32_BASE_IDX 0 1032 #define regMMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32 0x0793 1033 #define regMMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32_BASE_IDX 0 1034 #define regMMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32 0x0794 1035 #define regMMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32_BASE_IDX 0 1036 #define regMMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32 0x0795 1037 #define regMMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32_BASE_IDX 0 1038 #define regMMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32 0x0796 1039 #define regMMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32_BASE_IDX 0 1040 #define regMMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32 0x0797 1041 #define regMMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32_BASE_IDX 0 1042 #define regMMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32 0x0798 1043 #define regMMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32_BASE_IDX 0 1044 #define regMMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32 0x0799 1045 #define regMMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32_BASE_IDX 0 1046 #define regMMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32 0x079a 1047 #define regMMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32_BASE_IDX 0 1048 #define regMMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32 0x079b 1049 #define regMMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32_BASE_IDX 0 1050 #define regMMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32 0x079c 1051 #define regMMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32_BASE_IDX 0 1052 #define regMMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32 0x079d 1053 #define regMMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32_BASE_IDX 0 1054 #define regMMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32 0x079e 1055 #define regMMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32_BASE_IDX 0 1056 #define regMMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32 0x079f 1057 #define regMMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32_BASE_IDX 0 1058 #define regMMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32 0x07a0 1059 #define regMMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32_BASE_IDX 0 1060 #define regMMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32 0x07a1 1061 #define regMMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32_BASE_IDX 0 1062 #define regMMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32 0x07a2 1063 #define regMMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32_BASE_IDX 0 1064 #define regMMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32 0x07a3 1065 #define regMMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32_BASE_IDX 0 1066 #define regMMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32 0x07a4 1067 #define regMMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32_BASE_IDX 0 1068 #define regMMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32 0x07a5 1069 #define regMMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32_BASE_IDX 0 1070 #define regMMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32 0x07a6 1071 #define regMMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32_BASE_IDX 0 1072 #define regMMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32 0x07a7 1073 #define regMMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32_BASE_IDX 0 1074 #define regMMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32 0x07a8 1075 #define regMMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32_BASE_IDX 0 1076 #define regMMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32 0x07a9 1077 #define regMMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32_BASE_IDX 0 1078 #define regMMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32 0x07aa 1079 #define regMMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32_BASE_IDX 0 1080 #define regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0x07ab 1081 #define regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1082 #define regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0x07ac 1083 #define regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1084 #define regMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 0x07ad 1085 #define regMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1086 #define regMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 0x07ae 1087 #define regMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1088 #define regMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 0x07af 1089 #define regMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1090 #define regMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 0x07b0 1091 #define regMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1092 #define regMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 0x07b1 1093 #define regMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1094 #define regMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 0x07b2 1095 #define regMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1096 #define regMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 0x07b3 1097 #define regMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1098 #define regMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 0x07b4 1099 #define regMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1100 #define regMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 0x07b5 1101 #define regMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1102 #define regMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 0x07b6 1103 #define regMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1104 #define regMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 0x07b7 1105 #define regMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1106 #define regMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 0x07b8 1107 #define regMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1108 #define regMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 0x07b9 1109 #define regMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1110 #define regMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 0x07ba 1111 #define regMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1112 #define regMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 0x07bb 1113 #define regMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1114 #define regMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 0x07bc 1115 #define regMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1116 #define regMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 0x07bd 1117 #define regMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1118 #define regMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 0x07be 1119 #define regMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1120 #define regMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 0x07bf 1121 #define regMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1122 #define regMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 0x07c0 1123 #define regMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1124 #define regMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 0x07c1 1125 #define regMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1126 #define regMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 0x07c2 1127 #define regMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1128 #define regMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 0x07c3 1129 #define regMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1130 #define regMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 0x07c4 1131 #define regMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1132 #define regMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 0x07c5 1133 #define regMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1134 #define regMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 0x07c6 1135 #define regMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1136 #define regMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 0x07c7 1137 #define regMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1138 #define regMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 0x07c8 1139 #define regMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1140 #define regMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 0x07c9 1141 #define regMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1142 #define regMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 0x07ca 1143 #define regMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1144 #define regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0x07cb 1145 #define regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1146 #define regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0x07cc 1147 #define regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1148 #define regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 0x07cd 1149 #define regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1150 #define regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 0x07ce 1151 #define regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1152 #define regMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 0x07cf 1153 #define regMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1154 #define regMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 0x07d0 1155 #define regMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1156 #define regMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 0x07d1 1157 #define regMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1158 #define regMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 0x07d2 1159 #define regMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1160 #define regMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 0x07d3 1161 #define regMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1162 #define regMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 0x07d4 1163 #define regMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1164 #define regMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 0x07d5 1165 #define regMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1166 #define regMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 0x07d6 1167 #define regMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1168 #define regMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 0x07d7 1169 #define regMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1170 #define regMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 0x07d8 1171 #define regMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1172 #define regMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 0x07d9 1173 #define regMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1174 #define regMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 0x07da 1175 #define regMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1176 #define regMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 0x07db 1177 #define regMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1178 #define regMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 0x07dc 1179 #define regMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1180 #define regMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 0x07dd 1181 #define regMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1182 #define regMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 0x07de 1183 #define regMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1184 #define regMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 0x07df 1185 #define regMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1186 #define regMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 0x07e0 1187 #define regMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1188 #define regMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 0x07e1 1189 #define regMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1190 #define regMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 0x07e2 1191 #define regMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1192 #define regMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 0x07e3 1193 #define regMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1194 #define regMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 0x07e4 1195 #define regMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1196 #define regMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 0x07e5 1197 #define regMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1198 #define regMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 0x07e6 1199 #define regMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1200 #define regMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 0x07e7 1201 #define regMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1202 #define regMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 0x07e8 1203 #define regMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1204 #define regMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 0x07e9 1205 #define regMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1206 #define regMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 0x07ea 1207 #define regMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1208 #define regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0x07eb 1209 #define regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1210 #define regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0x07ec 1211 #define regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1212 #define regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 0x07ed 1213 #define regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1214 #define regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 0x07ee 1215 #define regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1216 #define regMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 0x07ef 1217 #define regMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1218 #define regMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 0x07f0 1219 #define regMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1220 #define regMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 0x07f1 1221 #define regMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1222 #define regMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 0x07f2 1223 #define regMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1224 #define regMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 0x07f3 1225 #define regMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1226 #define regMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 0x07f4 1227 #define regMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1228 #define regMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 0x07f5 1229 #define regMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1230 #define regMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 0x07f6 1231 #define regMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1232 #define regMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 0x07f7 1233 #define regMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1234 #define regMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 0x07f8 1235 #define regMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1236 #define regMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 0x07f9 1237 #define regMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1238 #define regMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 0x07fa 1239 #define regMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1240 #define regMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 0x07fb 1241 #define regMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1242 #define regMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 0x07fc 1243 #define regMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1244 #define regMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 0x07fd 1245 #define regMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1246 #define regMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 0x07fe 1247 #define regMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1248 #define regMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 0x07ff 1249 #define regMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1250 #define regMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 0x0800 1251 #define regMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1252 #define regMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 0x0801 1253 #define regMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1254 #define regMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 0x0802 1255 #define regMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1256 #define regMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 0x0803 1257 #define regMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1258 #define regMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 0x0804 1259 #define regMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1260 #define regMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 0x0805 1261 #define regMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1262 #define regMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 0x0806 1263 #define regMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1264 #define regMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 0x0807 1265 #define regMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1266 #define regMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 0x0808 1267 #define regMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1268 #define regMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 0x0809 1269 #define regMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1270 #define regMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 0x080a 1271 #define regMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1272 #define regMMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x080b 1273 #define regMMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 1274 #define regMMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x080c 1275 #define regMMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 1276 #define regMMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x080d 1277 #define regMMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 1278 #define regMMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x080e 1279 #define regMMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 1280 #define regMMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x080f 1281 #define regMMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 1282 #define regMMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0810 1283 #define regMMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 1284 #define regMMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0811 1285 #define regMMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 1286 #define regMMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0812 1287 #define regMMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 1288 #define regMMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0813 1289 #define regMMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 1290 #define regMMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0814 1291 #define regMMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 1292 #define regMMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0815 1293 #define regMMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 1294 #define regMMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0816 1295 #define regMMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 1296 #define regMMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0817 1297 #define regMMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 1298 #define regMMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0818 1299 #define regMMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 1300 #define regMMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0819 1301 #define regMMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 1302 #define regMMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x081a 1303 #define regMMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 1304 #define regMMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x081b 1305 #define regMMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 1306 1307 1308 // addressBlock: mmhub_mmutcl2_mmvml2pldec 1309 // base address: 0x6a090 1310 #define regMMMC_VM_L2_PERFCOUNTER0_CFG 0x0824 1311 #define regMMMC_VM_L2_PERFCOUNTER0_CFG_BASE_IDX 0 1312 #define regMMMC_VM_L2_PERFCOUNTER1_CFG 0x0825 1313 #define regMMMC_VM_L2_PERFCOUNTER1_CFG_BASE_IDX 0 1314 #define regMMMC_VM_L2_PERFCOUNTER2_CFG 0x0826 1315 #define regMMMC_VM_L2_PERFCOUNTER2_CFG_BASE_IDX 0 1316 #define regMMMC_VM_L2_PERFCOUNTER3_CFG 0x0827 1317 #define regMMMC_VM_L2_PERFCOUNTER3_CFG_BASE_IDX 0 1318 #define regMMMC_VM_L2_PERFCOUNTER4_CFG 0x0828 1319 #define regMMMC_VM_L2_PERFCOUNTER4_CFG_BASE_IDX 0 1320 #define regMMMC_VM_L2_PERFCOUNTER5_CFG 0x0829 1321 #define regMMMC_VM_L2_PERFCOUNTER5_CFG_BASE_IDX 0 1322 #define regMMMC_VM_L2_PERFCOUNTER6_CFG 0x082a 1323 #define regMMMC_VM_L2_PERFCOUNTER6_CFG_BASE_IDX 0 1324 #define regMMMC_VM_L2_PERFCOUNTER7_CFG 0x082b 1325 #define regMMMC_VM_L2_PERFCOUNTER7_CFG_BASE_IDX 0 1326 #define regMMMC_VM_L2_PERFCOUNTER_RSLT_CNTL 0x082c 1327 #define regMMMC_VM_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 1328 #define regMMUTCL2_PERFCOUNTER0_CFG 0x082d 1329 #define regMMUTCL2_PERFCOUNTER0_CFG_BASE_IDX 0 1330 #define regMMUTCL2_PERFCOUNTER1_CFG 0x082e 1331 #define regMMUTCL2_PERFCOUNTER1_CFG_BASE_IDX 0 1332 #define regMMUTCL2_PERFCOUNTER2_CFG 0x082f 1333 #define regMMUTCL2_PERFCOUNTER2_CFG_BASE_IDX 0 1334 #define regMMUTCL2_PERFCOUNTER3_CFG 0x0830 1335 #define regMMUTCL2_PERFCOUNTER3_CFG_BASE_IDX 0 1336 #define regMMUTCL2_PERFCOUNTER_RSLT_CNTL 0x0831 1337 #define regMMUTCL2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 1338 1339 1340 // addressBlock: mmhub_mmutcl2_mmvml2prdec 1341 // base address: 0x6a0e0 1342 #define regMMMC_VM_L2_PERFCOUNTER_LO 0x0838 1343 #define regMMMC_VM_L2_PERFCOUNTER_LO_BASE_IDX 0 1344 #define regMMMC_VM_L2_PERFCOUNTER_HI 0x0839 1345 #define regMMMC_VM_L2_PERFCOUNTER_HI_BASE_IDX 0 1346 #define regMMUTCL2_PERFCOUNTER_LO 0x083a 1347 #define regMMUTCL2_PERFCOUNTER_LO_BASE_IDX 0 1348 #define regMMUTCL2_PERFCOUNTER_HI 0x083b 1349 #define regMMUTCL2_PERFCOUNTER_HI_BASE_IDX 0 1350 1351 1352 // addressBlock: mmhub_mmutcl2_mmvmsharedhvdec 1353 // base address: 0x6a130 1354 #define regMMMC_VM_FB_SIZE_OFFSET_VF0 0x084c 1355 #define regMMMC_VM_FB_SIZE_OFFSET_VF0_BASE_IDX 0 1356 #define regMMMC_VM_FB_SIZE_OFFSET_VF1 0x084d 1357 #define regMMMC_VM_FB_SIZE_OFFSET_VF1_BASE_IDX 0 1358 #define regMMMC_VM_FB_SIZE_OFFSET_VF2 0x084e 1359 #define regMMMC_VM_FB_SIZE_OFFSET_VF2_BASE_IDX 0 1360 #define regMMMC_VM_FB_SIZE_OFFSET_VF3 0x084f 1361 #define regMMMC_VM_FB_SIZE_OFFSET_VF3_BASE_IDX 0 1362 #define regMMMC_VM_FB_SIZE_OFFSET_VF4 0x0850 1363 #define regMMMC_VM_FB_SIZE_OFFSET_VF4_BASE_IDX 0 1364 #define regMMMC_VM_FB_SIZE_OFFSET_VF5 0x0851 1365 #define regMMMC_VM_FB_SIZE_OFFSET_VF5_BASE_IDX 0 1366 #define regMMMC_VM_FB_SIZE_OFFSET_VF6 0x0852 1367 #define regMMMC_VM_FB_SIZE_OFFSET_VF6_BASE_IDX 0 1368 #define regMMMC_VM_FB_SIZE_OFFSET_VF7 0x0853 1369 #define regMMMC_VM_FB_SIZE_OFFSET_VF7_BASE_IDX 0 1370 #define regMMMC_VM_FB_SIZE_OFFSET_VF8 0x0854 1371 #define regMMMC_VM_FB_SIZE_OFFSET_VF8_BASE_IDX 0 1372 #define regMMMC_VM_FB_SIZE_OFFSET_VF9 0x0855 1373 #define regMMMC_VM_FB_SIZE_OFFSET_VF9_BASE_IDX 0 1374 #define regMMMC_VM_FB_SIZE_OFFSET_VF10 0x0856 1375 #define regMMMC_VM_FB_SIZE_OFFSET_VF10_BASE_IDX 0 1376 #define regMMMC_VM_FB_SIZE_OFFSET_VF11 0x0857 1377 #define regMMMC_VM_FB_SIZE_OFFSET_VF11_BASE_IDX 0 1378 #define regMMMC_VM_FB_SIZE_OFFSET_VF12 0x0858 1379 #define regMMMC_VM_FB_SIZE_OFFSET_VF12_BASE_IDX 0 1380 #define regMMMC_VM_FB_SIZE_OFFSET_VF13 0x0859 1381 #define regMMMC_VM_FB_SIZE_OFFSET_VF13_BASE_IDX 0 1382 #define regMMMC_VM_FB_SIZE_OFFSET_VF14 0x085a 1383 #define regMMMC_VM_FB_SIZE_OFFSET_VF14_BASE_IDX 0 1384 #define regMMMC_VM_FB_SIZE_OFFSET_VF15 0x085b 1385 #define regMMMC_VM_FB_SIZE_OFFSET_VF15_BASE_IDX 0 1386 1387 1388 // addressBlock: mmhub_mmutcl2_mmvmsharedpfdec 1389 // base address: 0x6a340 1390 #define regMMMC_VM_FB_OFFSET 0x08d7 1391 #define regMMMC_VM_FB_OFFSET_BASE_IDX 0 1392 #define regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0x08d8 1393 #define regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX 0 1394 #define regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0x08d9 1395 #define regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX 0 1396 #define regMMMC_VM_STEERING 0x08da 1397 #define regMMMC_VM_STEERING_BASE_IDX 0 1398 #define regMMMC_MEM_POWER_LS 0x08dc 1399 #define regMMMC_MEM_POWER_LS_BASE_IDX 0 1400 #define regMMMC_VM_CACHEABLE_DRAM_ADDRESS_START 0x08dd 1401 #define regMMMC_VM_CACHEABLE_DRAM_ADDRESS_START_BASE_IDX 0 1402 #define regMMMC_VM_CACHEABLE_DRAM_ADDRESS_END 0x08de 1403 #define regMMMC_VM_CACHEABLE_DRAM_ADDRESS_END_BASE_IDX 0 1404 #define regMMMC_VM_LOCAL_SYSMEM_ADDRESS_START 0x08df 1405 #define regMMMC_VM_LOCAL_SYSMEM_ADDRESS_START_BASE_IDX 0 1406 #define regMMMC_VM_LOCAL_SYSMEM_ADDRESS_END 0x08e0 1407 #define regMMMC_VM_LOCAL_SYSMEM_ADDRESS_END_BASE_IDX 0 1408 #define regMMMC_VM_APT_CNTL 0x08e1 1409 #define regMMMC_VM_APT_CNTL_BASE_IDX 0 1410 #define regMMMC_VM_LOCAL_FB_ADDRESS_START 0x08e2 1411 #define regMMMC_VM_LOCAL_FB_ADDRESS_START_BASE_IDX 0 1412 #define regMMMC_VM_LOCAL_FB_ADDRESS_END 0x08e3 1413 #define regMMMC_VM_LOCAL_FB_ADDRESS_END_BASE_IDX 0 1414 #define regMMMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL 0x08e4 1415 #define regMMMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL_BASE_IDX 0 1416 #define regMMUTCL2_CGTT_CLK_CTRL 0x08e5 1417 #define regMMUTCL2_CGTT_CLK_CTRL_BASE_IDX 0 1418 #define regMMUTCL2_CGTT_BUSY_CTRL 0x08e7 1419 #define regMMUTCL2_CGTT_BUSY_CTRL_BASE_IDX 0 1420 #define regMMMC_VM_FB_NOALLOC_CNTL 0x08e8 1421 #define regMMMC_VM_FB_NOALLOC_CNTL_BASE_IDX 0 1422 #define regMMUTCL2_HARVEST_BYPASS_GROUPS 0x08e9 1423 #define regMMUTCL2_HARVEST_BYPASS_GROUPS_BASE_IDX 0 1424 #define regMMUTCL2_GROUP_RET_FAULT_STATUS 0x08eb 1425 #define regMMUTCL2_GROUP_RET_FAULT_STATUS_BASE_IDX 0 1426 1427 1428 // addressBlock: mmhub_mmutcl2_mmvmsharedvcdec 1429 // base address: 0x6a3b0 1430 #define regMMMC_VM_FB_LOCATION_BASE 0x08ec 1431 #define regMMMC_VM_FB_LOCATION_BASE_BASE_IDX 0 1432 #define regMMMC_VM_FB_LOCATION_TOP 0x08ed 1433 #define regMMMC_VM_FB_LOCATION_TOP_BASE_IDX 0 1434 #define regMMMC_VM_AGP_TOP 0x08ee 1435 #define regMMMC_VM_AGP_TOP_BASE_IDX 0 1436 #define regMMMC_VM_AGP_BOT 0x08ef 1437 #define regMMMC_VM_AGP_BOT_BASE_IDX 0 1438 #define regMMMC_VM_AGP_BASE 0x08f0 1439 #define regMMMC_VM_AGP_BASE_BASE_IDX 0 1440 #define regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR 0x08f1 1441 #define regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 0 1442 #define regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x08f2 1443 #define regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 0 1444 #define regMMMC_VM_MX_L1_TLB_CNTL 0x08f3 1445 #define regMMMC_VM_MX_L1_TLB_CNTL_BASE_IDX 0 1446 1447 1448 // addressBlock: mmhub_mmutcl2_mmatcl2pfcntrdec 1449 // base address: 0x6a400 1450 #define regMM_ATC_L2_PERFCOUNTER_LO 0x0900 1451 #define regMM_ATC_L2_PERFCOUNTER_LO_BASE_IDX 0 1452 #define regMM_ATC_L2_PERFCOUNTER_HI 0x0901 1453 #define regMM_ATC_L2_PERFCOUNTER_HI_BASE_IDX 0 1454 1455 1456 // addressBlock: mmhub_mmutcl2_mmatcl2pfcntldec 1457 // base address: 0x6a420 1458 #define regMM_ATC_L2_PERFCOUNTER0_CFG 0x0908 1459 #define regMM_ATC_L2_PERFCOUNTER0_CFG_BASE_IDX 0 1460 #define regMM_ATC_L2_PERFCOUNTER1_CFG 0x0909 1461 #define regMM_ATC_L2_PERFCOUNTER1_CFG_BASE_IDX 0 1462 #define regMM_ATC_L2_PERFCOUNTER_RSLT_CNTL 0x090a 1463 #define regMM_ATC_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 1464 1465 1466 // addressBlock: mmhub_mmutcl2_mmvml2pspdec 1467 // base address: 0x6aa50 1468 #define regMMUTCL2_TRANSLATION_BYPASS_BY_VMID 0x0a94 1469 #define regMMUTCL2_TRANSLATION_BYPASS_BY_VMID_BASE_IDX 0 1470 #define regMMUTC_TRANSLATION_FAULT_CNTL0 0x0a99 1471 #define regMMUTC_TRANSLATION_FAULT_CNTL0_BASE_IDX 0 1472 #define regMMUTC_TRANSLATION_FAULT_CNTL1 0x0a9a 1473 #define regMMUTC_TRANSLATION_FAULT_CNTL1_BASE_IDX 0 1474 #define regMMUTCL2_FFBM_ENABLE_CNTL 0x0a9b 1475 #define regMMUTCL2_FFBM_ENABLE_CNTL_BASE_IDX 0 1476 1477 1478 // addressBlock: mmhub_mmutcl2_mml2tlbpspdec 1479 // base address: 0x6aa80 1480 #define regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL 0x0aa0 1481 #define regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL_BASE_IDX 0 1482 1483 1484 // addressBlock: mmhub_mmutcl2_mmatcl2pspdec 1485 // base address: 0x6aa90 1486 #define regMM_ATC_L2_IOV_MODE_CNTL 0x0aa4 1487 #define regMM_ATC_L2_IOV_MODE_CNTL_BASE_IDX 0 1488 1489 1490 // addressBlock: mmhub_mmutcl2_mml2tlbpfdec 1491 // base address: 0x6aac0 1492 #define regMML2TLB_TLB0_STATUS 0x0ab1 1493 #define regMML2TLB_TLB0_STATUS_BASE_IDX 0 1494 #define regMML2TLB_TMZ_CNTL 0x0ab2 1495 #define regMML2TLB_TMZ_CNTL_BASE_IDX 0 1496 #define regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO 0x0ab3 1497 #define regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO_BASE_IDX 0 1498 #define regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI 0x0ab4 1499 #define regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI_BASE_IDX 0 1500 #define regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO 0x0ab5 1501 #define regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO_BASE_IDX 0 1502 #define regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI 0x0ab6 1503 #define regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI_BASE_IDX 0 1504 #define regMMUTCL2_L2TLB_CREDIT_SAFETY_FETCH_RDREQ 0x0ab7 1505 #define regMMUTCL2_L2TLB_CREDIT_SAFETY_FETCH_RDREQ_BASE_IDX 0 1506 1507 1508 // addressBlock: mmhub_mmutcl2_mml2tlbpldec 1509 // base address: 0x6ab00 1510 #define regMML2TLB_PERFCOUNTER0_CFG 0x0ac0 1511 #define regMML2TLB_PERFCOUNTER0_CFG_BASE_IDX 0 1512 #define regMML2TLB_PERFCOUNTER1_CFG 0x0ac1 1513 #define regMML2TLB_PERFCOUNTER1_CFG_BASE_IDX 0 1514 #define regMML2TLB_PERFCOUNTER2_CFG 0x0ac2 1515 #define regMML2TLB_PERFCOUNTER2_CFG_BASE_IDX 0 1516 #define regMML2TLB_PERFCOUNTER3_CFG 0x0ac3 1517 #define regMML2TLB_PERFCOUNTER3_CFG_BASE_IDX 0 1518 #define regMML2TLB_PERFCOUNTER_RSLT_CNTL 0x0ac4 1519 #define regMML2TLB_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 1520 1521 1522 // addressBlock: mmhub_mmutcl2_mml2tlbprdec 1523 // base address: 0x6ab20 1524 #define regMML2TLB_PERFCOUNTER_LO 0x0ac8 1525 #define regMML2TLB_PERFCOUNTER_LO_BASE_IDX 0 1526 #define regMML2TLB_PERFCOUNTER_HI 0x0ac9 1527 #define regMML2TLB_PERFCOUNTER_HI_BASE_IDX 0 1528 1529 #endif 1530